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[AK4940] 018004574-E-00 2018/06 - 1 - 1. General Description The AK4940 is an audio CODEC with gain amplifier for microphone and analog direct path. It is ideal for data communication modules (DCM). The AK4940 is available in small 24-pin QFN (4 mm 4 mm, 0.5 mm pitch) package. 2. Features □ ADC: 24-bit Monaural ADC (with Microphone Gain Amplifier) - Sampling Frequency: fs = 8kHz to 48kHz - Analog Gain Amplifier for Microphones (-6 to 27dB, 3dB step) - Analog Input Selector - Differential Input/ Single-ended Input/ Pseudo Differential Input - ADC Characteristics: S/(N+D):80dB, S/N:90dB (fs=48kHz, Differential Input, MIC Gain=0dB) - Digital Volume (+24 to -103dB, 0.5dB Step, Mute) - Digital HPF for DC Offset Cancelling - Two Kinds of Digital Filters: Sharp Roll-Off Filter, Voice Filter □ DAC: 24-bit Monaural DAC (with Line Amplifier) - Sampling Frequency: fs=8kHz to 48kHz - Differential Output/ Pseudo Differential Output x2, Single-ended Output x1 - DAC Characteristics: S/(N+D): 80dB, S/N: 90dB (fs=48kHz, Single-ended Output) - Digital Volume (+12 to -115dB, 0.5dB Step, Mute) - Digital Filter: Sharp Roll-Off Filter □ Analog Direct Path - Switch Resistance: 300 (max.) - Signal Amplitude 3.0Vpp (max.) □ Audio Serial Interface: - Data Code: MSB First, 2’s complement - ADC: MSB justified / LSB justified / I2S / PCM Long Format / PCM Short Format - DAC: MSB justified / LSB justified / I2S / PCM Long Format / PCM Short Format □ Slave Operation □ PLL (Reference Clock BICK) □ μP Interface: I2C-bus (400kHz, Fast Mode) □ Power Supply: - Analog AVDD: 3.0 to 3.6V (typ. 3.3V) - Digital I/F TVDD: 1.7 to 3.6V (typ. 3.3V) □ Operation Temperature Range: -40C to 105C □ Package: 24-pin QFN (4mm x 4mm, 0.5mm pitch) 24-bit Mono CODEC with Analog Direct Path AK4940
[AK4940] 018004574-E-00 2018/06 - 2 - 3. Table of Contents
Figure 1. Block Diagram VREF Generate reference voltage VCOM (50% AVDD typ.). LDO Generate 1.2V (typ.) power supply for internal digital circuits. VCOM Amp. Supply reference voltage to internal analog circuits. MUX Select an analog signal from multiple analog signals. Analog Direct Path1/2 Connect analog input pin to analog output pin. Gain AMP + ADC Amplify analog input signal and Convert to digital data. DAC + Line-out Convert digital input data to analog signal and output it. PLL Multiply input BICK and generate internal master clock. CLKGEN & CONT Generate clocks for ADC block and DAC block operation.
- Pin Configurations and Functions
Figure 2. Pin Configuration
[AK4940] 018004574-E-00 2018/06 - 5 - ■ Pin Functions No. Pin Name I/O Functions Power-down Status
1 IN2P I
Analog Input Channel 2 Positive Differential: Analog Positive Signal Single-ended, Pseudo-differential: Analog Signal Hi-Z
2 IN1N I
Analog Input Channel 1 Negative Differential: Analog Negative Signal Single-ended: Connect a 10F capacitor between this pin and AVSS. Pseudo-differential: Connect a 10F capacitor between this pin and signal ground. Hi-Z
3 IN1P I
Analog Input Channel 1 Positive Differential: Analog Positive Signal Single-ended, Pseudo-differential: Analog Signal Hi-Z
4 TEST I TEST Mode Control
Connect to DVSS. This pin has 25k pull-down resister. Hi-Z
5 BICK I Serial Bit Clock Input Hi-Z
6 LRCK I LR Channel Select Clock Input Hi-Z
7 SDOUT O Audio Serial Data Output Pulled-down
by 50k
8 SDIN I Audio Serial Data Input Hi-Z
9 DVSS - Digital Ground -
10 TVDD - Digital I/O Power Supply, 1.7 - 3.6V -
11 SDA I/O I2C Bus Data Hi-Z
12 SCL I I2C Bus Clock Input Hi-Z
13 PDN I Power Down
“L”: Power Down, “H”: Normal Operation Hi-Z
14 STO O Internal Status Output Pulled-down
by 50k
15 AVDRV O
Connect a 2.2F (30%) capacitor between this pin and DVSS. This pin must not be connected to external circuit. This capacitor must be low ESR (Ex. Ceramic Capacitor). The 2.2F (30%) includes the bias effect and the fluctuation with temperature. Pulled-down by 110
16 OUT2N O
Analog Output Channel 2 Negative Analog Direct Path: IN2N Signal DAC Line Output: Inverted Signal or VCOM Hi-Z
17 OUT2P O
Analog Output Channel 2 Positive Analog Direct Path: IN2P Signal DAC Line Output: Non-Inverted Signal Hi-Z
18 OUT3 O DAC Line Output (Single-ended) Hi-Z
19 OUT1N O
Analog Output Channel 1 Negative Analog Direct Path: IN1N Signal DAC Line Output: Inverted Signal or VCOM Hi-Z
20 OUT1P O
Analog Output Channel 1 Positive Analog Direct Path: IN1P Signal DAC Line Output: Non-Inverted Signal Hi-Z 21 AVDD - Analog Power Supply, LDO Power Supply, 3.0 - 3.6V -
22 VCOM O
Connect 2.2F (30%) capacitor between this pin and AVSS. This pin must not be connected to external circuit.
23 AVSS - Analog Ground -
24 IN2N I
Unused I/O pins must be connected appropriately. Table 1. Handing of Unused Pins
[AK4940] 018004574-E-00 2018/06 - 7 - 6. Absolute Maximum Ratings (AVSS=DVSS=0V; Note 1) Parameter Symbol Min. Max. Unit Power Supply Voltage Analog Digital(I/F) Difference (AVSS, DVSS) (Note 1) AVDD TVDD ΔGND 0.3 0.3 0.3 4.3 4.3 0.3 V V V Input Current (Except power supply pins) IIN － ±10 mA Analog Input Voltage (Note 2) VINA 0.3 (AVDD+0.3) or 4.3 V Digital Input Voltage (Note 3) VIND 0.3 (TVDD+0.3) or 4.3 V Ambient Temperature Ta 40 105 C Storage Temperature Tstg 65 150 C Note 1. All voltages are with respect to ground. AVSS and DVSS must be connected to the same analog ground plane. Note 2. IN1P, IN1N, IN2P, IN2N pins. The maximum analog input voltage is lower value between (AVDD+0.3V) and 4.3V. Note 3. PDN, LRCK, BICK, SDIN, SDA(I), SCL pins The maximum digital input voltage is lower value between (TVDD+0.3V) and 4.3V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (AVSS=DVSS=0V; Note 1) Parameter Symbol Min. Typ. Max. Unit Power Supply Analog Digital(I/F) Difference AVDD TVDD AVDD – TVDD 3.0 1.7 0.3 3.3 3.3 3.6 3.6 3.6 V V V Note 4. AVDD must be powered up before or at the same time of TVDD. The AK4940 must be powered up when the PDN pin = “L”. Set the PDN pin to “H” after all powers are supplied and stabilized. Note 5. Do not turn off the power supply of the AK4940 with the power supply of the surrounding device turned on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be connected to TVDD or less voltage. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4940] 018004574-E-00 2018/06 - 8 - 8. Analog Characteristics ■ Gain Amplifier (Ta=25C; AVDD=TVDD=3.3V; AVSS=DVSS=0V) Gain Amp. Parameter Min. Typ. Max. Unit Input Impedance (Differential) IN1P, IN1N, IN2P, IN2N pins 14 20 26 kΩ Input Impedance (Single-ended, Pseudo Differential) IN1P, IN2P pins 16 24 31 kΩ IN1N, IN2N pins 900 1300 1700 kΩ Gain dB MGN [3:0]bits=3h (0011) 1.5 3 4.5 MGN [3:0]bits=4h (0100) 4.5 6 7.5 MGN [3:0]bits=5h (0101) 7.5 9 10.5 MGN [3:0]bits=6h (0110) 10.5 12 13.5 MGN [3:0]bits=7h (0111) 13.5 15 16.5 MGN [3:0]bits=8h (1000) 16.5 18 19.5 MGN [3:0]bits=9h (1001) 19.5 21 22.5 MGN [3:0]bits=Ah (1010) 22.5 24 25.5 MGN [3:0]bits=Bh (1011) 25.5 27 28.5 MGN [3:0]bits= Others Not Available
[AK4940] 018004574-E-00 2018/06 - 9 - ■ Gain Amplifier + ADC (Ta=25C; AVDD=TVDD=3.3V; AVSS=DVSS=0V; Signal Frequency=1kHz; 24bit Data; BICK=64fs; fs=48kHz; Measurement Frequency BW=20Hz ~ 20kHz; Amp Gain=0dB) Note 6. Full-scale voltage is proportional to AVDD. Note 7. PSRR is referred to AVDD and TVDD with 1kHz, 100 mVpp sine wave. Note 8. CMRR is referred to INnP and INnN (n= 1, 2) with 1kHz, 100 mVpp in-pahse sine wave. These are relative values to the output level when inputting 1kHz, 100mVpp sine wave. Note 9. Pseudo differential Input. CMRR is referred to INnP and INnN (n= 1, 2) with 1kHz, 100 mVpp sine wave. These are relative values to the output level when inputting 1kHz, 100mVpp sine wave. Gain AMP ADC Parameter Min. Typ. Max. Unit Resolution - - 24 bit Differential Input Input Full-scale Voltage (Note 6) Sharp Roll-off Filter (VOAD bit=“0”) ±2.0 ±2.2 ±2.4 Vpp Voice Filter (VOAD bit=“1”) ±2.07 ±2.28 ±2.48 Vpp S/(N+D) 1dBFS 72 80 - dB Dynamic Range 60dBFS, A-weighted 82 90 - dB S/N A-weighted 82 90 - dB PSRR (Note 7) - 50 - dB CMRR (Note 8) 60 80 - dB Single-ended Input, Pseudo Differential Input Input Full-scale Voltage (Note 6) Sharp Roll-off Filter (VOAD bit=“0”) 2.0 2.2 2.4 Vpp Voice Filter (VOAD bit=“1”) 2.07 2.28 2.48 Vpp S/(N+D) 1dBFS 72 80 - dB Dynamic Range 60dBFS, A-weighted 82 90 - dB S/N A-weighted 82 90 - dB PSRR (Note 7) - 50 - dB CMRR (Note 9) 55 75 - dB
[AK4940] 018004574-E-00 2018/06 - 10 - ■ DAC + Lineout (Ta=25C; AVDD=TVDD=3.3V; AVSS=DVSS=0V; Signal Frequency=1kHz; 24bit Data; BICK=64fs; fs=48kHz; Measurement Frequency BW=20Hz ~ 20kHz) DAC Line-out Parameter Min. Typ. Max. Unit Resolution - - 24 bit Output Full-scale Voltage (Note 10) Differential (Note 11) ±2.55 ±2.76 ±3.11 Vpp Single Ended, Pseudo Differential (Note 12) 2.55 2.76 3.11 Vpp S/(N+D) 0dBFS 72 80 - dB Dynamic Range 60dBFS, A-weighted 82 90 - dB S/N A-weighted 82 90 dB Channel Gain Mismatch (Note 13) - 0.0 0.5 dB Load Resistance (Note 14) 10 - - kΩ Load Capacitance - - 30 pF PSRR (Note 7) - 50 - dB Note 7. PSRR is referred to AVDD and TVDD with 1kHz, 100 mVpp sine wave. Note 10. Full-scale voltage is proportional to AVDD. Note 11. Output voltage between OUTxP pin and OUTxN pin (x = 1, 2) in differential output mode (OUTNSEL bit = “0”). Note 12. Output voltage at the OUT1P, OUT1N, OUT2P, OUT2N and OUT3 pins in single-ended ouptut mode or pseudo diferential output mode (OUTNSEL bit = “1”). Note 13. Channel gain mismatch between the OUT1P pin and OUT1N pin, the OUT2P pin and OUT2N pin when 0dBF is output.. Note 14. against AC load ■ Analog Direct Path (Ta=25C; AVDD=TVDD=3.0~3.6V; AVSS=DVSS=0V; Signal Frequency=1kHz; Measurement Frequency BW=20Hz ~ 20kHz) Note 15. AC signal amplitude after reducing DC signal via Input capacitor. ■ Consumption Current ADC ON; DAC ON; Line-out ON; CL=20pF(Digital Output); RL=10kΩ(Line Output)) Parameter Symbol Min. Typ. Max. Unit Power Supply Current Normal Operation, PDN Pin= “H” AVDD - 11.4 20 mA TVDD - 1 2 mA Power Supply Current Power Down State, PDN Pin= “L” AVDD - 1 10 A TVDD - 1 10 A Note 16. Consumption current depends on operation frequency. Analog Switch Parameter Min. Typ. Max. Unit Input PIN to Output PIN Pin to Pin Impedance - - 300 Ω Signal Amplitude (Note 15) - - 3.0 Vpp Load Resistance (Note 14) 10 - - kΩ
[AK4940] 018004574-E-00 2018/06 - 11 - 9. Digital Filter Characteristics ■ ADC (Ta= -40~105C; AVDD=3.0~3.6V; TVDD=1.7~3.6V; AVSS=DVSS=0V) Sharp Roll-Off Filter (VOAD bit = “0”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 17) +0.14dB/0.12dB PB 0 - 20.7 kHz 3.0dB PB - 22.8 - kHz Stopband (Note 17) SB 28.4 - - kHz Stopband Attenuation SA 65 - - dB Group Delay Distortion : 0Hz~20kHz GD - 0 - 1/fs Group Delay (Note 18) GD - 16.5 - 1/fs ADC Digital Filter(HPF) Frequency Response (Note 17) 3.0dB FR - 3.7 - Hz Voice Filter (VOAD bit = “1”) fs=16kHz Parameter Symbol Min. Typ. Max. Unit VOICE Passband (Note 17) 0.5dB/0.5dB PB 0 - 6.3 kHz 3.0dB - 6.9 - kHz Stopband (Note 17) SB 8.0 - - kHz Stopband Attenuation SA 59.5 - - dB Group Delay Distortion : 0Hz~8kHz GD - 0 - 1/fs Group Delay (Note 18) GD - 18.1 - 1/fs ADC Digital Filter(HPF) Frequency Response (Note 17) 3.0dB FR - 1.24 - Hz Note 17. Frequencies of Passband, Stopband and frequency response of HPF scale with fs (system sampling rate). HPF characteristics are not included to Passband and Stopband. Note 18. The calculated delay time caused by digital filtering. This time is from the input of analog signal to the output of MSB at the SDTO pin.
[AK4940] 018004574-E-00 2018/06 - 12 - ■ DAC (Ta= 40~105C; AVDD = 3.0~3.6V; TVDD =1.7~3.6V; AVSS = DVSS = 0V) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 19) 0.05dB PB 0 - 21.7 kHz 6.0dB PB - 24 - kHz Passband Ripple PR - 0.05 dB Stopband (Note 19) SB 26.2 - - kHz Stopband Attenuation (Note 20, Note 22) SA 64 - - dB Group Delay (Note 21) GD - 24 - 1/fs Digital Filter + SCF + SMF (Note 20) Frequency Response : 0 20.0kHz - - 0.5 - dB Note 19. Passband and stopband frequencies scale with fs (system sampling rate). PB max. = 0.4535fs, SB min. = 0.546fs Note 20. The output level when inputting a 1kHz, 0dB sine wave is defined as 0dB. Note 21. This time is from the input of impulse data to the output of analog peak signal. Note 22. from 0kHz to fs 10. DC Characteristics (Ta=40~105C; AVDD = 3.0~3.6V; TVDD =1.7~3.6V; AVSS= DVSS = 0V) Parameter Symbol Min. Typ. Max. Unit Normal Pin (Except for SBDATA and SBCLK Pins) High Level Input Voltage 1 (Note 23) VIH1 75%TVDD - - V Low Level Input Voltage 1 (Note 23) VIL1 - - 25%TVDD V High Level Input Voltage 2 (Note 24) VIH2 70%TVDD - - V Low Level Input Voltage 2 (Note 24) VIL2 - - 30%TVDD V High Level Output Voltage Iout= 100A (Note 25) VOH1 TVDD0.3 - - V Low Level Output Voltage Iout=100A (Note 25) VOL1 - - 0.3 V SDA Low Level Output Voltage TVDD2.0V (Iout=3mA) VOL2 - - 0.4 V TVDD<2.0V (Iout=3mA) VOL2 - - 20%TVDD V Input Leakage Current (Note 26) Iin - - ±10 A Note 23. PDN, SDIN, BICK, LRCK and TEST pins Note 24. SCL and SDA pins Note 25. SDOUT and STO pins Note 26. PDN, SDIN, BICK, LRCK, SCL and SDA (I) pins
- Switching Characteristics
Note 27. fBCLK must be higher than 2fs(IO Data Length). Figure 3. System Clock Timing Note 28. When the polarity of BCLKx is inverted, delay time is counted from BCLKx “”. Note 29. When the polarity of BCLKx is inverted, delay time is counted from BCLKx “”.
Figure 7. I2C BUS Interface Timing
LRCK are defined as system clocks. A clock for sampling frequency (fs) is input to the LRCK pin. Set DFS[2:0] bits according to the fs clock. The AK4940 integrates PLL and generates internal master clock from the input clock of the BICK pin. BITFS[1:0] bits that are for BICK frequency setting. Table 2. PLL Reference Clock (BICK) Frequency Note 31. When BICK is 48fs, sampling frequency cannot be set 12kHz or 11.025kHz. Table 3. Internal Master Clock
MSB justified, LSB justified, I2S compatible and PCM. Table 4. Audio Serial Interface Format Setting
01 LSB Justified 24-bit 48fs
01 LSB Justified 20-bit 48fs
00 LSB Justified 16-bit 64fs
01 LSB Justified 16-bit 48fs
10 LSB Justified 16-bit 32fs
01 I2S Compatible 24-bit 48fs
BICK edge direction at LRCK starting edge can be set by the BCKP pin. Table 5. BICK Edge Direction at LRCK Start Edge
0 Falling (default)
1 Rising
is stopped when PMAD/PMDA bit = “0”. The default value of PMAD and PMDA bits are “0”. Table 6. Device State (x: Don’t Care) Note 32. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “0” → “1”).
setting each power-management bit. stabilization of PLL after clock reset is released. Figure 17. Clock Mode Switching Sequence
with an interval of 1ms or more after the PDN pin = “H”. Figure 18. Power Up Sequence until the AK4940 is reset by the PDN pin.
voltage goes off from VCOM voltage. OUT3SEL[1:0] bits and OUTNSEL bit. Table 7. Analog Output Signal Select
01 X Analog Direct Path1 Connected to IN1P pin
11 X N/A N/A N/A
01 X Analog Direct Path2 Connected to IN2P pin
01 X DAC Single-ended Output DAC Lineout (+)
11 X N/A N/A
Figure 19. Analog Output Selector
The amplifier should be adjusted not to exceed the input full scale of the ADC. Table 8. Gain Setting pin that is not selected by ADCSEL bit is connected to VCOM voltage via 0.8 k (typ.) resistance. ADC operation starts since the reference voltage of input pin goes off from VCOM voltage.
differential input modes by setting ADDIFFN bit. Input channels are selected by ADCSEL bit. Figure 20. Analog Input Selector Table 9. ADC Input Setting
0 Differential (default) 0 IN1P, IN1N (default)
1 Single-End, Pseudo-Differential 1 IN2P, IN2N
1059/fs and the AK4940 starts outputting A/D data. the HPF is 3.7Hz (typ.) when fs = 48kHz. It is proportional to fs. ADC block has two kinds of digital filters and they can be selected by VOAD bit. Table 10. ADC Digital Filter Select
0 Sharp Roll-Off Filter (default)
1 Voice Filter
Digital volume control (256 level, 0.5dB) is available at the output block of the ADC. Table 11. VOLAD[7:0] bits vs ADC Digital Volume Level during these transitions. Digital volume transition speed is controlled by ATSPAD bit. Table 12. ADC Digital Volume Transition Speed It takes 1020/fs (21.3ms@fs=48kHz) from 00h (24dB) to FFh (Mute) when ATSPAD bit = “0”. Table 13. ADC Volume Transition Time between 00h and FFh
the OUT1N and the OUT2N pins with the OUT1P and the OUT2P pins, respectively. The AK4940 has digital volume control at DAC input block. (256 levels, 0.5 steps). Table 14. VOLDA[7:0] bits vs DAC Digital Volume Level during these transitions. The transition time between set values is selected by ATSPDA bit. Table 15. DAC Digital Volume Transition Speed
When ATSPDA bit = “0”, it takes 1020/fs (21.3ms@fs=48kHz) from 00H (0dB) to FFH (MUTE). Table 16. DAC Volume Transition Time between 00h and FFh cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. available when the DAC is in operation. Figure 23. DAC Soft Mute Operation system clocks can be avoided. It is possible to invert the DAC output polarity by INV bit. Table 17. DAC Output Polarity
0 Non-Invert (default)
1 Invert
The second byte consists of the control register address of the AK4940 and the format is MSB first. while SCL is HIGH defines a STOP condition (Figure 30). counter will “roll over” to “00H” and the previous data will be overwritten. the START and STOP conditions. Figure 24. Data Transfer Sequence at the I2C-Bus Figure 25. The First Byte
0 A6 A5 A4 A3 A2 A1 A0
Figure 26. The Second Byte
[AK4940] 018004574-E-00 2018/06 - 36 - ■ Register Map Control registers can be initialized by setting the PDN pin = “L”. Do not write "1" into bits described as 0. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default 00h Clock Management 0 0 0 0 CKRESET N DFS2 DFS1 DFS0 00h 01h Audio I/F Setting LRIF1 LRIF0 DOFAD1 DOFAD0 DIFDA1 DIFDA0 BITFS1 BITFS0 00h 02h ADC Control BCKP 0 0 0 0 0 0 VOAD 00h 03h Line Out Control OUTNSEL INV OUT3SEL OUT3SEL OUT2SEL OUT2SEL
0 OUT1SEL1 OUT1SEL0 00h
04h Power Management 0 0 PMAD PMDA ADCSEL ADDIFFN 0 CRESETN 00h 05h Input Gain 0 0 0 0 MGN3 MGN2 MGN1 MGN0 02h 06h ADC Digital Volume VOLAD7 VOLAD6 VOLAD5 VOLAD4 VOLAD3 VOLAD2 VOLAD1 VOLAD0 30h 07h DAC Digital Volume VOLDA7 VOLDA6 VOLDA5 VOLDA4 VOLDA3 VOLDA2 VOLDA1 VOLDA0 18h 08h Soft Mute Control 0 0 ADMUTE ATSPAD 0 0 DAMUTE ATSPDA 00h 09h Reserved 0 0 0 0 0 0 0 0 00h ■ Register Definitions Addr Name D7 D6 D5 D4 D3 D2 D1 D0 00h Clock Management 0 0 0 0 CKRESETN DFS2 DFS1 DFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 CKRESETN: Clock Reset 0: Clock Reset (default) 1: Clock Reset Release DFS[2:0]: Sampling Frequency Select DFS[2:0] fs 48kHz system 44.1kHz system 000 8kHz 7.35kHz (default) 001 12kHz 11.025kHz 010 16kHz 14.7kHz 011 24kHz 22.05kHz 100 32kHz 29.4kHz 101 48kHz 44.1kHz 11x N/A N/A
[AK4940] 018004574-E-00 2018/06 - 37 - Addr Name D7 D6 D5 D4 D3 D2 D1 D0 01h Audio I/F Setting LRIF1 LRIF0 DOFAD1 DOFAD0 DIFDA1 DIFDA0 BITFS1 BITFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LRIF[1:0]: Format Type Selection (Table 4) DOFAD[1:0]: ADC Data Length and Data Position Selection (Table 4) DIFDA[1:0]: DAC Data Length and Data Position Selection (Table 4) BITFS[1:0]: BICK Frequency Selection (Table 4) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 02h ADC Control BCKP 0 0 0 0 0 0 VOAD R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 BCKP: BICK Edge Direction on LRCK Start Edge 0: Falling Edge (default) 1: Rising Edge VOAD: ADC Digital Filter Selection 0: Sharp Roll-Off (default) 1: Voice Addr Name D7 D6 D5 D4 D3 D2 D1 D0 03h Line Out Control OUTNSEL INV OUT3SEL1 OUT3SEL0 OUT2SEL1 OUT2SEL0 OUT1SEL1 OUT1SEL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 OUTNSEL: DAC Lineout(-) Signal Selection (Table 7 (a), (b), (c)) INV: DAC Output Polarity Selection 0: Non-Invert (default) 1: Invert OUT3SEL[1:0]: OUT3 pin Output Selection (Table 7 (c)) OUT2SEL[1:0]: OUTP2/OUTN2 pins Output Selection (Table 7 (b)) OUT1SEL[1:0]: OUTP1/OUTN1 pins Output Selection (Table 7 (a))
[AK4940] 018004574-E-00 2018/06 - 38 - Addr Name D7 D6 D5 D4 D3 D2 D1 D0 04h Power Management 0 0 PMAD PMDA ADCSEL ADDIFFN 0 CRESETN R/W RW RW R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMAD: ADC Operation Selection 0: Reset State (default) 1: Normal Operation PMDA: DAC Operation Selection 0: Reset State (default) 1: Normal Operation ADCSEL: ADC Input Channel Selection 0: INP1, INN1 (default) 1: INP2, INN2 ADDIFFN: ADC Input Method Selection 0: Differential (default) 1: Single-ended, Pseudo-differential CRESETN: ADC &DAC Reset 0: Reset (default) 1: Normal Operation Addr Name D7 D6 D5 D4 D3 D2 D1 D0 05h Input Gain 0 0 0 0 MGN3 MGN2 MGN1 MGN0 R/W R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 MGN[3:0]: Input Block Amplifier Gain Setting (Table 8) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 06h ADC Digital Volume VOLAD7 VOLAD6 VOLAD5 VOLAD4 VOLAD3 VOLAD2 VOLAD1 VOLAD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 0 0 0 0 VOLAD[7:0]: ADC Block Digital Volume Setting (Table 11) Addr Name D7 D6 D5 D4 D3 D2 D1 D0 07h DAC Digital Volume VOLDA7 VOLDA6 VOLDA VOLDA4 VOLDA3 VOLDA2 VOLDA1 VOLDA0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 1 0 0 0 VOLDA[7:0]: DAC Block Digital Volume Setting (Table 14)
[AK4940] 018004574-E-00 2018/06 - 39 - Addr Name D7 D6 D5 D4 D3 D2 D1 D0 08h Soft Mute Control 0 0 ADMUTE ATSPAD 0 0 DAMUTE ATSPDA R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ADMUTE: ADC Block Soft Mute Control 0: Release Mute (default) 1: Start Mute ATSPAD: ADC Block Soft Mute Transition Speed Selection 0: 4/fs (default) 1: 16/fs DAMUTE: DAC Block Soft Mute Control 0: Release Mute (default) 1: Start Mute ATSPDA: DAC Block Soft Mute Transition Speed Selection 0: 4/fs (default) 1: 16/fs
Figure 35. Pseudo-Differential Input 2ch, Pseudo-Differential Output 2ch, Single-ended Output 1ch
[AK4940] 018004574-E-00 2018/06 - 42 - 1. Ground AVSS and DVSS should be connected to the same ground. Decoupling capacitors, particularly capacitors of small capacity, should be placed at positions as close as possible to the AK4940. 2. Reference Voltage VCOM is a common voltage of this chip and the VCOM pin outputs AVDD/2. A 2.2µF capacitor should be connected between the VCOM pin and AVSS. Do not connect the VCOM pin to any external devices except the 2.2µF capacitor. Digital signal lines, especially clock signal line should be kept away as far as possible from this pin in order to avoid unwanted coupling into the AK4940. 3. Analog Input The internal operating point level at the analog input pins of the AK4940 is VCOM voltage (AVDD/2). Concerning the internal operating point formation circuit, each input pin has impedance of 20k (typ.) for the IN1P, and IN2P pins and 0.8 k (typ.) for the IN1N and IN2N pins. After power-down is released, each analog input pin that is connected to an AC coupling capacitor becomes the same level as VCOM voltage by the impedance and required start-up time (time-constant). The AK4940 samples the analog inputs at 512kHz when fs=8kHz. Digital filters remove noise around from 5kHz to 512kHz. The AK4940 includes a low-pass filter (fc=50kHz). This filter attenuates noises around 509.5kHz ~ 512kHz, which are not removed by the digital filters. Therefore no external low-pass filter is needed in front of the ADC since most of audio signals do not have a large noise around 509.5kHz. However, an external low-pass filter should be connected before the ADC for a signal which has large out-of-band noise such as D/A converted audio signals. Digital output code is 2‘s complement. DC offset is cancelled by the internal HPF. The analog power supply to the AK4940 is +3.3V typical. A voltage more than AVDD + 0.3V or less than AVSS - 0.3V, and a current more than 10mA must not be applied to analog input pins. Excessive current will damage the internal protection circuit and will cause latch-up, destroying the IC. Accordingly, if the external analog circuit voltage is ±15V, the analog input pins must be protected from signals which are equal or larger than absolute maximum ratings. 4. Analog Output The analog output corresponds to both single-ended and differential outputs; it can be controlled by register setting. The digital input data format is two’s compliment. Positive full-scale output corresponds to 7FFFFFh (@24bit) input code, negative full-scale is 800000h (@24bit) and VCOM voltage ideally is 000000h (@24bit). The out-of-band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated by an internal filter.
[AK4940] 018004574-E-00 2018/06 - 43 - 14. Package ■ Outline Dimensions 24-pin QFN (Unit: mm) ■ Material and Lead Finish Package molding compound: Epoxy resin Lead frame materials: Cu Pin surface treatment: Solder (Pb free) plate ■ Marking 1) Pin #1 indication 2) Date Code : XXXX (4 digits) 3) Marketing Code : 4940 4) AKM Logo: AKM AKM 4940 XXXX
[AK4940] 018004574-E-00 2018/06 - 44 - 15. Ordering Guide AK4940VN 40 ~ +105°C 24-pin QFN (0.5mm pitch) AKD4940 Evaluation Board for the AK4940 16. Revision History Date (Y/M/D) Revision Reason Page Contents 18/06/21 00 First Edition
[AK4940] 018004574-E-00 2018/06 - 45 - IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document ( “Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this d ocument. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodi ly injury, serious property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transporta tion, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance -related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in p art, without prior written consent of AKM.