AK4710 AKM | Alldatasheet
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Technical content
[AK4710] Rev. 0.3 2011/07 - 1 -
FEATURES
THD+N: −92dB (@2Vrms) Dynamic Range: 96dB (@2Vrms, A-weighted) Full Differential or Single-ended input for Decoder DAC Stereo Output for TV SCART and CINCH (2Vrms) Ground-Referenced Output Eliminates DC-Blocking Capacitor and Mute Circuit Video section Integrated LPF: –40dB@27MHz 6dB Gain for Outputs 5ch 75ohm driver 4ch for SCART: CVBS/Y, R/C, G, B 1ch for CINCH: CVBS Y/Pb/Pr Option (to 6MHz) Low-power Standby SCART pin#16(Fast Blanking), pin#8(Slow Blanking) Output Control Power supply Low Power Dissipation / Low Power Standby Mode Package 32pin QFN (0.4mm pitch) Low Power Single SCART Driver AK4710 = Preliminary =
[AK4710] Rev. 0.3 2011/07 - 2 - ■ Block Diagram TVOUTL TVOUTR AI NL+ AI NL- AI NR- AI NR+ MONO SCL SDA Register Control PDN VD1 AMP VSS1 Volume -6dB to +24dB (3dB/step) CP CN VEE VSS2 Charge Pump VD2 TV SCART CINCH Audio Audio Block ENC C TVRC ENC G/CVBS TVG ENC B/Pb TVB ENC Y TVVOUT 6dB ENC R/C/Pr RCAVOUT ENC CVBS/Y ENCC ENCG ENCB ENCY ENCRC ENCV ( Typical connection ) TV SCART CINCH Video ( Typical connection ) VSS3 VVD 6dB 6dB 6dB 6dB 6:5 Selector Video Block TVFB 6dB 1.25V TVSB 0/ 6/ 12V TV S CART ( Typical connection ) VP Video Blanking Block
[AK4710] Rev. 0.3 2011/07 - 3 - ■ Ordering Guide AK4710EN -10 ∼ +70°C 32pin QFN (0.4mm pitch) AKD4710 Evaluation board for AK4710 ■ Pin Layout 32pin QFN (0.4mm pitch) VD2 VEE CN CP VSS2 SCL 24 23 22 21 20 19 18 17 1 2 RCAVOUT 3VSS3 4TVVOUT 5TVFB 6TVRC 7TVG 8TVB ENCB Top View AK4710 ENRC ENCG ENCV ENCC VP ENCY AINL- AINR+ AINR- TVOUTL TVOUTR VD1 VSS1 SDA AINL+ TVSB VVD PDN
[AK4710] Rev. 0.3 2011/07 - 4 - PIN/FUNCTION No. Pin Name I/O Function PDN I Power-Down Mode Pin When at “L”, the AK4710 is in the power-down mode and is held in reset. The AK4710 should always be reset upon power-up.
2 RCAVOUT O Composite/Luminance Output Pin for RCA
3 VSS3 - Video Ground Pin , 0V
4 TVVOUT O Composite/Luminance Output Pin for TV
5 TVFB O Fast Blanking Output Pin for TV
6 TVRC O Red/Chrominance Output Pin for TV
7 TVG O Green Output Pin for TV
8 TVB O Blue Output Pin for TV
9 VVD -
Video Power Supply Pin: 3.13V ~ 3.47V Normally connected to VSS3 with a 0.1μF ceramic capacitor in parallel with a 4.7μF electrolytic capacitor.
10 ENCB I Blue Input Pin for Encoder
11 ENCG I Green Input Pin for Encoder
12 ENCRC I Red/Chrominance Input Pin #1 for Encoder
13 ENCC I Chrominance Input Pin #2 for Encoder
14 ENCV I Composite/Luminance Input Pin #1 for Encoder
15 ENCY I Composite/Luminance Input Pin #2 for Encoder
16 VP -
Blanking Power Supply Pin, 10.8V ~ 13.2V The VP pin must connect to power supply through 10ohm resistor with 0.1μF ceramic capacitor in parallel with a 1μF electrolytic capacitor to VSS1.
17 TVSB O
Slow Blanking Output Pin for TV A 470ohm ±5% resistor must be connected between the TVSB pin and SCART connector.
18 VSS1 - Audio Ground Pin , 0V
19 VD1 -
Audio Power Supply Pin: 3.13V ~ 3.47V Normally connected to VSS1 with a 0.1μF ceramic capacitor in parallel with a 4.7μF electrolytic capacitor.
20 TVOUTR O Rch Anal og Output Pin #2
21 TVOUTL O Lch Analog Output Pin #2
22 AINRN I Rch Negative Analog Input Pin
23 AINRP I Rch Positive Analog Input Pin
24 AINLN I Lch Negative Analog Input Pin
25 AINLP I Lch Positive Analog Input Pin
[AK4710] Rev. 0.3 2011/07 - 5 -
26 VEE O
Negative Voltage Output Pin Connect to VSS2 with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used.
27 CN I
Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used.
28 CP I
Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used.
29 VSS2 - Charge Pump Ground Pin , 0V
30 VD2 -
Charge Pump Power Supply Pin: 3.13V ~ 3.47V Normally connected to VSS2 with a 0.1μF ceramic capacitor in parallel with a 4.7μF electrolytic cap.
31 SCL I Control Data Clock Pin
32 SDA I/O Control Data Pin
Note: All digital input pins should not be left floating.
Note 1. All voltages with respect to ground. Note 2. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane. Note 3. VEE: VEE pin voltage. The internal negative power supply generating circuit provides negative power supply(VEE).
0 Full Power-down 0V
1 Mute 0V
Table 1. VEE pin voltage WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
[AK4710] Rev. 0.3 2011/07 - 7 - RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3= 0V; Note 1) Parameter Symbol Min typ max Units Power Supply (Note 4) VD1 VD2 VVD VP 3.13 3.13 3.13 10.8 3.3 3.3 3.3 3.47 3.47 3.47 13.2 V V V V Note 1. All voltages with respect to ground. Note 4. VVD must be connected to the same voltage. *AKM assumes no responsibility for the usage beyond recommended operating conditions in this datasheet.
ELECTRICAL CHARACTERISTICS
(Ta = 25°C; VP=12V, VD1=VD2=VVD= 3.3V) Power Supplies min typ max Units Power Supply Current Normal Operation (PDN = “H”) ( Note 5) VD1+VD2+VVD VP Power-Down Mode (PDN = “L”) ( Note 6) VD1+VD2 VVD VP 386 TBD TBD TBD TBD TBD μA μA μA μA μA Note 5. All video outputs active. No signal, no load for A/V switches, refer to the Table 3. Note 6. All digital inputs are held at VVD or VSS3. No signal, no load for A/V switches. DIGITAL CHARACTERISTICS (Ta = 25°C; VD1=VD2=VVD= 3.13 ∼ 3.47V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%VVD 30%VVD V V Low-Level Output Voltage (SDA pin: Iout= 3mA) VOL - - 0.4 V Input Leakage Current Iin - - ± 10 μA
[AK4710] Rev. 0.3 2011/07 - 8 - ANALOG CHARACTERISTICS (AUDIO) (Ta=25°C; VP=12V, VD1=VD2=VVD =3.3V; Signal Frequency=1kHz; Measurement frequency=20Hz ∼ 20kHz; RL ≥4.5kΩ; 0dB=2Vrms output; Volume=0dB, unless otherwise specified) Parameter min typ max Units Analog Input: (AINL+/AINL-/AINR-/AINR+ pins) Analog Input Characteristics Input Voltage (AIN+) − (AIN−), (Note 7) 2.0 Vrms Input Resistance (AINL+, AINR+ pins) 85 120 kΩ Input Resistance (AINL-, AINR- pins) 85 120 - kΩ Stereo/Mono Output: (TVOUTL/TVOUTR pins) (Note 8) Analog Output Characteristics Volume Step Width 2.3 3.0 3.7 dB THD+N (at 2Vrms output, Note 10, Note 12) −92 -80 dB Dynamic Rang (−60dB Output, A-weighted, Note 10) 92 96 dB S/N (A-weighted, Note 10, Note 14) 92 96 dB Interchannel Isolation ( Note 10, Note 11) 80 90 dB Interchannel Gain Mismatch (Note 10, Note 11) -0.5 0 +0.5 dB DC offset ( Note 13) -5 0 +5 mV Gain Drift - 200 - ppm/°C Load Resistance TVOUTL/R 4.5 kΩ Load Capacitance TVOUTL/R pF Output Voltage ( Note 9) 1.8 2 2.2 Vrms Power Supply Rejection (PSR) (Note 15) - 50 dB Note 7. f = 1kHz, THD+N < -80dB, gain = 0dB(Volume=0dB) Note 8. Measured by Audio Precision System Two Cascade. Note 9. The output level of the internal AMP with volume should be less than 2Vrms. Note 10. Analog In to TVOUT. Path : AINL+/− → TVOUTL, AINR+/− → TVOUTR,Volume0dB. At 2Vrms single input, TDH+N is -91dB (typ), on path AINL+ → TVOUTL, AINR+ → TVOUTR, Volume=0dB Note 11. Between TVOUTL and TVOUTR with analog inputs AINL+/−, AINL/R+/−, 1kHz/0dB. Inter-channel crosstalk is -80dB (typ), at 20Hz~20kHz other than 1kHz. Note 12. -79dB (typ) referred to 0.5Vrms output level at Volume=+24dB : path = AIN+/- → TVOUT. Note 13. Analog In to TVOUT. Volume=0dB Path : AINL+/− → TVOUTL, AINR+/− → TVOUTR Note 14. 82dB (typ) referred to 0.5Vrms output level at Volume=+24dB : path = AIN+/- → TVOUT. 84dB (typ), referred to 0.5Vrm output level at Volume = +21dB. Note 15. The PSR is applied to VD1 and VD2 with 1kHz, 100mV.
Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz. S/N Reference Level = 0.7Vp-p, CCIR 567 weighting. Differential Gain 0.7Vpp 5steps modulated staircase. Differential Phase 0.7Vpp 5steps modulated staircase. Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
[AK4710] Rev. 0.3 2011/07 - 10 - SWITCHING CHARACTERISTICS Parameter Symbol min typ max Units Control Interface Timing (I2C Bus): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling ( Note 16) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 0.3 0.3 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF Reset Timing PDN Pulse Width (Note 17) tPD 150 ns Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 17. The AK4710 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied. Note 18. I 2C-bus is a trademark of NXP B.V.
[AK4710] Rev. 0.3 2011/07 - 11 - ■ Timing Diagram tHIGH SCL SDA VIH tLOWtBUF tHD:STA tR tF tHD:DAT tSU:DAT tSU:STA Stop Start Start Stop tSU:STO VIL VIH VIL tSP I2C Bus mode Timing tPD VIL PDN Power-down Timing
- System Reset and Power-down Options
The AK4710 should be reset once by bringing the PDN pin = “L” after all power supplies are supplied. L: Full Power-down Mode. Power-down, reset and initializes control registers. When the MUTE bit = “1”, the audio outputs settle to VSS (0V, typ) and the charge pump circuit is in power down mode.
0 L x Full Power-down
1 H 1 Mute (Note 19)
2 H 0 Normal operation
Note 19. TVOUTL/R are muted by Mute bit in the default state. Table 2. Operation Mode Settings (x: Don’t Care)
0 Full Power-down NOT
1 Mute
2 Normal operation
Note 20. 1kHz 2Vrms output with 4.5kΩ load at all audio output pins. 47.46 IRE at all video inputs corresponding to all video output pins with 150Ω load. Note 21. Internally pulled down by 120kΩ (typ) resistor. Table 3. Status of Each Operation Modes
Table 5. Volume, Single-ended Input
The AK4710 has switches for TV. Each switch can be controlled via the registers independently. Table 6. TV Video Output (Note 23) Table 7. RCA Video Output (Note 23) Note 23. When input the video signals via the ENCRC pin, set CLAMP1-0 bits respectively.
Each video output can be set to Hi-Z individually via the control registers. (Encoder Red/Chroma) and the ENCB pin (Encoder Blue), and CLAMP2 bit selects the input circuit for the ENCG pin. VCLP1-0 bits select the sync source of DC- restore circuit. Table 8. DC-restore Control for Encoder Input
0 DC restore clamp active
1 Sync tip clamp active
VCLP1-0 bits = “11” (DC restore source = ENCG), the sync tip is selected even if the CLAMP2 bit = “0”. Table 9. DC-restore Control for Encoder Green/Y Input Table 10. DC-restore Source Control
The AK4710 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV SCART. Table 11. TV Fast Blanking Output (Note: minimum load is 150Ω) Table 12. TV Slow Blanking Output (Note: minimum load is 10kΩ)
[AK4710] Rev. 0.3 2011/07 - 23 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 0 0 0 0 1 0 MUTE 1 01H Switch 1 0 0 1 MONO 1 0 1 02H Reserve 0 0 0 0 0 0 0 0 03H Zerocross 0 0 CAL 0 0 1 1 1 04H Video switch 0 0 0 RCA1 RCA0 1 VTV1 VTV0 05H Video output enable 0 TVFB 0 RCAV TVB TVG TVR TVV 06H Video volume/clamp CLAMPB VCLP1 VCLP0 CLAMP2 CLAMP1 1 0 0 07H S/F Blanking control 0 0 0 0 SBT1 SBT0 FB1 FB0 08H Reserve 0 0 0 0 0 0 0 0 09H Reserve 0 0 0 0 0 0 0 0 0AH Reserve 0 0 0 0 0 0 1 1 0BH Reserve 0 0 0 0 0 0 0 0 0CH Reserve 0 0 0 0 0 0 0 0 0DH Volume 0 VOL3 VOL2 VOL1 VOL0 1 1 1 When the PDN pin goes “L”, the registers are initialized to their default values. While the PDN pin = “H”, all registers can be accessed. Do not write any data to the register over 0DH. ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 0 0 0 0 1 0 MUTE 1 R/W R/W Default 0 0 0 0 1 0 1 1 MUTE: Audio output control 0: Normal operation 1: ALL Audio outputs to GND (default) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Switch 1 0 0 1 MONO 1 0 1 R/W R/W Default 1 0 0 1 0 1 0 1 MONO: Mono select for TVOUTL/R pins 0: Stereo. (default) 1: Mono. (L+R)/2 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Volume Control 0 0 CAL 0 0 1 1 1 R/W R/W Default 0 0 1 0 0 1 1 1 CAL: Offset calibration Enable 0: Offset calibration disable. 1: Offset calibration enable (default)
[AK4710] Rev. 0.3 2011/07 - 24 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Video switch 0 0 0 RCA1 RCA0 1 VTV1 VTV0 R/W R/W Default 0 0 0 1 1 1 0 0 VTV1-0: Selector for TV video output Refer to Table 6. RCA1-0: Selector for RCA video output Refer to Table 7. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Output Enable 0 TVFB 0 RCAV TVB TVG TVR TVV R/W R/W Default 0 0 0 0 0 0 0 0 TVV: TVVOUT output control TVR: TVRCOUT output control TVG: TVGOUT output control TVB: TVBOUT output control RCAV: RCAVOUT output control TVFB: TVFB output control 0: Hi-Z (default) 1: Active. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Video volume CLAMPB VCLP1 VCLP0 CLAMP2 CLAMP1 1 0 0 R/W R/W Default 0 0 0 0 0 1 0 0 CLAMPB, CLAMP2-1: Clamp control. Refer to Table 8 and Table 9. VCLP1-0: DC restore source control 00: ENCV pin (default) 01: ENCY pin 10: (Reserved) 11: ENCG pin
[AK4710] Rev. 0.3 2011/07 - 25 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H S/F Blanking 0 0 0 0 SBT1 SBT0 FB1 FB0 R/W R/W Default 0 0 0 0 0 0 0 0 FB1-0: TV Fast Blanking output control (for TVFB pin) 00: 0V (default) 01: 2V<, 2.5V(typ) at 150Ω load 10: (Reserved) 11: (Reserved) SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kΩ.) 00: < 2V (default) 01: 4.73V <, < 7V 10: (Reserved) 11: 10V < Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Main volume 0 VOL3 VOL2 VOL1 VOL0 1 1 1 R/W R/W Default 0 0 0 1 1 1 1 1 VOL3-0: Volume control Those registers control both Lch and Rch of Volume. 1011: Volume gain = +24dB 1010: Volume gain = +21dB 1001: Volume gain = +18dB 1000: Volume gain = +15dB 0111: Volume gain = +12dB 0110: Volume gain = +9dB 0101: Volume gain = +6dB 0100: Volume gain = +3dB 0011: Volume gain = +0dB (default) 0010: Volume gain = -3dB 0001: Volume gain = -6dB 0000: MUTE
circuits, the optimum layout, power supply arrangements and measurement results.
2 RACVOUT
3 VSS3
7 TVG
1 PDN
Figure 16. Typical Connection Diagram
[AK4710] Rev. 0.3 2011/07 - 27 - ■ Grounding and Power Supply Decoupling VD1, VD2, VP, VVD, VSS1, VSS2 and VSS3 should be supplied from analog supply unit with low impedance and be separated from system digital supply. An electrolytic capacitor 4.7μF parallel with a 0.1μF ceramic capacitor should be attached to VD1, VD2, VVD, VSS1, VSS2 and VSS3 pin to eliminate the effects of high frequency noise. The 0.1μF ceramic capacitor should be placed as near to VD1 (VD2, VVD) as possible. The VP pin must be connected to the Analogue 12V power supply via a 10ohm resistor and with a 0.1µF ceramic capacitor in parallel with a 1µF electrolytic capacitor to VSS1, as shown in Figure 16. ■ Analog Audio Outputs The analog outputs are also single-ended and centered on 0V(typ.). The output signal range is typically 2Vrms . ■ Slow Blanking pins The Slow Blanking Pin must have a 470ohm ±5% series resistor.
[AK4710] Rev. 0.3 2011/07 - 28 - ■ External Circuit Example The analog audio input pin must have 300ohm series resistor and 0.47uF capacitor. Analog Audio Input pin AINR+ AINR- AINL+ AINL- 0.47μF 300Ω Analog Audio Output pin TVOUTL/R 300Ω Total > 4.5kΩ (Cable) Analog Video Input pin ENCV, ENCY, ENCRC, ENCC, ENCG, ENCB, 0.1μF 75Ω (Cable) 75Ω Analog Video Output pin TVVOUT, TVRC TVG, TVB, RCAVOUT max 400pF 75Ω 75Ω max 15pF (Cable)
[AK4710] Rev. 0.3 2011/07 - 29 - Slow Blanking pin TVSB max 3nF (with 470Ω) 470Ω ±5% min: 10kΩ (Cable) Fast Blanking Output pin TVFB 75Ω 75Ω (Cable)
[AK4710] Rev. 0.3 2011/07 - 30 - PACKAGE 32pin QFN (Unit: mm) 2.8 ± 0.1 0.4 16 25 4.0 ± 0.1 4.0 ± 0.1 0.35 ± 0.10 A B 17 24 Exposed Pad 0.75 ± 0.05 C0.35 ■ Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
[AK4710] Rev. 0.3 2011/07 - 31 - MARKING 4710 XXXX XXXX : Date code (4 digit) Pin #1 indication IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, app lication circuits, software and other related informa tion contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circ uits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.