AK4691

AK4691 AKM | Alldatasheet

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Technical content

[AK4691] MS0672-E-00 2007/11 - 1 - GENERAL DESCRIPTION The AK4691 is a 16bit, 4ch ADC and 2ch DAC with Microphone-Amp lifier, Headphone-Amplifier, and Speaker-Amplifier. The recording block corresponds to supports 4-c hannel inputs, and also has 3-input selector for Internal/External MIC and LINE, output power for Microphone, Pre-Amp, and ALC (Automatic Level Control) circuit. The playback bock has Lineout-Amplifier, Headphone-Amplifier, and Speaker-Amplifier. The AK4691 is suitable for portable applications such as built-in LCD. The AK4691 is available in a 57pin BGA, utilizing less board space than competitive offerings.

FEATURES

1. Recording Function

• 4-channel Single-ended Pre-Amp (Pre-Amp Gain: 0dB, +18dB, +20dB, +24dB or +28dB)
• 2-channel Line Input
• 3-input Selector (Internal MIC, External MIC or LINE)
• 4-channel Digital ALC (Automatic Level Control)
• ADC Performance: S/(N+D): 82dB, DR, S/N: 90dB (Pre-Amp=+24dB) S/(N+D): 85dB, DR, S/N: 90dB (LINE)
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• Fade-in/out Function 2. Playback Function
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital Volume (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
• Stereo Separation Emphasis
• Stereo Line Output - Performance: S/(N+D): 85dB, S/N: 90dB - Output Level: -3.9dBV @ AVDD=LVDD=3.0V, LVOL=0dB +2dBV @ AVDD=3.0V, LVDD=4.5V, LVOL=+5.9dB
• Stereo Headphone-Amp - S/(N+D): 70dB, S/N: 90dB - Output Power: 58mW @ 16Ω (LVDD=3.3V) - Pop Noise Free at Power ON/OFF
• Mono Speaker-Amp - S/(N+D): 50dB@240mW, S/N: 90dB - BTL Output - Output Power: 400mW @ 8Ω (SVDD=3.3V)
• Analog Mixing 3. Power Management 4. Master Clock: (1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs 4ch ADC + 2ch DAC with MIC/HP/SPK-AMP AK4691

[AK4691] MS0672-E-00 2007/11 - 2 - 6. Sampling Rate:

• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 48kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. μP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode) 8. Master/Slave mode 9. Audio Interface Format: MSB First, 2’s complement
• ADC: 16bit MSB justified, I2S, TDM Mode
• DAC: 16bit MSB justified, 16bit LSB justified, 16-24bit I2S, TDM Mode 11. Power Supply Voltage:
• Analog (AVDD), Digital (DVDD): 2.6 ∼ 3.6V
• MIC (MVDD): 2.6 ∼ 5.5V
• Lineout & Headphone (LVDD): 2.6 ∼ 5.5V
• Speaker (SVDD): 2.6 ∼ 3.6V
• Digital I/F (TVDD1, TVDD2): 1.6 ∼ 3.6V 12. Package: 57pin BGA (5mm x 5mm, 0.5mm pitch, height: 1.0mm)

Figure 1. Block Diagram

[AK4691] MS0672-E-00 2007/11 - 4 - ■ Ordering Guide AK4691EG −30 ∼ +85°C 57pin BGA AKD4691 Evaluation board for AK4691 ■ Pin Layout A Top View BC E DF G H J AK4691

9 NC VCOC VCOM AVDD RIN LOUT LVCM MUTET NC

8 MRF PRELN1 VSS1 LIN BEEP ROUT LVDD HPL VSS4

7 PRERN2 PRELN2 VSS3 HPR

6 PRERN1 MVDD SVDD SPP

5 MPWR INTL1 Top View PDN SPN

4 INTL2 EXTL1 CDTI/SDA MUTE

3 INTR1 EXTL2 NC CSN/CAD0 CCLK/SCL

2 INTR2 EXTR1 TVDD1 MCKI SDTO2 LRCK MCKO TVDD2 NC

1 NC EXTR2 I2CN SDTI SDTO1 BICK DVDD VSS2 NC

[AK4691] MS0672-E-00 2007/11 - 5 - PIN/FUNCTION No. Pin Name I/O Function Power Supply D9 AVDD - Analog Power Supply Pin, 2.6 ∼ 3.6V C8 VSS1 - Ground 1 Pin C9 VCOM O Common Voltage Output Pin, 0.5 x AVDD Bias voltage of ADC inputs and DAC outputs. G1 DVDD - Digital Power Supply Pin, 2.6 ∼ 3.6V H1 VSS2 - Ground 2 Pin H6 SVDD - Speaker-Amp Power Supply Pin, 2.6 ∼ 3.6V H7 VSS3 - Ground 3 Pin B6 MVDD - MIC Block Power Supply Pin, 2.6 ∼ 5.5V A5 MPWR O MIC Power Output Pin A8 MRF O MIC Power Supply Ripple Filter Pin G8 LVDD - Headphone & LINEOUT-Amp Power Supply Pin, 2.6 ∼ 5.5V G9 LVCM O LINEOUT-Amp Common Vo ltage Output Pin, 0.5 x LVDD J8 VSS4 - Ground 4 Pin C2 TVDD1 - Digital I/F(Audio Interface) Power Supply 1 Pin, 1.6 ∼ 3.6V H2 TVDD2 - Digital I/F(Control Register Interface) Power Supply 2 Pin, 1.6 ∼ 3.6V Audio Interface D2 MCKI I External Master Clock Input Pin G2 MCKO O Master Clock Output Pin F2 LRCK I/O Input / Output Channel Clock Pin F1 BICK I/O Audio Serial Data Clock Pin D1 SDTI I Audio Serial Data Input Pin E1 SDTO1 O Audio Serial Data Output 1 Pin E2 SDTO2 O Audio Serial Data Output 2 Pin Control Register Interface C1 I2CN I Control Mode Select Pin “L”: I2C Bus, “H”: 3-wire Serial CSN I Chip Select Pin (I2CN pin = “H”) H3 CAD0 I Chip Address 0 Select Pin (I2CN pin = “L”) CCLK I Control Data Clock Pin (I2CN pin = “H”) J3 SCL I Control Data Clock Pin (I2CN pin = “L”) CDTI I Control Data Input Pin (I2CN pin = “H”) H4 SDA I/O Control Data Input/Output Pin (I2CN pin = “L”) MIC Block B5 INTL1 I Internal MIC Lch Input 1 Pin B4 EXTL1 I External MIC Lch Input 1 Pin B8 PRELN1 I Lch Pre-Amp Negative Input 1 Pin A3 INTR1 I Internal MIC Rch Input 1 Pin B2 EXTR1 I External MIC Rch Input 1 Pin A6 PRERN1 I Rch Pre-Amp Negative Input 1 Pin A4 INTL2 I Internal MIC Lch Input 2 Pin B3 EXTL2 I External MIC Lch Input 2 Pin B7 PRELN2 I Lch Pre-Amp Negative Input 2 Pin A2 INTR2 I Internal MIC Rch Input 2 Pin B1 EXTR2 I External MIC Rch Input 2 Pin A7 PRERN2 I Rch Pre-Amp Negative Input 2 Pin ADC Block D8 LIN I Lch Line Input Pin E9 RIN I Rch Line Input Pin

[AK4691] MS0672-E-00 2007/11 - 6 - No. Pin Name I/O Function DAC Block F9 LOUT O Lch Stereo Line Output Pin F8 ROUT O Rch Stereo Line Output Pin HP-Amp Block H8 HPL O Lch Headphone-Amp Output Pin J7 HPR O Rch Headphone-Amp Output Pin H9 MUTET O Mute Time Constant Control Pin Connected to VSS4 pin with a capacitor for mute time constant. SPK-Amp Block J5 SPN O Speaker Amp Negative Output Pin J6 SPP O Speaker Amp Positive Output Pin Other Functions J4 MUTE I Mute Pin “L”: Normal Operation, “H”: Mute B9 VCOC O Output Pin for Loop Filter of PLL Circuit This pin should be connected to VSS1 with one resistor and capacitor in series. H5 PDN I Power-Down Mode Pin “H”: Power-up, “L”: Power-down, reset and initialize the control register. E8 BEEP I BEEP Signal Input Pin NC - No Connection Pin No internal bonding. This pin should be connected to ground. Note 1. All input pins except analog input pins (BEEP, INTL1/2, EXTL1/2, INTR1/2, EXTR1/2, LIN, and RIN) should not be left floating. Note 2.All analog input pins (INTL1/2, EXTL1/2, INTR1/2, EXTR1/2, LIN, and RIN pins ) except the BEEP pin should be supplied signal via AC-coupling capacitor. Note 3. The BEEP pin should be supplied signal via AC-coupling capacitor and resistor. Note 4. Analog output pins (HPL, HPR, LOUT, and ROUT pins) except the SPP and SPN pins should deliver signal via AC-coupling capacitor. ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting MPWR, VCOC, SPN, SPP, HPR, HPL, MUTET, ROUT, LOUT, BEEP These pins should be open. Analog INTL1, INTL2, INTR1, INTR2, EXTL1, EXTL2, EXTR1, EXTR2, LIN, RIN These pins should be open and each path should be switched off. MCKO, SDTO1, SDTO2 These pins should be open. Digital MCKI, SDTI, MUTE These pins should be connected to VSS2. Other NC This pin should be connected to ground (VSS1, VSS2, VSS3 or VSS4).

[AK4691] MS0672-E-00 2007/11 - 7 - ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4 = 0V; Note 5, Note 6) Parameter Symbol min max Units Power Supplies: Analog AVDD −0.3 6.0 V Digital DVDD −0.3 6.0 V MIC-Amp MVDD −0.3 6.0 V Speaker-Amp SVDD −0.3 6.0 V Headphone-Amp/LINEOUT-Amp LVDD −0.3 6.0 V Digital I/F 1 TVDD1 −0.3 6.0 V Digital I/F 2 TVDD2 −0.3 6.0 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 7) VINA1 −0.3 AVDD+0.3 V (Note 8) VINA2 −0.3 MVDD+0.3 V Digital Input Voltage (Note 9) VIND1 −0.3 TVDD1+0.3 V (Note 10) VIND2 −0.3 TVDD2+0.3 V Ambient Temperature (powered applied) Ta −30 85 °C Storage Temperature Tstg −65 150 °C Maximum Power Dissipation (Note 11) Pd - 1.1 W Note 5. All voltages with respect to ground. Note 6. VSS1, VSS2, VSS3, and VSS4 must be connected to the same analog ground plane. Note 7. LIN, RIN, BEEP pins Note 8. INTL1/2, INTR1/2, EXTL1/2, EXTR1/2, PRELN1/2, PRERN1/2 pins Note 9. I2CN, MCKI, LRCK, BICK, SDTI pins Note 10. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, MUTE pins Pull-up resistors at the SDA and SCL pins should be connected to (TVDD2+0.3)V or less voltage. Note 11. In case of PCB wiring density is 200% or more. This power is the AK4691 internal dissipation that does not include power dissipation of externally connected speaker and headphone. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

[AK4691] MS0672-E-00 2007/11 - 8 - RECOMMEND OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4 = 0V; Note 5) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 2.6 3.0 3.6 V (Note 14) LINE/HP ( Note 12) LVDD 2.6 3.0 5.5 V MIC ( Note 13) MVDD 2.6 or “AVDD – 0.1” 3.0 5.5 V Digital DVDD 2.6 3.0 3.6 V Digital I/F 1 TVDD1 1.6 3.0 DVDD V Digital I/F 2 TVDD2 1.6 3.0 DVDD V SPK SVDD 2.6 3.0 3.6 V Difference AVDD – DVDD -0.3 0 0.3 V Note 5. All voltages with respect to ground. Note 12. When the voltage of LVDD pin is low and a high level signal is output from LINEOUT, the output signal is clipped and the distortion of LINEOUT degrades. LVDD should be more than (0.6 x AVDD + 0.8)[V] at LVOL2-0 bits = “000” and be more than (0.76 x AVDD + 0.8)[V] at LVOL2-0 bits = “001” and be more than (1.19 x AVDD + 0.8)[V] at LVOL2-0 bits = “010” and be more than (1.36 x AVDD + 0.8)[V] at LVOL2-0 bits = “100”in order to avoid clipping. Note 13. The Minimum value is higher value between 2.6V and “AVDD – 0.1”V. Note 14. The power up sequence among AVDD, LVDD, MVDD, DVDD, TVDD1, TVDD2, and SVDD is not critical. The AK4691 supports the following two cases of partial power ON/OFF. In these cases, the PDN pin must be “L”. 1. TVDD1=TVDD2=ON: AV DD=DVDD=LVDD=MVDD=SVDD can be power ON/OFF. 2. TVDD2=ON: TVDD1=AVDD=DVDD= LVDD=MVDD=SVDD can be power ON/OFF. When the power state is changed from OFF to ON in the above cases, the PDN pin should be changed from “L” to “H” after all power supply pins (TVDD1, TVDD2, AVDD, DVDD, MVDD, LVDD, and SVDD pins) are supplied. “L” time of 150ns or more is needed to reset the AK4691. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4691] MS0672-E-00 2007/11 - 9 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=MVDD=LVDD=SVDD=TVDD1=TVDD2=3.0V; VSS1=VSS2=VSS3=VSS4 = 0V; fs=48kHz; Input Frequency =1kHz; Measurement width=20Hz ∼ 20kHz, unless otherwise specified) Parameter min typ max Units Pre-Amp Characteristics: Input Resistance: Positive Input Pin (Note 15) 70 100 130 k Ω Negative Input Pin (Note 16) 1.54 2.2 2.86 k Ω Gain PRG12-10 bits = “000”, FB bit = “1” PRG22-20 bits = “000”, FB bit = “1” -0.8 0 +17.2 dB PRG12-10 bits = “001”, FB bit = “0” PRG22-20 bits = “001”, FB bit = “0” +17.2 +18 +18.8 dB PRG12-10 bits = “010”, FB bit = “0” PRG22-20 bits = “010”, FB bit = “0” +19.2 +20 +20.8 dB PRG12-10 bits = “011”, FB bit = “0” PRG22-20 bits = “011”, FB bit = “0” +23.2 +24 +24.8 dB PRG12-10 bits = “100”, FB bit = “0” PRG22-20 bits = “100”, FB bit = “0” +27.2 +28 +28.8 dB MIC Power Supply Voltage Characteristics: MPWR pin Output Voltage (Output current = 0mA) (Note 17) 1.7 1.9 2.1 V Maximum Output Current - - 4 mA ADC Analog Input Characteristics: ALC = OFF Resolution - - 16 bits Input Resistance (LIN, RIN pins) 70 100 130 k Ω Input Voltage (Note 18) (Note 19) (Note 18) (Note 20) -4.5 -57.9 -3.7 -57.1 -2.9 -56.3 dBV dBV S/(N+D) (-1dBFS) (Note 19) (Note 21) dB dB DR (-60dBFS, A-Weighted) (Note 19) (Note 20) dB dB S/N (A-Weighted) (Note 19) (Note 20) dB dB Interchannel Isolation (Note 19) (Note 20) 100 dB dB Interchannel Gain Mismatch (Note 19) (Note 20) 0.5 0.5 dB dB Note 15. INTL1/2, INTR1/2, EXTL1/2, EXTR1/2 pins Note 16. PRELN1/2, PRERN1/2 pins. Gain=0dB, +20dB: 3.5kΩ ± 30%; Gain=+18dB: 4.4kΩ ± 30%, Gain=+24dB: 2.2kΩ ± 30%, Gain=+28dB: 1.4kΩ ± 30% Note 17. When the output current is 0mA, the output voltage of MPWR pin is typically (MVDD – 1.1) V at MVDD=3.0V and typically (MVDD-1.4) V at MVDD=4.5V. When the output current is 4mA, the output voltage of MPWR pin is typically (MVDD – 1.3) V at MVDD=3.0V and typically (MVDD-1.5) V at MVDD=4.5V. Note 18. Input voltages are proportional to AVDD voltage. LIN, RIN = typ. (0.62 x AVDD) Vpp INTL1/2, INTR1/2, EXTL1/2, EXTR1/2 = typ. (0.0013 x AVDD) Vpp Note 19. Input from LIN, RIN pins. FB = “1”, IVOL=0dB. Note 20. Input from INTL1/2, INTR1/2, EXTL1/2 or EXTR1/2 pins. Pre-Amp Gain = + 24dB, PRE bit = “1”, FB bit = “0”, IVOL = +29.625dB, MGL12-10 = MGR12-10 = MGL22-20 = MGR22-20 bits = “010” (0dB) Note 21. Input from INTL1/2, INTR1/2, EXTL1/2 or EXTR1/2 pins. Pre-Amp Gain = + 24dB, PRE bit = “1”, FB bit = “0”, IVOL = +0dB, MGL12-10 = MGR12-10 = MGL22-20 = MGR22-20 bits = “010” (0dB) * 0dBV = 1Vrms = 2.83Vpp

Note 24. Output voltage is proportional to AVDD voltage. Figure 2. Headphone-Amp output circuit

[AK4691] MS0672-E-00 2007/11 - 11 - Parameter min typ max Units Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, IVOL=DVOL=0dB, RL=8Ω, BTL, SVDD=3.0V (Note 27) Output Voltage (Note 26) SPKG1-0 bits = “00”, 0dBFS (Po=140mW) - 0.5 - dBV SPKG1-0 bits = “10”, −3.75dBFS (Po=240mW) 1.4 3 4.6 dBV SPKG1-0 bits = “11”, −3.75dBFS, SVDD=3.3V, (Po=400mW) - 5 - dBV S/(N+D) SPKG1-0 bits = “00”, 0dBFS (Po=140mW) - 60 - dB SPKG1-0 bits = “10”, −3.75dBFS (Po=240mW) 20 50 - dB SPKG1-0 bits = “11”, −3.75dBFS, SVDD=3.3V (Po=400mW) - 20 - dB S/N (A-weighted) 80 90 - dB Load Resistance 8 - - Ω Load Capacitance - - 30 pF Mono Input: BEEP pin (External Input Resistance=20kΩ) Maximum Input Voltage (Note 28) - 1.8 - Vpp Gain (Note 29) BEEP Æ LOUT/ROUT LVOL2-0 bits = “000” −4.5 0 +4.5 dB BEEP Æ HPL/HPR HPG bit = “0” −24.5 −20 −15.5 dB BEEP Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” −0.57 +4.43 +8.93 dB ALC bit = “0”, SPKG1-0 bits = “01” - +6.43 - dB ALC bit = “0”, SPKG1-0 bits = “10” - +10.65 - dB ALC bit = “0”, SPKG1-0 bits = “11” - +12.65 - dB ALC bit = “1”, SPKG1-0 bits = “00” - +6.43 - dB ALC bit = “1”, SPKG1-0 bits = “01” - +8.43 - dB ALC bit = “1”, SPKG1-0 bits = “10” - +12.65 - dB ALC bit = “1”, SPKG1-0 bits = “11” - +14.65 - dB Note 26. Output voltage is proportional to AVDD voltage. But actual speaker output level is clipped according to the supplied SVDD voltage. Vout = typ. 1.0 x AVDD Vpp @ SPKG1-0 bits = “00” & 0dBFS, typ. 1.26 x AVDDVpp @ SPKG1-0 bits = “01” & 0dBFS, typ. 2.04 x AVDDVpp @ SPKG1-0 bits = “10” & 0dBFS, typ. 2.58 x AVDDVpp @ SPKG1-0 bits = “11” & 0dBFS at Full-differential. Note 27. In case of measuring at the SPP and SPN pins. Note 28. The Maximum voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 29. The gain is in inverse proportion to external input resistance. * 0dBV = 1Vrms = 2.83Vpp

[AK4691] MS0672-E-00 2007/11 - 12 - Parameter min typ max Units Power Supplies: Power-Up (PDN pin = “H”) All Circuit Power-up: ( Note 30) AVDD+DVDD+MVDD+TVDD1+TVDD2 - 28 42 mA LVDD: HP & LINEOUT-Amp Normal Op eration (No Output) - 6.4 9.6 mA SVDD: SPK-Amp Normal Oper ation (No Output) - 8 24 mA MIC + ADC (4ch Mode): AVDD+DVDD+TVDD1+TVDD2 ( Note 31) - 15.2 - mA MVDD - 7.5 - mA DAC+LINEOUT: AVDD+DVDD+MVDD+SVDD+TVDD1+TVDD2 ( Note 32) - 9.2 - mA LVDD: LINEOUT-Amp Normal Operation - 1.8 - mA Power-Down (PDN pin = “L”) (Note 33) AVDD+DVDD+MVDD+LVDD+SVDD+ TVDD1+TVDD2 - 10 100 μA Note 30. PLL Master Mode (MCKI=12.288MHz), PMMICL1=PMMICR1=PMMICL2=PMMICR2=PMADC1 = PMADC2 = PMDAC = PMLO = PMHPL = PMHPR = PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S = SPPSN =HPMNT bits = “1” and LOPS bit = “0”. The MPWR pin outputs 0mA. EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”): AVDD=13.5mA(typ), DVDD=4.1mA(typ), TVDD1=TVDD2=0mA(typ) Note 31. PLL Master Mode (MCKI=12.288MHz) and PMMICL1 = PMMICR1 = PMMICL2 = PMMICR2 = PMADC1 = PMADC2 = PMVCM=PMPLL=MCKO=PMMP = M/S bits = “1”. Note 32. PLL Master Mode (MCKI=12.288MHz), PMDAC = PMLO =PMVCM= PMPLL = MCKO = PMBP = M/S bits = “1”, and LOPS bit = “0”. Note 33. All digital input pins are fixed to TVDD1, TVDD2 or VSS2. The PDN pin is held at “VSS2”.

[AK4691] MS0672-E-00 2007/11 - 13 - FILTER CHARACTERISTICS DEM=OFF; FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 34) ±0.16dB PB 0 - 18.8 kHz −0.66dB - 21.1 - kHz −1.1dB - 21.6 - kHz −6.9dB - 24.0 - kHz Stopband SB 28.4 - - kHz Passband Ripple PR - - ±0.1 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 35) GD - 19 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): (Note 36) Frequency Response (Note 34) −3.0dB FR - 1.0 - Hz −0.5dB - 2.9 - Hz −0.1dB - 6.5 - Hz DAC Digital Filter (LPF): Passband (Note 34) ±0.1dB PB 0 - 21.3 kHz −0.7dB - 21.8 - kHz −6.0dB - 24.0 - kHz Stopband SB 25.2 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 59 - - dB Group Delay (Note 35) GD - 26 - 1/fs DAC Digital Filter (LPF) + SCF: Frequency Response: 0 ∼ 20.0kHz FR - ±1.0 - dB DAC Digital Filter (HPF): (Note 36) Frequency Response (Note 34) −3.0dB FR - 1.0 - Hz −0.5dB - 2.9 - Hz −0.1dB - 6.5 - Hz BOOST Filter: (Note 37) MIN 20Hz FR - 6.27 - dB 100Hz - 3.18 - dB 1kHz - 0.02 - dB MID 20Hz FR - 11.6 - dB 100Hz - 7.44 - dB 1kHz - 0.14 - dB MAX 20Hz FR - 17.48 - dB 100Hz - 11.47 - dB Frequency Response 1kHz - 0.40 - dB Note 34. The passband and stopband frequencies scale with fs (system sampling rate). For example, ADC is PB=0.45 x fs (@-1.1dB). Each response refers to that of 1kHz. Note 35. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16-bit data of both channels from the input register to the output of analog signal. DAC group delay is at PMADC1 = PMADC2 bits = “0”. When PMADC1 bit is “1” or PMADC2 bit is “1”, it is typ. 19/fs. Note 36. When PMADC1 bit = “1” or PMADC2 bit = “1”, the HPF of ADC is enabled but the HPF of DAC is disabled. When PMADC1 = PMADC2 bits = “0” and PMDAC bit = “1”, the HPF of DAC is enabled (@ HPFN bit = “0”) but the HPF of ADC is disabled. Note 37. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale.

[AK4691] MS0672-E-00 2007/11 - 14 - DC CHARACTERISTICS Parameter Symbol min typ max Units High-Level Input Voltage 2.2V ≤TVDD1≤3.6V VIH1 70 %TVDD1 - - V (Note 38)1 . 6 V ≤TVDD1<2.2V VIH1 80 %TVDD1 - - V Low-Level Input Voltage 2.2V ≤TVDD1≤3.6V VIL1 - - 30 %TVDD1 V (Note 38)1 . 6 V ≤TVDD1<2.2V VIL1 - - 20 %TVDD1 V High-Level Output Voltage (Note 39) (Iout=−200μA) VOH1 TVDD1−0.2 V Low-Level Output Voltage (Note 39) (Iout=200μA) VOL1 - - 0.2 V High-Level Input Voltage 2.2V ≤TVDD2≤3.6V VIH2 70 %TVDD2 - - V (Note 40)1 . 6 V ≤TVDD2<2.2V VIH2 80 %TVDD2 - - V Low-Level Input Voltage 2.2V ≤TVDD2≤3.6V VIL2 - - 30 %TVDD2 V (Note 40)1 . 6 V ≤TVDD2<2.2V VIL2 - - 20 %TVDD2 V Low-Level Output Voltage (SDA pin) (2.0V≤TVDD2≤3.6V: Iout=3mA) (1.6V≤TVDD2<2.0V: Iout=3mA) VOL2 VOL2 0.4 20%TVDD2 V V Input Leakage Current Iin - - ±10 μA Note 38. I2CN, MCKI, BICK, LRCK, SDTI pins Note 39. MCKO, SDTO1, SDTO2 pins Note 40. MUTE, PDN, CSN/CAD0, CCLK/SCK, CDTI pins SWITCHING CHARACTERISTICS Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Output Timing Frequency fs 7.35 - 48 kHz Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - %

[AK4691] MS0672-E-00 2007/11 - 15 - Parameter Symbol min typ max Units PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Cycle (Except TDM mode) Duty 45 - 55 % “H” time in TDM mode tLRCKH 1/(16fs) - 1/(32fs) ns BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Cycle (Except TDM mode) Duty 45 - 55 % “H” time in TDM mode tLRCKH 1/(16fs) - 1/(32fs) ns BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 240 - - ns Pulse Width High tBCKH 240 - - ns PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Cycle (Except TDM mode) Duty 45 - 55 % “H” time in TDM mode tLRCKH 1/(16fs) - 1/(32fs) ns BICK Input Timing Period PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns External Slave Mode MCKI Input Timing Frequency MCKI = 256fs fCLK 1.8816 - 12.288 MHz MCKI = 512fs fCLK 3.7632 - 24.576 MHz MCKI = 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Input Timing Frequency MCKI = 256fs fs 7.35 - 48 kHz MCKI = 512fs fs 7.35 - 48 kHz MCKI = 1024fs fs 7.35 - 13 kHz Duty Cycle (Except TDM mode) Duty 45 - 55 % “H” time in TDM mode tLRCKH 1/(16fs) - 1/(32fs) ns BICK Input Timing Period tBCK 312.5 - - ns Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns

[AK4691] MS0672-E-00 2007/11 - 16 - Parameter Symbol min typ max Units Audio Interface Timing Master Mode BICK “↓” to LRCK Edge (Note 42) tMBLR −40 - 40 ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD −70 ns BICK “↓” to SDTO tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK Edge to BICK “↑” (Note 42) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 42) tBLR 50 - - ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD ns BICK “↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTI Setup Time tCDS 40 - - ns CDTI Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN Edge to CCLK “↑” (Note 43) tCSS 50 - - ns CCLK “↑” to CSN Edge (Note 43) tCSH 50 - - ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μs Clock Low Time tLOW 1.3 - - μs Clock High Time tHIGH 0.6 - - μs Setup Time for Repeated Start Condition tSU:STA 0.6 - - μs SDA Hold Time from SCL Falling ( Note 44) tHD:DAT 0 - - μs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μs Rise Time of Both SDA and SCL Lines tR - - 0.3 μs Fall Time of Both SDA and SCL Lines tF - - 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 - - μs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppre ssed by Input Filter tSP 0 - 50 ns Power-down & Reset Timing PDN Pulse Width (Note 45) tPD 150 - - ns PMADC1 or PMADC2 “↑” to SDTO valid (Note 46) tPDV - 1059 - 1/fs Note 41. I2C is a registered trademark of Philips Semiconductors. Note 42. BICK rising edge must not occur at the same time as LRCK edge. Note 43. CCLK rising edge must not occur at the same time as CSN edge. Note 44. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 45. The AK4691 can be reset by the PDN pin = “L”. Note 46. This is the count of LRCK “↑” from the PMADC1 or PMADC2 bit = “1”.

There are the following four clock modes to interface with external devices (Table 1, Table 2). Note 47. If this mode is selected, the invalid clocks are output from the MCKO pin when MCKO bit is “1”. Table 1. Clock Mode Setting (x: Don’t care)

0 L PLL Slave Mode

Table 2. Clock pins state in Clock Mode the AK4691 is set to master mode by changing M/S bit = “1”.

0 Slave Mode (default)

1 Master Mode

Table 3. Select Master/Slave Mode

powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. **Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)** Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (N/A: Not available) Table 6). FS2 bit is “don’t care”. Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” (x: Don’t care)

“L” by setting PMPLL bit to “0”. Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

Figure 13. PLL Master Mode Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) Table 10. BICK Output Frequency at Master Mode

Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”), (N/A: Not available, x: Don’t care) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. the LOUT/ROUT pins at fs=8kHz is shown in Table 12. Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 16. EXT Slave Mode

initialization cycle is complete. be set to “0”. When PMDAC bit is “0”, INITDA bit should be changed. format is the same as SDTO2’s. Table 13. Audio Interface Format

16 BICK 16 BICK

“0”, SDTO2 is output to “0” data during the period of L2 and R2. Figure 17. Mode 0 Timing (TDM Mode) Figure 18. Mode 1 Timing

14 Don't Care

Figure 19. Mode 2 Timing

15 Don't Care

Figure 20. Mode 3 Timing

0 INTL1 pin 0 INTR1 pin

1 EXTL1 pin 1 EXTR1 pin

0 INTL2 pin 0 INTR2 pin

1 EXTL2 pin 1 EXTR2 pin

Table 14. Pre-Amp Input Signal Source Select impedance (typ. 100kΩ) and external capacitors (C2, C3). Table 15. Relationship between Pre-Amp Gain and Feedback resistor (N/A: Not available) Figure 21. Pre-Amp

1 Output

Table 16. MIC Power Figure 22. MIC Block Circuit example

+32.4dB. It is ignored when Pre-Amp gain is 0dB or -4.4dB. Table 17. Relationship between register and input pin Table 18. MIC Sensitivity Compensation function (N/A: Not available) Figure 23. Analog Mixing Circuit for Recording Block When AIN bit is “1”, LIN and RIN pins are selected. The MIX-Amp gain is changed by FB bit. Table 19. MIX-Amp gain at LINE Input

changing HPFN bit, DAC should be powered-down. When ADC side is powered-up, HPFN bit must be set to “0”.

0 DAC 00 1 1 OFF

Table 22. HPF ON/OFF (x: Don’t care) powered-up or both ADC and DAC are powered-up, digital EQ/HPF/LPF circuit in ADC1 operates at recording path. Even if the path is switched from recording to playback, the register setting of filter coefficient at recording remains. (PMADC1=PMADC2=PMDAC bits = “0”) should be powered-down.

10 Recording & Playback Recording path

01 Recording & Playback Recording path

Note 50. When LOOP1-0 bits = “10”, TDM mode (DIF1-0 bits = “00”) is not supported. Note 51. Stereo emphasis circuit in ADC1 and ADC2 is effective only at stereo operation. Table 23. Digital EQ/HPF/LPF Circuit Setting (x: Don’t care) PMADC2-1 bits = “01”) are changed at PMDAC bit = “1, PMADC1 = PMADC2 bits = “11” should be set more than 2/fs.

FIL3A, EQA, FIL1A, GN1A, and GN0A bits are for ADC1. FIL3B, EQB, FIL1B, GN1B, and GN0B bits are for ADC2. FIL3A(FIL3B) coefficient also sets the attenuation of the stereo separation emphasis. Table 24) and EQA(EQB) coefficient set the compensation gain. become LPF when F1ASA(F1ASB) and F3ASA(F3ASB) bits are “1”, respectively. When EQA(EQB) and FIL1A(FIL1B) bits are “0”, EQA(EQB) and FIL1A(FIL1B) blocks become “through” (0dB). filter should be set to “through” (“MUTE” in case of FIL3A (FIL3B)). Figure 25. Digital EQ/HPF/LPF Table 24. Gain select of gain block (x: Don’t care)

[AK4691] MS0672-E-00 2007/11 - 37 - [Filter Coefficient Setting] 1) When FIL1A(FIL1B) and FIL3A(FIL3B) are set to “HPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1A(FIL1B) should be set to 0dB.) Register setting for ADC1 FIL1A: F1ASA bit = “0”, F1A[13:0]A bits =A, F1B[13:0]A bits =B FIL3A: F3ASA bit = “0”, F3A[13:0]A bits =A, F3B[13:0]A bits =B (MSB=F1A13A, F1B13A, F3A13A, F3B13A; LSB=F1A0A, F1B0A, F3A0A, F3B0A) Register setting for ADC2 FIL1B: F1ASB bit = “0”, F1A[13:0]B bits =A, F1B[13:0]B bits =B FIL3B: F3ASB bit = “0”, F3A[13:0]B bits =A, F3B[13:0]B bits =B (MSB=F1A13B, F1B13B, F3A13B, F3B13B; LSB=F1A0B, F1B0B, F3A0B, F3B0B) A = 10K/20 x 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function Amplitude Phase H(z) = A 1 − z −1 1 + Bz −1 M(f) = A 2 − 2cos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) When FIL1A(FIL1B) and FIL3A(FIL3B) are set to “LPF” fs: Sampling frequency fc: Cut-off frequency f: Input signal frequency K: Filter gain [dB] (Filter gain of FIL1A (FIL1B) should be set to 0dB.) Register setting for ADC1 FIL1A: F1ASA bit = “0”, F1A[13:0]A bits =A, F1B[13:0]A bits =B FIL3A: F3ASA bit = “0”, F3A[13:0]A bits =A, F3B[13:0]A bits =B (MSB=F1A13A, F1B13A, F3A13A, F3B13A; LSB=F1A0A, F1B0A, F3A0A, F3B0A) Register setting for ADC2 FIL1B: F1ASB bit = “0”, F1A[13:0]B bits =A, F1B[13:0]B bits =B FIL3B: F3ASB bit = “0”, F3A[13:0]B bits =A, F3B[13:0]B bits =B (MSB=F1A13B, F1B13B, F3A13B, F3B13B; LSB=F1A0B, F1B0B, F3A0B, F3B0B) A = 10K/20 x 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function Amplitude Phase H(z) = A 1 + z −1 1 + Bz −1 M(f) = A 2 + 2cos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs)

[AK4691] MS0672-E-00 2007/11 - 38 - 3) EQ fs: Sampling frequency fc 1: Pole frequency fc2: Zero-point frequency f: Input signal frequency K: Filter gain [dB] (Maximum +12dB) Register setting for ADC1 EQA[15:0]A bits =A, EQB[13:0]A bits =B, EQC[15:0]A bits =C (MSB=EQA15A, EQB13A, EQC15A; LSB=EQA0A, EQB0A, EQC0A) Register setting for ADC2 EQA[15:0]B bits =A, EQB[13:0]A bits =B, EQC[15:0]B bits =C (MSB=EQA15B, EQB13B, EQC15B; LSB=EQA0B, EQB0B, EQC0B) A = 10K/20 x 1 + 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) B = 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc1/fs) , C =10 K/20 x 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) Transfer function Amplitude Phase H(z) = A + Cz −1 1 + Bz −1 M(f) = A2 + C2 + 2ACcos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) [Translation the filter coefficient calculated by the equations above from real number to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. [Filter Coefficient Setting Example] 1) FIL1Ablock Example: HPF, fs=44.1kHz, fc=100Hz F1ASAbit = “0” F1A[13:0]A bits = 01 1111 1100 0110 F1B[13:0]A bits = 10 0000 0111 0100 2) EQA block Example: fs=44.1kHz, fc 1=300Hz, fc2=3000Hz, Gain=+8dB Gain[dB] +8dB fc1 fc 2 Frequency EQA[15:0]A bits = 0000 1001 0110 1110 EQB[13:0]A bits = 10 0001 0101 1001 EQC[15:0]A bits = 1111 1001 1110 1111

powered-up or ADC1, ADC2, and DAC are powered-up, ALC circuit operates at recording path. Note 52. When LOOP1-0 bits = “10”, TDM mode (DIF1-0 bits = “00”) is not supported. Table 25. ALC Setting (x: Don’t care) ATT step (Table 27). The IVL and IVR are then set to the same value for both channels. timeout. When LFST bit = “1”, the attenuation level is fixed to 1 step regardless of the setting of LMAT1-0 bits. ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. input signal level exceeds LMTH1-0 bits.

Table 26. ALC Limiter Detection Level / Recovery Counter Reset Level Table 27. ALC Limiter ATT Step (x: Don’t care) Table 28. ALC Zero Crossing Timeout Period

Table 29) to be set after completing the ALC limiter operation. to the set reference level (Table 31) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 28). waits until WTM2-0 period and the next recovery operation is executed. the reference level (REF7-0 bits), the IVOL values are not increased. the waiting timer of ALC recovery operation starts. Table 29. ALC Recovery Operation Waiting Period Table 30. ALC Recovery GAIN Step

Table 31. Reference Level at ALC Recovery operation (0.375dB step) Table 32. Fast Limiter / Recovery Speed Setting (N/A: Not Available)

Table 33 shows the examples of the ALC setting for MIC recording. Table 33. Example of the ALC setting operation is finished by ALC bit = “0” or PMADC1=PMADC2 = PMDAC bits = “0”.

• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, GSEL, RFST1-0, LFST bits Manual Mode * The value of IVL/R should be the same or smaller than REF’s WR (ZTM1-0, WTM2-0) WR (ZELMN, RGAIN1-0, LMAT1-0) WR (LFST, RFST1-0, GSEL, LMTH1-0) WR (ALC= “1”) Example: MIC Input Recording Limiter = Zero crossing Enable Recovery Cycle = 21.3ms@48kHz Zero Crossing Timeout Period = 21.3ms@48kHz Limiter and Recovery Step = 1 Fast Limiter/Recovery Speed = 4 step Gain of IVOL = +30.0dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS LFST bit = “0” ALC bit = “1” (1) Addr=0AH, Data=1BH (2) Addr=0BH, Data=00H (5) Addr=0EH & 10H, Data=E1H (3) Addr=0CH, Data=01H ALC Operation WR (REF7-0) (4) Addr=0DH, Data=E1H WR (IVL/R7-0) (6) Addr=12H, Data=04H Note : WR : Write

Figure 26. Registers set-up sequence at ALC operation

operation stops and the ALC operation starts. NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation. Figure 27. Example for controlling sequence in FADEIN operation (1) WR(IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”. (3) WR (ALC bit = FDIN bit = “1”): The FADEIN operation starts. The IVL/R is fade-in from MUTE state. bits). After completing the FADEIN operation, the ALC operation starts. Table 34. FADEIN/OUT Period Table 35. FADEIN/OUT ATT Step Setting

the FADEOUT operation stops and the IVL/R keeps the value at that time. NOTE: When FDIN and FDOUT bits are set to “1” at the same time, FADEOUT operation is prior to FADEIN operation. Figure 28. Example for controlling sequence in FADEOUT operation (1) WR (FDOUT bit = “1”): The FADEOUT operation starts. Then ALC bit should be always “1”. (2) FADEOUT time is set by REF7-0, FDTM1-0 and FDATT bits. (4) Analog and digital outputs are muted externally. Then the IVL/R values are MUTE state. (5) WR (IVL/R7-0 bits = 00H) : IVL/R are changed to “MUTE”. (7) WR (IVL/R7-0 bits = XXH): The IVL/R value should be set to the same or smaller than REF’s. completing zero crossing detection operation of IVL/R. (9) Release an external mute function for analog and digital outputs.

volume setting is common to ADC1 and ADC2 and has two tables that are LINE and MIC.

1. After exiting reset state, when setting up the registers for the ALC operation (ZTM1-0, LMTH1-0 and etc)
2. When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.

For example; when the change of the sampling frequency.

1. When IVOL is used as a manual volume.

cycle after PMADC1, PMADC2, or PMDAC bit is changed to “1”. IVR7-0 bits should be set to “91H” (0dB) at GSEL bit = “0”. Table 36. Input Digital Volume Setting

zero-crossing counter is not reset. Therefore, IVL and IVR can be written in an interval less than zero crossing timeout. Figure 29. IVOL value during ALC operation (GSEL bit = “0”) (1) The IVL value becomes the start value if the IVL and IVR are different when the ALC starts. with an interval more than zero crossing timeout period after ALC bit = “0”. de-emphasis filter (Table 37). Table 37. De-emphasis Control

output clips to the full scale. Figure 30 shows the boost frequency response at –20dB signal input. Figure 30. Bass Boost Frequency Response (fs = 48kHz) Table 38. Bass Boost Control

from 00H (+12dB) to FFH (MUTE). Table 39. Digital Volume Code Table Table 40. Transition Time Setting of Digital Output Volume

output amplifier. The external resister Ri adjusts the signal level of BEEP input. typical gain example at Ri = 20kΩ. This gain is in inverse proportion to Ri . Figure 32. Block Diagram of BEEP pin Table 41. BEEP Input Æ LOUT/ROUT Output Gain (typ) at Ri = 20kΩ (N/A: Not available) Table 42. BEEP Input Æ Headphone-Amp Output Gain (typ) at Ri = 20kΩ Table 43. BEEP Input Æ Speaker-Amp Output Gain (typ) at Ri = 20kΩ

a common connector of LINEIN/OUT. Figure 33. Stereo Line Output Table 44. Stereo Line Output Volume Setting (x: Don’t care, N/A: Not Available)

1. LMODE bit = “1” (When Line input and Line output are not used as a common connector.)

Figure 34. Rise/Fall time is 300ms (max) at C=1μF. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation.

0 Power-down Pull-down to VSS4 (default) 0 1 Normal Operation Normal Operation

0 Power-save Fall down to VSS4 1 1 Power-save Rise up to LVCM

Table 45. Stereo Line Output Mode Select @ LMODE bit = “1” Figure 34. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)

1. LMODE bit = “0” (When Line input and Line output are used as a common connector.)

AK4691 should be in the power-save mode.

1 Power-save LVCM 1 0 Normal Operation Normal Operation

Table 47. External Circuit for Stereo Line Output @ LMODE bit = “0” (x: Don’t care) Figure 36. Connection Example (When Line input and Line output are used as a common connector.)

load resistance is 16Ω (min). HPG bit selects the output voltage (Table 48). Table 48. Headphone-Amp Output Voltage MUTET pin typ. max typ. max. Table 49. Relationship between capacitor value of MUTET pin and MUTE ON/OFF time (HPG bit = “0”)

0 Fall down to

1 Rise up to common

Table 50. Headphone-Amp Mode Setting (x: Don’t care)

and BTL output. The gain is set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits. Table 52. SPK-Amp Gain output signal is not clipped. Table 53. SPK-Amp Output Level

Table 54. ALC Operation Example of Speaker Playback Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pin are in Hi-Z state.

0 Power-save Hi-Z SVDD/2 1 1 Normal Operation Normal Operation Normal Operation

Table 55. Speaker-Amp Mode Setting (x: Don’t care) Figure 39. Power-up/Power-down Timing for Speaker-Amp become VCOM or LVCM voltage. LINEOUT and Speaker-Amp become Power-save mode, HP-Amp is in mute state.

one command. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”. Figure 40. Serial Control I/F Timing 1

In this mode, data can be written continuously and address counter is incremented automatically. rising edge (“↑”) and CSN rising edge (“↑”). Note 58. When CSN is set to “H” while data is written, the data is ignored. CCLK and CDTI in CSN = “L”, data is rewritten in address 33H. Figure 41. Control Data Timing 2

[AK4691] MS0672-E-00 2007/11 - 64 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 PMMP PMMICR2 PMMICL2 PMMICR1 PMMICL1 PMADC2 PMADC1 PMVCM 01H Power Management 2 0 HPMTN PMHPR PMHPL PMSPK PMLO PMDAC PMBP 02H Mode Control 1 0 0 BCKO M/S PS1 PS0 MCKO PMPLL 03H Mode Control 2 PLL3 PLL2 PLL1 PLL0 FS3 FS2 FS1 FS0 04H Mode Control 3 ADM1 ADM0 0 INITDA LMODE HPFN DIF1 DIF0 05H Pre-Amp Gain Select 0 0 PRG22 PRG21 PRG20 PRG12 PRG11 PRG10 06H Signal Select 1 0 FB AIN PRE PRSR2 PRSL2 PRSR1 PRSL1 07H Signal Select 2 SPPSN BEEPS DACS BEEPL DACL HPM BEEPH DACH 08H HP/SPK Gain Select 0 0 MICL2 MICR1 MICL1 HPG SPKG1 SPKG0 09H Mode Control 4 LVOL2 LVOL1 LVOL0 LOPS 0 0 DVOLC IVOLC 0AH Timer Select FDTM1 FDTM0 0 ZTM1 ZTM0 WTM2 WTM1 WTM0 0BH ALC Mode Control 1 0 ZELMN FDATT1 FDATT0 RGAIN1 RGAIN0 LMAT1 LMAT0 0CH ALC Mode Control 2 0 0 LFST RFST1 RFST0 GSEL LMTH1 LMTH0 0DH ALC Mode Control 3 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 0EH Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0FH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 10H Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 11H Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 12H ALC Mode Control 4 0 0 0 0 0 ALC FDOUT FDIN 13H Mode Control 5 LOOP1 LOOP0 S MUTE DVTM BST1 BST0 DEM1 DEM0 14H Mode Control 6 0 0 MGR12 MGR11 MGR10 MGL12 MGL11 MGL10 15H Mode Control 7 0 0 MGR22 MGR21 MGR20 MGL22 MGL21 MGL20 16H Digital Filter Select 1 GN1A GN0A 0 FIL1A EQA FIL3A 0 0 17H FIL3A Co-efficient 0 F3A7A F3A6A F3A5A F3A4A F3A3A F3A2A F3A1A F3A0A 18H FIL3A Co-efficient 1 F3ASA 0 F3A13A F3A12A F3A11A F3A10A F3A9A F3A8A 19H FIL3A Co-efficient 2 F3B7A F3B6A F3B5A F3B4A F3B3A F3B2A F3B1A F3B0A 1AH FIL3A Co-efficient 3 0 0 F3B13A F3B12A F3B11A F3B10A F3B9A F3B8A 1BH EQA Co-efficient 0 EQA7A E QA6A EQA5A EQA4A EQA3A EQA2A EQA1A EQA0A 1CH EQA Co-efficient 1 EQA15A EQA14A EQA13A EQA12A EQA11A EQA10A EQA9A EQA8A 1DH EQA Co-efficient 2 EQB7A EQB6A EQB5A EQB4A EQB3A EQB2A EQB1A EQB0A 1EH EQA Co-efficient 3 0 0 EQB13A EQB12A EQB11A EQB10A EQB9A EQB8A 1FH EQA Co-efficient 4 EQC7A EQC6A EQC5A EQC4A EQC3A EQC2A EQC1A EQC0A 20H EQA Co-efficient 5 EQC15A EQC14A EQC13A EQC12A EQC11A EQC10A EQC9A EQC8A 21H FIL1A Co-efficient 0 F1A7A F1A6A F1A5A F1A4A F1A3A F1A2A F1A1A F1A0A 22H FIL1A Co-efficient 1 F1ASA 0 F1A13A F1A12A F1A11A F1A10A F1A9A F1A8A 23H FIL1A Co-efficient 2 F1B7A F1B6A F1B5A F1B4A F1B3A F1B2A F1B1A F1B0A 24H FIL1A Co-efficient 3 0 0 F1B13A F1B12A F1B11A F1B10A F1B9A F1B8A 25H Digital Filter Select 2 GN1B GN0B 0 FIL1B EQB FIL3B 0 0 26H FIL3B Co-efficient 0 F3A7B F3A6B F3A5B F3A4B F3A3B F3A2B F3A1B F3A0B 27H FIL3B Co-efficient 1 F3ASB 0 F3A13B F3A12B F3A11B F3A10B F3A9B F3A8B 28H FIL3B Co-efficient 2 F3B7B F3B6B F3B5B F3B4B F3B3B F3B2B F3B1B F3B0B 29H FIL3B Co-efficient 3 0 0 F3B13B F3B12B F3B11B F3B10B F3B9B F3B8B 2AH EQB Co-efficient 0 EQA7B EQA6B EQA5B EQA4B EQA3B EQA2B EQA1B EQA0B 2BH EQB Co-efficient 1 EQA15B EQA14B EQA13B EQA12B EQA11B EQA10B EQA9B EQA8B 2CH EQB Co-efficient 2 EQB7B EQB6B EQB5B EQB4B EQB3B EQB2B EQB1B EQB0B 2DH EQB Co-efficient 3 0 0 EQB13B EQB12B EQB11B EQB10B EQB9B EQB8B 2EH EQB Co-efficient 4 EQC7B EQC6B EQC5B EQC4B EQC3B EQC2B EQC1B EQC0B 2FH EQB Co-efficient 5 EQC15B EQC14B EQC13B EQC12B EQC11B EQC10B EQC9B EQC8B 30H FIL1B Co-efficient 0 F1A7B F1A6B F1A5B F1A4B F1A3B F1A2B F1A1B F1A0B 31H FIL1B Co-efficient 1 F1ASB 0 F1A13B F1A12B F1A11B F1A10B F1A9B F1A8B 32H FIL1B Co-efficient 2 F1B7B F1B6B F1B5B F1B4B F1B3B F1B2B F1B1B F1B0B 33H FIL1B Co-efficient 3 0 0 F1B13B F1B12B F1B11B F1B10B F1B9B F1B8B Note 60. PDN pin = “L” resets the registers to their default values. Note 61. Write “0” data to the bits named “0”.

[AK4691] MS0672-E-00 2007/11 - 65 - ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 PMMP PMMICR2 PMMICL2 PMMICR1 PMMICL1 PMADC2 PMADC1 PMVCM R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMVCM: VCOM and LVCM Power Management 0: Power-down (default) 1: Power-up When any blocks are powered-up, th e PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits of 00H and 01H, PMPLL and MCKO bits are “0”. PMADC1: ADC1 Power Management 0: Power-down (default) 1: Power-up PMADC2: ADC2 Power Management 0: Power-down (default) 1: Power-up When the PMADC1 or PMADC2 bit is changed from “0 ” to “1”, the initialization cycle (1059/fs=22.1ms @48kHz) starts. After initializing, digital data of the ADC is output. PMMICL1: Lch Pre-Amp #1 Power Management 0: Power-down (default) 1: Power-up PMMICR1: Rch Pre-Amp #1 Power Management 0: Power-down (default) 1: Power-up PMMICL2: Lch Pre-Amp #2 Power Management 0: Power-down (default) 1: Power-up PMMICR2: Rch Pre-Amp #2 Power Management 0: Power-down (default) 1: Power-up PMMP: MPWR pin Power Management 0: Power-down. Pull-down to VSS1 with 5.3k Ω (typ.) (default) 1: Power-up

[AK4691] MS0672-E-00 2007/11 - 66 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 0 HPMTN PMHPR PMHPL PMSPK PMLO PMDAC PMBP R/W RD R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMBP: BEEP Input Power Management 0: Power-down (default) 1: Power-up Both PMDAC and PMBP bits should be set to “1” when DAC is powered-up for playback. After that, BEEPL, BEEPH, BEEPS, MICL1, MICR1, or MICL2 bit is used to control each path when BEEP input is used. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Lineout Power Management 0: Power-down (default) 1: Power-up PMSPK: Speaker-Amp Power Management 0: Power-down (default) 1: Power-up PMHPL: Headphone-Amp Lch Power Management 0: Power-down (default) 1: Power-up PMHPR: Headphone-Amp Rch Power Management 0: Power-down (default) 1: Power-up HPMTN: Headphone-Amp Mute Control 0: Mute (default) 1: Normal operation Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When all power management bits are “0” in the 00H and 01H addresses, PMPLL bit and MCKO bit is “0”, all blocks are powered-down. The register values remain unchanged. When neither ADC nor DAC are used, external clocks may not be present. When ADC or DAC is used, external clocks must always be present.

[AK4691] MS0672-E-00 2007/11 - 67 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Mode Control 1 0 0 BCKO M/S PS1 PS0 MCKO PMPLL R/W RD RD R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (default) 1: Enable: Output frequency is selected by PS1-0 bits. PS1-0: MCKO Output Frequency Select ( Table 9) Default: “00” (256fs) M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode BCKO: BICK Output Frequency Select at Master Mode ( Table 10) Default: “0” (32fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Mode Control 2 PLL3 PLL2 PLL1 PLL0 FS3 FS2 FS1 FS0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 FS3-0: Sampling Frequency Select ( Table 5, Table 6.) and MCKI Frequency Select (Table 11) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. PLL3-0: PLL Reference Clock Select ( Table 4) Default: “0000”(LRCK pin) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Mode Control 3 ADM1 ADM0 0 INITDA LMODE HPFN DIF1 DIF0 R/W R/W R/W RD R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 DIF1-0: Audio Interface Format ( Table 13) Default: “10” (Left justified) HPFN: HPF Control on DAC 0: Enable (default) 1: Disable LMODE: Select power-save m ode of stereo line output ( Table 45, Table 47) INITDA: DAC Initialization Cycle Enable 0: Enable (Initialization Cycle= 1059/fs) (default) 1: Disable ADM1-0: ADC Mono Mode ( Table 21) Default: “00” (Stereo Output)

[AK4691] MS0672-E-00 2007/11 - 68 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Pre-Amp Gain Select 0 0 PRG22 PRG21 PRG20 PRG12 PRG11 PRG10 R/W RD RD R/W R/ W R/W R/W R/W R/W Default 0 0 0 1 1 0 1 1 PRG12-10: Pre-Amp #1 Gain Setting ( Table 15) Default: “011” (+24dB) PRG22-20: Pre-Amp #2 Gain Setting ( Table 15) Default: “011” (+24dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Signal Select 1 0 FB AIN PRE PRSR2 PRSL2 PRSR1 PRSL1 R/W RD R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 1 0 0 0 0 PRSL1: Select input signal of Lch Pre-Amp #1 0: INTL1 pin (default) 1: EXTL1 pin PRSR1: Select input signal of Rch Pre-Amp #1 0: INTR1 pin (default) 1: EXTR1 pin PRSL2: Select input signal of Lch Pre-Amp #2 0: INTL2 pin (default) 1: EXTL2 pin PRSR2: Select input signal of Rch Pre-Amp #2 0: INTR2 pin (default) 1: EXTR2 pin PRE: Enable input signal from Pre-Amp 1 to ADC1 0: OFF 1: ON (default) AIN: Enable input signal from LIN/RIN pin to ADC1 0: OFF (default) 1: ON FB: Select MIX-Amp feedback resistor 0: 60k Ω (typ) (default) 1: 100kΩ (typ)

[AK4691] MS0672-E-00 2007/11 - 69 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Signal Select 2 SPPSN BEEPS DACS BEEPL DACL HPM BEEPH DACH R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DACH: Switch Control from DAC to Headphone-Amp 0: OFF (default) 1: ON BEEPH: Switch Control from the BEEP pin to Headphone-Amp 0: OFF (default) 1: ON HPM: Headphone-Amp Mono Output Select 0: Stereo (default) 1: Mono When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-Amp. Both PMHPL and PMHPR bits should be “1” when HPM bit is “1”. DACL: Switch Control from DAC to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, DACL bit is enabled. BEEPL: Switch Control from the BEEP pin to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, BEEPL bit is enabled. DACS: Switch Control from DAC to Speaker-Amp 0: OFF (default) 1: ON When DACS bit is “1”, DAC output signal is input to Speaker-Amp. BEEPS: Switch Control from BEEP pin to Speaker-Amp 0: OFF (default) 1: ON When BEEPS bit is “1”, mono signal is input to Speaker-Amp. SPPSN: Speaker-Amp Power-Save Mode 0: Power-Save Mode (default) 1: Normal Operation When SPPSN bit is “0”, Speaker-Amp is in power-save mode. In this mode, the SPP pin changes to Hi-Z and the SPN pin outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “H”, Speaker-Amp is in power-down mode since PMSPK bit is “0”.

[AK4691] MS0672-E-00 2007/11 - 70 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H HP/SPK Gain 0 0 MICL2 MICR1 MICL1 HPG SPKG1 SPKG0 R/W RD RD R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SPKG1-0: Speaker-Amp Output Gain Select ( Table 52) HPG: Headphone-Amp Gain Select ( Table 48) 0: 0dB (default) 1: +3.6dB MICL1: Select path from Lch Pre-Amp #1 to LOUT pin. 0: OFF (default) 1: ON When PMMICL1 = PMLO bits = “1”, MICL1 bit is enabled. MICR1: Select path from Rch Pre-Amp #1 to LOUT pin 0: OFF (default) 1: ON When PMMICR1 = PMLO bits = “1”, MICR1 bit is enabled. MICL2: Select path from Lch Pre-Amp #2 to LOUT pin 0: OFF (default) 1: ON When PMMICL2 = PMLO bits = “1”, MICL2 bit is enabled. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Mode Control 4 LVOL2 LVOL1 LVOL0 LOPS 0 0 DVOLC IVOLC R/W R/W R/W R/W R/ W RD RD R/W R/W Default 0 0 0 0 0 0 1 1 IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. DVOLC: Output Digital Volu me Control Mode Select 0: Independent 1: Dependent (default) When DVOLC bit = “1”, DVL7-0 bits control both Lch and Rch volume level, while register values of DVL7-0 bits are not written to DVR7-0 bits. When DVOL C bit = “0”, DVL7-0 bits control Lch level and DVR7-0 bits control Rch level, respectively. LOPS: Stereo Line Ou tput Power-Save Mode 0: Normal Operation (default) 1: Power-Save Mode LVOL2-0: Stereo Line Output Gain Select ( Table 44) Default: “000” (0dB)

[AK4691] MS0672-E-00 2007/11 - 71 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Timer Select FDTM1 FDTM0 0 ZTM1 ZTM0 WTM2 WTM1 WTM0 R/W R/W R/W RD R/ W R/W R/W R/W R/W Default 0 1 0 0 0 1 0 0 WTM2-0: ALC Recovery Waiting Period (Table 29) Default: “100” (2048/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 28.) Default: “00” (128/fs) FDTM1-0: FADEIN/OUT Cycle Setting (Table 34) Default: “01” (2048/fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH ALC Mode Control 1 0 ZELMN FDATT1 FDATT0 RGAIN1 RGAIN0 LMAT1 LMAT0 R/W RD R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LMAT1-0: ALC Limiter ATT Step (Table 27) Default: “00” RGAIN1-0: ALC Recovery GAIN Step (Table 30) Default: “00” FDATT1-0: FADEIN/OUT ATT Step Setting (Table 35) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH ALC Mode Control 2 0 0 LFST RFST1 RFST0 GSEL LMTH1 LMTH0 R/W RD RD R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 26) Default: “00” GSEL: Select IVOL Gain 0: MIC (default) 1: LINE RFST1-0: ALC First limiter/recovery Speed (Table 32) Default: “00” (4 times) LFST: Setting of Limiter operation when input signal exceeds full-scale level 0: IVL/R values are changed at zero-crossing detection or zero-crossing timeout. (default) 1: IVL/R values are immediately (period: 1/fs) attenuated by 1step when ALC output signal exceeds full-scale level.

[AK4691] MS0672-E-00 2007/11 - 72 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH ALC Mode Control 3 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 31) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Lch Input Volume Control IVL7 IV L6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 10H Rch Input Volume Control IVR7 IV R6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level ( Table 36) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 11H Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 1 1 0 0 0 DVL7-0, DVR7-0: Output Digital Volume ( Table 39) Default: “18H” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 12H ALC Mode Control 4 0 0 0 0 0 ALC FDOUT FDIN R/W RD RD RD RD RD R/W R/W R/W Default 0 0 0 0 0 0 0 0 ALC: ALC Enable 0: ALC Disable (default) 1 : A L C E n a b l e FDOUT: FADEOUT Enable 0: Disable (default) 1: Enable FDIN: FADEIN Enable 0: Disable (default) 1: Enable

[AK4691] MS0672-E-00 2007/11 - 73 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 13H Mode Control 5 LOOP1 LOOP 0 SMUTE DVTM BST1 BST0 DEM1 DEM0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 DEM1-0: De-emphasis Frequency Select ( Table 37) Default: “01” (OFF) BST1-0: Bass Boost Function Select ( Table 38) Default: “00” (OFF) DVTM: Digital Volume Transition Time Setting ( Table 40) 0: 1061/fs (default) 1: 256/fs This is the transition time between DVL/R7-0 bits = 00H and FFH. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted LOOP1-0: Digital Internal Loopback ( Table 23, Table 25) 00: SDTI → DAC (default) 01: SDTO1 → DAC 10: SDTO2 → DAC 11: SDTO1 → DAC When LOOP1-0 bits = “10” (SDTO2 Æ DAC), TDM mode (DIF1-0 bits = “00”) is not supported. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 14H Mode Control 6 0 0 MGR12 MGR11 MGR10 MGL12 MGL11 MGL10 15H Mode Control 6 0 0 MGR22 MGR21 MGR20 MGL22 MGL21 MGL20 R/W RD RD R/W R/ W R/W R/W R/W R/W Default 0 0 0 1 0 0 1 0 MGL12-10: MIC sensitivity compensation for INTL1/EXTL1 input MGR12-10: MIC sensitivity compensation for INTR1/EXTR1 input MGL22-20: MIC sensitivity compensation for INTL2/EXTL2 input MGR22-20: MIC sensitivity compensation for INTR2/EXTR2 input Default: “010” (0dB) ( Table 17, Table 18)

[AK4691] MS0672-E-00 2007/11 - 74 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 16H Digital Filter Select 1 GN1A GN0A 0 FIL1A EQA FIL3A 0 0 R/W R/W R/W RD R/ W R/W R/W RD RD Default 0 0 0 0 0 0 0 0 FIL3A: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3A bit is “1”, the settings of F3A13A-0A and F3B13A-0A bits are enabled. When FIL3A bit is “0”, FIL3A block is OFF (MUTE). EQA: EQA (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQA bit is “1”, the settings of EQA15A-0A, EQB13A-0A and EQC15A-0A bits are enabled. When EQA bit is “0”, EQA block is through (0dB). FIL1A: FIL1A (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1A bit is “1”, the settings of F1A13A-0A and F1B13A-0A bits are enabled. When FIL1A bit is “0”, FIL1A block is through (0dB). GN1A-0A: Gain Select at GAIN block in ADC1 ( Table 24) Default: “00” (0dB)

[AK4691] MS0672-E-00 2007/11 - 75 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 17H FIL3A Co-efficient 0 F3A7A F3A6A F3A5A F3A4A F3A3A F3A2A F3A1A F3A0A 18H FIL3A Co-efficient 1 F3ASA 0 F3A13A F3A12A F3A11A F3A10A F3A9A F3A8A 19H FIL3A Co-efficient 2 F3B7A F3B6A F3B5A F3B4A F3B3A F3B2A F3B1A F3B0A 1AH FIL3A Co-efficient 3 0 0 F3B13A F3B12A F3B11A F3B10A F3B9A F3B8A 1BH EQA Co-efficient 0 EQA7A EQA6 A EQA5A EQA4A EQA3A EQA2A EQA1A EQA0A 1CH EQA Co-efficient 1 EQA15A EQA14A E QA13A EQA12A EQA11A EQA10A EQA9A EQA8A 1DH EQA Co-efficient 2 EQB7A EQB6A EQB5A EQB4A EQB3A EQB2A EQB1A EQB0A 1EH EQA Co-efficient 3 0 0 EQB13A EQB12A EQB11A EQB10A EQB9A EQB8A 1FH EQA Co-efficient 4 EQC7A EQC6A EQC5A EQC4A EQC3A EQC2A EQC1A EQC0A 20H EQA Co-efficient 5 EQC15A EQC14A EQ C13A EQC12A EQC11A EQC10A EQC9A EQC8A 21H FIL1A Co-efficient 0 F1A7A F1A6A F1A5A F1A4A F1A3A F1A2A F1A1A F1A0A 22H FIL1A Co-efficient 1 F1ASA 0 F1A13A F1A12A F1A11A F1A10A F1A9A F1A8A 23H FIL1A Co-efficient 2 F1B7A F1B6A F1B5A F1B4A F1B3A F1B2A F1B1A F1B0A 24H FIL1A Co-efficient 3 0 0 F1B13A F1B12A F1B11A F1B10A F1B9A F1B8A R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 F3A13A-0A, F3B13A-0A: FIL3A (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3ASA: FIL3A (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15A-0A, EQB13A-0A, EQC15A-C0A: EQA (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13A-0A, F1B13A-B0A: FIL1A (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1ASA: FIL1A (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF

[AK4691] MS0672-E-00 2007/11 - 76 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 25H Digital Filter Select 2 GN1B GN0B 0 FIL1B EQB FIL3B 0 0 R/W R/W R/W RD R/ W R/W R/W RD RD Default 0 0 0 0 0 0 0 0 FIL3B: FIL3B (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3B bit is “1”, the settings of F3A13B-0B and F3B13B-0B bits are enabled. When FIL3B bit is “0”, FIL3B block is OFF (MUTE). EQB: EQB (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQB bit is “1”, the settings of EQA15B-0B, EQB13B-0B and EQC15B-0B bits are enabled. When EQB bit is “0”, EQB block is through (0dB). FIL1B: FIL1B (Wind-noise Reduction Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL1B bit is “1”, the settings of F1A13B-0B and F1B13B-0B bits are enabled. When FIL1B bit is “0”, FIL1B block is through (0dB). GN1B-0B: Gain Select at GAIN block in ADC2 ( Table 24) Default: “00” (0dB)

[AK4691] MS0672-E-00 2007/11 - 77 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 26H FIL3B Co-efficient 0 F3A7B F3A6B F3A5B F3A4B F3A3B F3A2B F3A1B F3A0B 27H FIL3B Co-efficient 1 F3ASB 0 F3A13B F3A12B F3A11B F3A10B F3A9B F3A8B 28H FIL3B Co-efficient 2 F3B7B F3B6B F3B5B F3B4B F3B3B F3B2B F3B1B F3B0B 29H FIL3B Co-efficient 3 0 0 F3B13B F3B12B F3B11B F3B10B F3B9B F3B8B 2AH EQB Co-efficient 0 EQA7B EQA6 B EQA5B EQA4B EQA3B EQA2B EQA1B EQA0B 2BH EQB Co-efficient 1 EQA15B EQA14B E QA13B EQA12B EQA11B EQA10B EQA9B EQA8B 2CH EQB Co-efficient 2 EQB7B EQB6B EQB5B EQB4B EQB3B EQB2B EQB1B EQB0B 2DH EQB Co-efficient 3 0 0 EQB13B EQB12B EQB11B EQB10B EQB9B EQB8B 2EH EQB Co-efficient 4 EQC7B EQC6B EQC5B EQC4B EQC3B EQC2B EQC1B EQC0B 2FH EQB Co-efficient 5 EQC15B EQC14B EQ C13B EQC12B EQC11B EQC10B EQC9B EQC8B 30H FIL1B Co-efficient 0 F1A7B F1A6B F1A5B F1A4B F1A3B F1A2B F1A1B F1A0B 31H FIL1B Co-efficient 1 F1ASB 0 F1A13B F1A12B F1A11B F1A10B F1A9B F1A8B 32H FIL1B Co-efficient 2 F1B7B F1B6B F1B5B F1B4B F1B3B F1B2B F1B1B F1B0B 33H FIL1B Co-efficient 3 0 0 F1B13B F1B12B F1B11B F1B10B F1B9B F1B8B R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 F3A13B-0B, F3B13B-0B: FIL3B (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3ASB: FIL3B (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF EQA15B-0B, EQB13B-0B, EQC15B-C0B: EQB (Gain Compensation Filter) Coefficient (14bit x 2 + 16bit x 1) Default: “0000H” F1A13B-0B, F1B13B-B0B: FIL1B (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: “0000H” F1ASB: FIL1B (Wind-noise Reduction Filter) Select 0: HPF (default) 1: LPF

[AK4691] MS0672-E-00 2007/11 - 79 - PACKAGE 57pin BGA (Unit: mm) 5.0 ± 0.1 5.0 ± 0.1 0.5 A B C D E F G 7 6 5 4 3 2 1 57 - φ 0.3 ± 0.05 H J 9 8 0.08 S S φ 0.05 ABS B 0.5 M A 4.0 1.0MAX 0.25 ± 0.05 ■ Material & Lead finish Package molding compound: Epoxy I n t e r p o s e r m a t e r i a l : B T r e s i n Solder ball material: SnAgCu

[AK4691] MS0672-E-00 2007/11 - 80 - MARKING 4691 XXXX XXXX: Date code (4 digits) Pin #1 indication

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents 07/11/02 00 First Edition IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these produc ts, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.