AK4679

AK4679EG AKM | Alldatasheet

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[AK4679] MS1402-E-06 2013/02 - 1 - GENERAL DESCRIPTION The AK4679 is a 24bit stereo CODEC and a built-in Microphone-Amplifier, Receiver-Amplifier, Mono Class-D Speaker-Amplifier, Cap-less Class-G Headphone-Amplifier and Line-Amplifier as well as HF/Audio DSP. The AK4679 features AKM DSP core to deal with hands free function for wide band and dual PCM I/F in addition to audio I/F that allows easy interfacing in mobile phone designs with Bluetooth I/F. The playback features also include 5-band Parametric EQ and Dynamic Range Control; therefore the AK4679 can automatically adjus t the volume to a comfortable leve l that has no dist ortion and provides great flexibility. The AK4679 is av ailable in a 78pin BGA, utilizing less board space than competitive offerings.

FEATURES

‹ CODEC&Amp block 1. Recording Function (Stereo CODEC)

• 4 Stereo Input Selectors
• 4 Stereo Inputs (Single-ended) or 3 Mono Input (Full-differential)
• MIC Amplifier: +24dB ~ −6dB, 3dB step
• 2 Output MIC Power Supplies
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• ADC CHARACTERISTICS: S/(N+D): 80dB, DR, S/N: 87dB (MIC-Amp=+18dB) S/(N+D): 80dB, DR, S/N: 92dB (MIC-Amp=0dB)
• Stereo Digital MIC Interface
• Wind-noise Reduction Filter
• Stereo Separation Emphasis
• 3-band Programmable Notch Filter
• Audio Interface Format: 24/16bit MSB justified, 24/16bit I2S, 16bit DSP Mode 2. Playback Function (Stereo CODEC)
• Digital Volume (+6dB ~ −57.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control): +36dB ~ −54dB, 0.375dB Step, Mute
• Stereo Separation Emphasis
• Dynamic Range Control
• 5-band Parametric Equalizer
• Stereo Line Output (Selectable Full-differential / Single-ended)
• Mono Receiver-Amp - BTL Output - Output Power: 60mW @ 32Ω - Analog Volume: +12 ~ −30dB & Mute, 3dB Step
• Cap-less Stereo Class-G Headphone-Amp - Output Power: 25mW @ 32Ω, 45mW @ 16Ω - Analog Volume: +6 ~ −62dB & Mute, 2dB Step - Zero crossing Detection - Pop Noise Free at Power-ON/OFF
• Mono Class-D Speaker-Amp - BTL Output - Short Protection Circuit - Output Power: 1.1W @ 8Ω, SVDD=4.2V, THD+N = 10% 0.89W @ 8Ω, SVDD=4.2V, THD+N = 1% - Analog Volume: +12 ~ −30dB & Mute, 3dB Step - Pop Noise Free at Power-ON/OFF
• Audio Interface Format: - 24/16bit MSB justified, 16bit LSB justified, 16/24bit I 2S, 16bit DSP Mode AK4679 24bit Stereo CODEC with DSP and MIC/RCV/HP/SPK/LINE-AMP

[AK4679] MS1402-E-06 2013/02 - 2 - 3. Dual PCM I/F for Baseband & Bluetooth Interface

• Four sample Rate Converters (Up sample: up to x6: Down sample: down to x1/6)
• Sample Rate: - PORTA (Mono): 8 ~ 16kHz - PORTB (Stereo): 8 ~ 48kHz
• Digital Volume
• Slave Mode
• Audio Interface Format: - 16bit Linear, 8bit A-law, 8bit μ-law - Short/Long Frame, I2S, MSB justified 4. Power Management 5. Master Clock(Audio I/F): (1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13. 5MHz, 19.2MHz, 24MHz, 25MHz, 26MHz, 27MHz (MCKI pin) 32fs or 64fs (BICK pin) (2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 6. Output Master Clock Frequencies(Audio I/F): 32fs/64fs/128fs/256fs 7. Sampling Frequency (Audio I/F)
• PLL Slave Mode (BICK pin): 8kHz ~ 48kHz
• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode: 8kHz ∼ 48kHz (256fs), 8kHz ~ 24kHz (512fs), 8kHz ~ 12kHz (1024fs) 8. Audio I/F: Master/Slave mode ‹ DSP block 9. Embedded DSP - Flexible programming with built-in program and data memories - Hardware accelerator - Word length: 24bit (Data RAM 24bit floating point) - Multiplier 20 x 20 Æ 40bit (double precision available) - Divider 20 / 20 Æ 20bit - ALU: 44bit arithmetic operation (with overflow margin 4bit) 24bit floating point arithmetic and logic operation - Program RAM: 4096w x 36bit - Coefficient RAM: 2048w x 20bit - Data RAM: 2048w x 24bit (24bit floating point) - Offset Register: 32w x 15bit - Delay RAM: 16384w x 24bit (24bit floating point) - 5625 steps at fs16KHz, 1875 steps at fs48KHz - Internal clock generator 10. DSP Serial Audio Interface Format - 24bit Left justified, I 2S, - 16/24 bit linear, 8bit A-law, 8bit µ-law PCM - Sampling rate 8 KHz ~ 48 KHz - Up/Down sampling rate converter for Port#2 (8KHz → 16KHz) 11. Operational, sleep, suspend mode

[AK4679] MS1402-E-06 2013/02 - 3 - ‹ General 12. μP I/F: I2C Bus (Ver 1.0, 400kHz Fast Mode), SPI (DSP block only) 14. Power Supply:

• SVDD (SPK/RCV/LINE-Amp): 3.0 ~ 5.5V
• A V D D ( A n a l o g ) : 1 . 7 ~ 2 . 0 V
• DVDD (Digital Core): 1.7 ~ 2.0V
• PVDD (HP-Amp & Charge Pump): 1.7 ~ 2.0V
• TVDDA, TVDDE (Digital I/F): 1.6 ~ 3.6V
• VDDE (DSP Core) 1.1 ~ 1.3V 15. Package : 78pin FBGA(4.5 x 4.5 mm, 0.4mm pitch)

Figure 1. Analog Block Diagram

Figure 2. Digital Block Diagram

Figure 3. DSP Block Diagram

Figure 4. DSP Core

[AK4679] MS1402-E-06 2013/02 - 8 - ■ Ordering Guide AK4679EG −30 ∼ +85°C 78pin BGA (0.4mm pitch) Black type AKD4679 Evaluation board for AK4679 ■ Pin Layout Top View A Top View BC E DF G H J

9 LIN2/

IN3+ HPR PVDD CNA VSS5 CNB

8 VSS1 CSN/

7 VCOM LOUT/

SCLK_ CAD0 PDNE RIN4 LIN4 PDNA SDAA VSS2

6 AVDD ROUT/

CAD1 SYNC2 BCLK1 SCLA SDTO TVDDA

5 MPWR1 MPWR2 SO/

SYNC3 SDIN1 SYNC1 LRCK BICK

4 RCP RCN SDOUT2 TEST SDOUT3

/GP0 SYNCA SDTOB SDTI

3 SVDD VSS3 SDIN4 SDIN2 SDIN3 JX0/

2 SPN VSS3 I2CE SDOUT4

/GP1 SDTIA BCLK2 BICKA BICKB SDTOA

1 SVDD SPP SPFIL TVDDE DVDD VSS4 VDDE SDOUT1 SDTIB

[AK4679] MS1402-E-06 2013/02 - 9 - PIN/FUNCTION No. Pin Name I/O Function Power Supply A6 AVDD - Analog Power Supply Pin, 1.7 ∼ 2.0V A7 VCOM O Common Voltage Output Pin A8 VSS1 - Ground 1 Pin E1 DVDD - Digital Core Power Supply Pin, 1.7 ~ 2.0V J6 TVDDA - Digital I/O Power Supply Pin, 1.6 ∼ 3.6V J7 VSS2 - Ground 2 Pin A1,A3 SVDD - Analog Amp Power Supply Pin, 3.0 ~ 5.5V B2,B3 VSS3 - Ground 3 Pin F9 PVDD - HP-Amp & Charge Pump Power Supply Pin H9 VSS5 - Ground 5 Pin F8,G8 VEE - Charge Pump Circuit Negative Voltage Output Pin H8 CPA O Positive Charge Pump Capacitor Terminal A Pin G9 CNA I Negative Charge Pump Capacitor Terminal A Pin J8 CPB O Positive Charge Pump Capacitor Terminal B Pin J9 CNB I Negative Charge Pump Capacitor Terminal B Pin A5 MPWR1 O MIC Power Supply 1 Pin B5 MPWR2 O MIC Power Supply 2 Pin Audio Interface J3 MCKI I External Master Clock Input Pin J5 BICK I/O Audio Serial Data Clock Pin H5 LRCK I/O Input / Output Channel Clock Pin J4 SDTI I Audio Serial Data Input Pin H6 SDTO O Audio Serial Data Output Pin PCM Interface G2 BICKA I Serial Data Clock A Pin G4 SYNCA I Sync Signal A Pin E2 SDTIA I Serial Data Input A Pin J2 SDTOA O Serial Data Output A Pin H2 BICKB I Serial Data Clock B Pin H3 SYNCB I Sync Signal B Pin J1 SDTIB I Serial Data Input B Pin H4 SDTOB O Serial Data Output B Pin Analog Input LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input, DMIC bit = “0”) IN1+ I Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input, DMIC bit = “0”) DMDAT I Digital Microphone Data Input Pin (DMIC bit = “1”) RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input, DMIC bit = “0”) IN1− I Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input, DMIC bit = “0”) DMCLK O Digital Microphone Clock Pin (DMIC bit = “1”) LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) A9 IN2- I Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input) RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input) B9 IN2+ I Positive Line Input 2 Pin (MDI F2 bit = “1”: Full-differential Input) LIN3 I Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input) D9 IN3+ I Positive Line Input 3 Pin (MDI F3 bit = “1”: Full-differential Input) RIN3 I Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input) D8 IN3− I Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input) F7 LIN4 I Lch Analog Input 4 Pin E7 RIN4 I Rch Analog Input 4 Pin

[AK4679] MS1402-E-06 2013/02 - 10 - PIN/FUNCTION (Cont.) No. Pin Name I/O Function Analog Output ROUT O Rch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output) B6 LON O Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) LOUT O Lch Stereo Line Output Pin (LODIF bit = “0”: Stereo Line Output) B7 LOP O Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output) A4 RCP O Receiver-Amp Positive Output Pin B4 RCN O Receiver-Amp Negative Output Pin E8 HPL O Lch Headphone-Amp Output Pin E9 HPR O Rch Headphone-Amp Output Pin B1 SPP O Speaker-Amp Positive Output Pin A2 SPN O Speaker-Amp Negative Output Pin C1 SPFIL O Speaker-Amp Filter Pin Connect 2.2nF between SPFIL pin and VSS1. Control Interface for Audio Block G6 SCLA I Control Data Clock Pin H7 SDAA I/O Control Data Input Pin G7 PDNA I Power-Down Mode Pin “H”: Power-up, “L”: Power-down, reset and initializes the control register. Note 1. All input pins except analog input pins (LIN1/IN1+, RIN1/IN1−, LIN2/IN2-, RIN2/IN2+, LIN3/IN3+, RIN3/IN3−, LIN4, RIN4) must not be allowed to float. I/O pins (LRCK, BICK and SDAA pins) should be processed appropriately. NO Pin Name I/O Function DSP I/O G1 VDDE - Core Power Supply Pin 1.2V D1 TVDDE - I/O power Supply Pin 1.6∼3.6V F1 VSS4 - Ground pin 0V D7 PDNE I Power-Down Mode Pin “H”: Power-up, “L”: Power-down, reset the control register. The AK4679 DSP must be reset once upon power-up. STO Status Output Pin (STRDY bit = “0”) G3 RDY O Data Write Ready output pin for control I/F (STRDY bit = “1”) G5 SYNC1 I Frame Sync 1 pin F6 BCLK1 I Serial Data Clock 1 Pin AK4679 DSP goes into stanby state when BCLK1 is not present. F5 SDIN1 I Serial Data Input 1 Pin H1 SDOUT1 O Serial Data Output 1 Pin D6 SYNC2 O Frame Sync 1 pin F2 BCLK2 O Serial Data Clock 2 Pin D3 SDIN2 I Serial Data Input 2 Pin C4 SDOUT2 O Serial Data Output 2 Pin SYNC3 Frame Sync 3 pin (SELPT bit = “1”) D5 JX1 I Conditional Jump 1 Pin (SELPT bit = “0”) BCLK3 Serial Data Clock 3 Pin (SELPT bit = “1”) F3 JX0 I Conditional Jump 0 Pin (SELPT bit = “0”) E3 SDIN3 I Serial Data Input 3 Pin SDOUT3 Serial Data Output 3 Pi n (SELDO3 bit = “0”) F4 GP0 O DSP Programmable output 0 Pin (SELDO3 bit = “1”) C3 SDIN4 I Serial Data Input 4 Pin

[AK4679] MS1402-E-06 2013/02 - 11 - SDOUT4 Serial Data Output 4 Pin (SELDO4 bit = “0”) D2 GP1 O DSP Programmable output 1 Pin (SELDO4 bit = “1”) C2 I2CE I Control Interface Mode Select Pin for DSP Block “H”: I2CE, “L”: SPI SCLK Serial Clock Input pin SPI (I2CE pin = “L”) C7 CAD0 I Slave Address 0 Input pin I2C (I2CE pin = “H”) CSN Chip select pin SPI (I2CE pin = “L”) B8 SCLE I Control Interface clock input pin I2C (I2CE pin = “H”) SO O Serial data output pin SPI (I2CE pin = “L”) C5 SDAE I/O Control Interface input/output acknowledge pin I2C (I2CE pin = “H”) SI Serial data input pin SPI (I2CE pin = “L”) C6 CAD1 I Slave Address 1 Input pin I2C(I2CE pin = “H”) E4 TEST I Test pin (pull-down resistor) must be connected to VSS4. Note 2. All input pins must not be allowed to float. Note 3. I2CE and CAD0/1 pins must be fixed to “L” (VSS4) or “H” (TVDDE). ■ Handling of Unused Pin on the System The unused input and output pins on the system should be processed appropriately as below. Classification Pin Name Setting Analog MPWR1, MPWR2, SPP, SPN, RCP, RCN, HPL, HPR, ROUT/LON, LOUT/LOP, RIN4, LIN4, RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-, RIN1/IN1−, LIN1/IN1+, CPA, CNA, CPB, CNB, VEE, SPFIL These pins should be open. SDTO, SDTOA, SDTOB STO/RDY, SDOUT3/GPO, SDOUT4/GP1 These pins should be open. MCKI, SDTI, SDTIA, SDTIB, BICKA, SYNCA, BICKB, SYNCB These pins should be connected to VSS2. LRCK, BICK These pins should be connected to VSS2 and M/S bit should be set to “0”. Digital SYNC1, BCLK1, SDIN3, SDIN4, SYNC3/JX1, BCLK3/JX0, TEST These pins should be connected to VSS4 ■ Pin States in DSP Power-down Mode The table below shows pin states when the PDNE pin= “L”. NO Pin Name I/O Pin state STO G3 RDY O Low H1 SDOUT1 O SDIN2 data output D6 SYNC2 O SYNC1 data output F2 BCLK2 O BCLK1 data output C4 SDOUT2 O SDIN1 data output SDOUT3 F4 GP0 O SDIN4 data output SDOUT4 D2 GP1 O SDIN3 data output SO O Low level (I2CE pin = “L”: SPI) C5 SDAE I/O Hi-z (I2CE pin = “H” :I 2C)

[AK4679] MS1402-E-06 2013/02 - 12 - ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=VSS4=VSS5=0V; Note 4, Note 5) Parameter Symbol min max Unit Power Supplies: Analog AVDD −0.3 2.5 V SPK/RCV/LINE-Amp SVDD −0.3 6.0 V HP-Amp & Charge Pump PVDD −0.3 2.5 V Digital Core DVDD −0.3 2.5 V Digital I/O (Codec) TVDDA −0.3 6.0 V DSP Core VDDE -0.3 1.6 V Digital I/O (DSP) TVDDE -0.3 4.1 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 6) VINA −0.3 AVDD + 0.3 V Digital Input Voltage (Note 8) VIND1 −0.3 TVDD + 0.3 V Digital Input Voltage (Note 7) VINDE −0.3 TVDDE + 0.3 V Ambient Temperature (powered applied) Ta −30 85 °C Storage Temperature Tstg −65 150 °C Maximum Power Dissipation Pd − 1 W Note 4. All voltages with respect to ground. Note 5. VSS1 to VSS5 must be connected to the same analog ground plane. Note 6. RIN4, LIN4, RIN3/IN3−, LIN3/IN3+, RIN2/IN2+, LIN2/IN2-, RIN1/IN1−, LIN1/IN1+ pins Note 7. SDTI, LRCK, BICK, MCKI, PDNA, BICKA, SYNC A, SDITA, BICKB, SYNCB, SDTIB, SCLA and SDAA pins. Pull-up resistors at SDAA and SCLA pins should be connected to (TVDDA+0.3)V or less voltage. Note 8. SYNC1/2/3, BCLK1/2/3, SDIN1-4, SDOUT1-4, I2CE, STO/RDY, SCLK/C AD, SI/CAD0, CSN/SCLE and SO/SDAE. Pull-up resistors at SDAE and SCLE pins should be connected to (TVDDE+0.3)V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

[AK4679] MS1402-E-06 2013/02 - 13 - RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=VSS4=VSS5=0V; Note 4) Parameter Symbol min typ max Unit Power Analog AVDD 1.7 1.8 2.0 V Supplies SPK/RCV/LINE-Amp SVDD 3.0 4.2 5.5 V (Note 9) HP-Amp & Charge Pump PVDD 1.7 1.8 2.0 V Digital Core DVDD 1.7 1.8 2.0 V Digital I/O (Codec) TVDDA 1.6 1.8 3.6 V DSP Core VDDE 1.1 1.2 1.3 V Digital I/O (DSP) TVDDE 1.6 1.8 3.6 V Difference AVDD – PVDD −0.2 − 0.2 V AVDD – DVDD −0.2 − 0.2 V PVDD – DVDD −0.2 − 0.2 V Note 4. All voltages with respect to ground. Note 9. The power-up sequence between supplies (AVDD, SVDD, PVDD, DVDD or TVDD) is not critical. The PDNA pin should be held “L” when power supplies are tuning on. The PDNA pin is allowed to be “H” after all power supplies are applied and settled. The AK4679 should be operated along the recommended power-up/down sequence shown in “ System Design (Grounding and Power Supply Decoupling)” to avoid pop noise at speaker output, receiver output, headphone outputs and line outputs. * AVDD, PVDD, DVDD, VDDE, TVDDE and TVDDA can be powered OFF (Power is not applied) when SVDD is powered ON (Power is applied) with both PDNA and PDNE pin “L”. When turning on AVDD, PVDD, DVDD, VDDE, TVDDE and TVDDA again in this case, the PDNA pin must be “L” until all other power supplies are powered ON. Also, when turning off AVDD, PVDD, DVDD, VDDE, TVDDE and TVDDA both the PDNA and PDNE pin must be “L” before other power supplies start to turn off. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4679] MS1402-E-06 2013/02 - 14 - ANALOG CHARACTERISTICS (CODEC) (Ta=25°C; AVDD=PVDD= DVDD=TVDDA= TVDDE=1.8V, SVDD=4.2V, VDDE=1.2V; VSS1=VSS2=VSS3=VSS4 =VSS5 =0V; Signal Frequency=1kHz; 24bit Data; fs=44.1kHz, BICK=64fs; Measurement Bandwidth=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Unit MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins Input Resistance 17 25 38 kΩ Gain (Note 10) Gain Setting −6 - +24 dB Step Width - 3 - dB MIC Power Supply: MPWR1, MPWR2 pin Output Voltage (Note 11) 2.3 2.5 2.7 V Load Resistance 1.0 - - kΩ Load Capacitance - - 30 pF Output Noise Level (A-weighted) - −107 - dBV PSRR (Note 12) 217Hz - 100 - dB 1kHz - 100 - dB Stereo ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 pins(Single-ended Input) → Stereo ADC → Programmable Filter (IVOL=0dB, EQ=ALC=OFF) → SDTO Resolution - - 24 Bits (Note 14) 69 80 - dB S/(N+D) (−1dBFS) (Note 15) - 80 - dB (Note 14) 76 87 - dB D-Range (−60dBFS, A-weighted) (Note 15) - 92 - dB (Note 14) 76 87 - dB S/N (A-weighted) (Note 15) - 92 - dB (Note 14) 75 90 - dB Interchannel Isolation (Note 16) (Note 15) - 100 - dB (Note 14) - 0 0.8 dB Interchannel Gain Mismatch (Note 16) (Note 15) - 0 0.8 dB Note 10. In case of full-differential input, MGAIN (min)=-3dB MICL1 bit or MICL2 bit = “1”: typ. 1.56 x AVDD V Note 12. PSRR is referred to SVDD with 500mVpp sine wave. Note 13. Input voltage which means ADC full-scale voltage is proportional to AVDD voltage. Single-ended Input: Vin = 1.0 x AVDD Vpp(typ). Full-Differential Input: Vin = (IN+) – (IN–) = 1.0 x AVDD Vpp(typ). IN+ = 0.5 x AVDD(typ), IN– = 0.5 x AVDD(typ) Pseudo-Differential Input: Vin = (IN+) – (IN–) = 1.0 x AVDD Vpp (typ). IN+ = 1.0 x AVDD(typ), IN– = 0V (IN– pin should be connected to VSS1.) Note 14. MGNL3-0=MGNR3-0 bits = “BH” (+18dB). In case of Full-differential, S/(N+D) =75dB, DR=S/N=81dB Note 15. MGNL3-0=MGNR3-0 bits = “5H” (0dB). In case of Full-differential, S/(N+D) =79dB, DR=S/N=91dB Note 16. This is a value between Lch and Rch of each input.

[AK4679] MS1402-E-06 2013/02 - 15 - Parameter min typ max Unit Stereo DAC Characteristics: Resolution - - 24 Bits Stereo Line Output Characteristics: Stereo DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, OVOL=0dB, LVL=0dB, RL=10kΩ; unless otherwise specified. Output Voltage (Note 17) 1.62 1.8 1.98 Vpp S/(N+D) (0dBFS) 70 80 - dB S/N (A-weighted) 82 92 - dB Interchannel Isolation 85 95 - dB Interchannel Gain Mismatch - 0 0.8 dB Load Resistance 10 - - kΩ Load Capacitance - - 30 pF PSRR (Note 18) 217Hz - 75 - dB 1kHz - 75 - dB Mono Line Output Characteristics: Stereo DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, OVOL=0dB, LVL=0dB, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential) Output Voltage (Note 19) 3.24 3.6 3.96 Vpp S/(N+D) (0dBFS) - 73 - dB S/N (A-weighted) - 95 - dB Load Resistance (LOP/LON pins, respectively) (Note 20) 10 - - kΩ Load Capacitance (LOP/LON pins, respectively) (Note 21) - - 30 pF PSRR (Note 18) 217Hz - 70 - dB 1kHz - 70 - dB Mono Receiver-Amp Output Characteristics: DAC(Stereo, Note 22) → RCP/RCN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, RCVG=−6dB, RL=32Ω, BTL; unless otherwise specified. Output Voltage (Note 23) 0dBFS 1.76 1.96 2.16 Vpp 0dBFS, RCVG=0dB - 3.91 - Vpp S/(N+D) 0dBFS 40 59 - dB 0dBFS, RCVG=0dB - 55 - dB S/N (A-weighted) (DAC Æ RCP/RCN pins) 84 94 - dB Output Noise Level (A-weighted, RCVG = −9dB) - −100 - dBV Load Resistance 32 - - Ω Load Capacitance (Note 21) - - 30 pF PSRR (Note 18) 217Hz - 75 - dB 1kHz - 75 - dB Note 17. Output voltage is proportional to AVDD voltage. Vout = 1.0 x AVDD Vpp(typ) Note 18. PSRR is referred to SVDD with 200mVpp sine wave. Note 19. Output voltage is proportional to AVDD voltage. Vout = (LOP) – (LON) = 2.0 x AVDD Vpp(typ) Note 20. This is a resistance value between output pin and VSS1. When a resistor is connected between output pins, load resistance for each output pin is half. Therefore, it is n ecessary to decide load resi stance in consideration of these. Note 21. This is a capacitance value between output pin and VSS1. When a capacitor is connected between output pins, load capacitance for each output pin doubles. Therefore, it is necessary to decide load capacitance in consideration of these. Note 22. Input signal of left and right channels is same phase and level. Note 23. Output voltage is proportional to AVDD voltage. Vout = (RCP) – (RCN) = 2.17 x AVDD Vpp(typ) Po = 15mW @ 32Ω, Vout = 1.96Vpp. Po = 60mW @ 32Ω, Vout = 3.91Vpp.

[AK4679] MS1402-E-06 2013/02 - 16 - Parameter min typ max Unit Headphone-Amp Characteristics: DAC(Stereo, Note 22) → HPL/HPR pins, ALC=OFF, IVOL=0dB, OVOL=0dB, HPG=0dB, RL=32Ω Output Voltage (Note 24) 0dBFS, RL = 32Ω, HPG=−4dB 1.44 1.6 1.76 Vpp 0dBFS, RL = 16Ω, HPG=−4dB - 1.6 - Vpp 0dBFS, RL = 32Ω, HPG=0dB - 2.5 - Vpp 0dBFS, RL = 16Ω, HPG=0dB - 0.85 - Vrms S/(N+D) 0dBFS, RL = 32Ω, HPG=−4dB 50 73 - dB 0dBFS, RL = 16Ω, HPG=−4dB - 67 - dB 0dBFS, RL = 32Ω HPG=0dB - 73 - dB 0dBFS, RL = 16Ω HPG=0dB - 20 - dB S/N (A-weighted) 85 95 - dB Output Noise Level (A-weighted, HPG=−14dB) - −106 - dBV Interchannel Isolation 60 80 - dB Interchannel Gain Mismatch - 0 0.8 dB Load Resistance 16 32 - Ω Load Capacitance (Note 25) - - 300 pF PSRR (Note 26) 217Hz - 70 - dB 1kHz - 60 - dB DC-offset (HPG ≤ −4dB) −1 0 1 mV Speaker-Amp Characteristics: DAC(stereo, Note 27 ) → SPP/SPN pins, ALC=OFF, IVOL=0dB, OVOL=0dB, SPKG=−6dB, RL=8Ω + 10μH Output Power SVDD=5.0V, THD+N = 10% - 1.57 - W SVDD=4.2V, THD+N = 10% - 1.1 - W SVDD=4.2V, THD+N = 1% - 0.89 - W SVDD=3.7V, THD+N = 1% - 0.69 - W Output Voltage (−3dBFS) (Note 28) 5.0 5.4 6.2 Vpp S/(N+D) (SVDD=3.7V, Po=0.35W) 40 59 - dB Output Noise Level (A-weighted) (Note 29) - −82 −73 dBV Load Resistance 8 - - Ω Load Capacitance (Note 25) - - 300 pF PSRR (Note 30) 217Hz - 63 - dB 1kHz - 63 - dB DC-offset −10 0 10 mV Current Limit (Note 31) - 40 80 mA Note 24. The Output voltage is proportional to AVDD voltage. Vout = 1.4 x AVDD Vpp(typ). Po = 10mW @ 32Ω, Vout = 1.6Vpp. Po = 25mW @ 32Ω, Vout = 2.5Vpp. Po = 20mW @ 16Ω, Vout = 1.6Vpp. Po = 45mW @ 16Ω, Vout = 0.85Vrms. Note 25. Load Capacitance for VSS1. Note 26. PSRR is referred to PVDD with 200mVpp sine wave. Note 27. Input signal of left and right channels is same phase and level. Note 28. Output voltage is proportional to AVDD voltage. Vout = (SPP) – (SPN) = 3.0 x AVDD Vpp(typ). Note 29. In case of mono signal input (e.g. Lch only) and SPKG=0dB, output noise level is -84dBV. Note 30. PSRR is referred to SVDD with 200mVpp sine wave. Note 31. The average current between SVDD and VSS3 when the SPP and SPN pins are shorted and output power is 890mW.

[AK4679] MS1402-E-06 2013/02 - 17 - Parameter min typ max Unit Stereo Line Output Volume Characteristics: Gain Setting -9 - +6 dB Step Width 1 3 5 dB Headphone Output Volume Characteristics: Gain Setting −62 - +6 dB Step Width Gain: +6 ~ −40dB 1 2 3 dB Gain: −40 ~ −62dB - 2 - dB Speaker Output Volume Characteristics: Gain Setting −30 - +12 dB Step Width 1 3 5 dB Receiver Output Volume Characteristics: Gain Setting −30 - +12 dB Step Width 1 3 5 dB

MPWR1 and MPWR2 pins are 0mA. Note 34. All digital input pins are fixed to each supply pin TVDDA, TVDDE or VSS2, VSS4. Note 35. AVDD, DVDD, PVDD, TVDDA, VDDE and TVDDE are powered OFF. connecting DIN1 with DOUT2 and DIN2 with DOUT1. BICK=64fs; No data input, Receiver / Speaker / Headphone = No Load. Table 1. Power Consumption for Each Operation Mode (typ)

[AK4679] MS1402-E-06 2013/02 - 19 - SRC CHARACTERISTICS (Ta=25°C; AVDD=PVDD= DVDD=TVDDA=TVDDE =1.8V, SVDD=4.2V, VDDE=1.2V; VSS1=VSS2=VSS3=VSS4 =VSS5 =0V; Signal Frequency=1kHz; 16bit Data; Measurement Bandwidth=20Hz ∼ FSO/2kHz; unless otherwise specified) Parameter Symbol min typ max Unit SRC Characteristics (SRCAI): SDTIA Æ SRCAI Æ SDTO Resolution - - 16 Bits Input Sample Rate FSI 8 - 16 kHz Output Sample Rate FSO 8 - 48 kHz THD+N (Input = 1kHz, −1dBFS, Note 43) FSO/FSI = 44.1kHz/8kHz - −88 - dB Dynamic Range (Input = 1kHz, −60dBFS, Note 43) FSO/FSI = 44.1kHz/8kHz - 98 - dB Ratio between Input and Output Sample Rate FSO/FSI 1/2 6 - SRC Characteristics (SRCAO): SDTI Æ SRCAO Æ SDTOA Resolution - - 16 Bits Input Sample Rate FSI 8 - 48 kHz Output Sample Rate FSO 8 - 16 kHz THD+N (Input = 1kHz, −1dBFS, Note 43) FSO/FSI = 8kHz/44.1kHz - −75 - dB FSO/FSI = 16kHz /8kHz - −88 - dB Dynamic Range (Input = 1kHz, −60dBFS, Note 43) FSO/FSI = 8kHz/44.1kHz - 100 - dB FSO/FSI = 16kHz /8kHz - 99 - dB Ratio between Input and Output Sample Rate FSO/FSI 1/6 2 - SRC Characteristics (SRCBI, SRCBO): SDTI Æ SRCBO Æ SDTOB, SDTIB Æ SRCBI Æ SDTO Resolution - - 16 Bits Input Sample Rate FSI 8 - 48 kHz Output Sample Rate FSO 8 - 48 kHz THD+N (Input = 1kHz, −1dBFS, Note 43) FSO/FSI = 8kHz/44.1kHz FSO/FSI = 44.1kHz/8kHz - −75 −88 dB dB Dynamic Range (Input = 1kHz, −60dBFS, Note 43) FSO/FSI = 8kHz/44.1kHz FSO/FSI = 44.1kHz/8kHz - 100 dB dB Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 - Note 43. Measured by Audio Precision System Two Cascade.

[AK4679] MS1402-E-06 2013/02 - 20 - FILTER CHARACTERISTICS (CODEC) VDDE=1.1~1.3V; fs=44.1kHz; Programmable Filter=OFF) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): Passband (Note 44) ±0.16dB PB 0 - 17.3 kHz −0.66dB - 19.4 - kHz −1.1dB - 19.9 - kHz −6.9dB - 22.1 - kHz Stopband (Note 44) SB 26.1 - - kHz Passband Ripple PR - - ±0.16 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 45) GD - 20 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response −3.0dB FR - 3.4 - Hz −0.5dB - 10 - Hz −0.1dB - 22 - Hz DAC Digital Filter (LPF): Passband (Note 44) ±0.05dB PB 0 - 20.0 kHz −6.0dB - 22.05 - kHz Stopband (Note 44) SB 24.1 - - kHz Passband Ripple PR - - ±0.05 dB Stopband Attenuation SA 54 - - dB Group Delay (Note 45) GD - 25 - 1/fs DAC Digital Filter (LPF) + SCF + SMF: Frequency Response: 0 ∼ 20.0kHz FR - ±1.0 - dB Note 44. The passband and stopband frequencies scale with fs (system sampling rate). For example, DAC is PB=0.454 x fs (@±0.05dB). Each response refers to that of 1kHz. Note 45. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 24-bit data of both channels from the input register to the output register of the ADC. This time includes group delay of the HPF and Programmable filter. For the DAC, this time is from setting the 24-bit data of both channels from the input register to the output of analog signal and includes selector block (SDMIN, PFMXL/R and SRMXL/R), DRC, 5-band EQ and DATT-A. For the signal through the programmable filters, group delay is increased 4/fs at Playback Mode from the value above if there is no phase changed by the IIR filter.

[AK4679] MS1402-E-06 2013/02 - 21 - FILTER CHARACTERISTICS (SRC) VDDE=1.1~1.3V; Programmable Filter=OFF) Parameter Symbol min typ max Unit Digital Filter −0.23dB 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 - 0.4583FSI kHz −0.20dB 0.905 ≤ FSO/FSI < 0.985 PB 0 - 0.4167FSI kHz −0.13dB 0.714 ≤ FSO/FSI < 0.905 PB 0 - 0.3104FSI kHz −0.11dB 0.656 ≤ FSO/FSI < 0.714 PB 0 - 0.2813FSI kHz −0.10dB 0.492 ≤ FSO/FSI < 0.656 PB 0 - 0.2167FSI kHz −0.09dB 0.452 ≤ FSO/FSI < 0.492 PB 0 - 0.1948FSI kHz −0.07dB 0.357 ≤ FSO/FSI < 0.452 PB 0 - 0.1458FSI kHz −0.07dB 0.324 ≤ FSO/FSI < 0.357 PB 0 - 0.1271FSI kHz −0.06dB 0.226 ≤ FSO/FSI < 0.324 PB 0 - 0.0729FSI kHz Passband −0.17dB 0.1667 ≤ FSO/FSI < 0.226 PB 0 - 0.0625FSI kHz 0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI - - kHz 0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI - - kHz 0.714 ≤ FSO/FSI < 0.905 SB 0.3958FSI - - kHz 0.656 ≤ FSO/FSI < 0.714 SB 0.3667FSI - - kHz 0.492 ≤ FSO/FSI < 0.656 SB 0.3021FSI - - kHz 0.452 ≤ FSO/FSI < 0.492 SB 0.2802FSI - - kHz 0.357 ≤ FSO/FSI < 0.452 SB 0.2313FSI - - kHz 0.324 ≤ FSO/FSI < 0.357 SB 0.2125FSI - - kHz 0.226 ≤ FSO/FSI <0.324 SB 0.1583FSI - - kHz Stopband 0.1667 ≤ FSO/FSI < 0.226 SB 0.1271FSI - - kHz 0.985 ≤ FSO/FSI ≤ 6.000 SA 87.0 - - dB 0.905 ≤ FSO/FSI < 0.985 SA 88.0 - - dB 0.714 ≤ FSO/FSI < 0.905 SA 87.5 - - dB 0.656 ≤ FSO/FSI < 0.714 SA 86.8 - - dB 0.492 ≤ FSO/FSI < 0.656 SA 86.4 - - dB 0.452 ≤ FSO/FSI < 0.492 SA 86.0 - - dB 0.357 ≤ FSO/FSI < 0.452 SA 86.6 - - dB 0.324 ≤ FSO/FSI < 0.357 SA 86.1 - - dB 0.226 ≤ FSO/FSI < 0.324 SA 85.7 - - dB Stopband Attenuation 0.1667 ≤ FSO/FSI < 0.226 SA 72.8 - - dB Group Delay (Note 46) PCM I/F A Æ PCM I/F B (PMMIX bit=“0”) GD - 30/fs2+10.5/fs3 - s (PMMIX bit=“1”) GD - 29.5/fs2+37.5/fs3 +9.5/fs - s PCM I/F B Æ PCM I/F A (PMMIX bit=“0”) GD - 30/fs2+10.5/fs3 - s (PMMIX bit=“1”) GD - 29.5/fs2+37.5/fs3 +9.5/fs - s PCM I/F A Æ SDTO GD - 29.5/fs2+11.5/fs - s PCM I/F B Æ SDTO GD - 29.5/fs2+12.5/fs - s PCM I/F A Æ 5-band EQ Æ DATT-A Æ DRC Æ DAC Digital Output (Note 47) GD - 29.5/fs2+32.5/fs - s PCM I/F B Æ 5-band EQ Æ DATT-A Æ DRC Æ DAC Digital Output (Note 47) GD - 29.5/fs2+33.5/fs - s Note 46. This value is the time from the rising edge of LRCK, SYNCA or SYNCB after data is input to rising edge of LRCK after data is output, when LRCK, SYNCA or SYNCB for Output data corresponds with SYNCA or SYNCB for Input. fs: LRCK Frequency, fs2: SYNCA Frequency, fs3: SYNCB Frequency. Note 47. This value includes group delay of DAC digital filter.

[AK4679] MS1402-E-06 2013/02 - 22 - DC CHARACTERISTICS Parameter Symbol min typ max Unit High-Level Input Voltage 2.2V ≤TVDDA≤3.6V VIH1 70 %TVDDA - - V (Note 48) 1.6V ≤TVDDA<2.2V VIH1 80 %TVDDA - - V Low-Level Input Voltage 2.2V ≤TVDDA≤3.6V VIL1 - - 30 %TVDDA V (Note 48) 1.6V ≤TVDDA<2.2V VIL1 - - 20 %TVDDA V High-Level Output Voltage (Note 49)(Iout=−200μA) VOH1 TVDDA−0.2 - - V Low-Level Output Voltage - - V (Note 49)(Iout=200μA) VOL1 - - 0.2 V (SDAA pin, 2.0V≤TVDDA≤3.6V: Iout=3mA) VOL2 - - 0.4 V (SDAA pin, 1.6V≤TVDDA<2.0V: Iout=3mA) VOL2 - - 20%TVDDA V Input Leakage Current (Note 50) Iind - - ±2 μA Digital MIC Interface (DMDAT pin Input; DMIC bit = “1”) High-Level Input Voltage Low-Level Input Voltage VIH3 VIL3 65%AVDD 35%AVDD V V Digital MIC Interface (DMCLK pin Output; DMIC bit = “1”) High-Level Output Voltage (Iout=−80μA) Low-Level Output Voltage (Iout= 80μA) VOH3 VOL3 AVDD-0.4 0.4 V V Input Leakage Current (Note 50) Iin - - ±10 μA Note 48. BICK, LRCK, SDTI, MCKI, PDNA, BICKA, SYNCA, SDTIA, BICKB, SYNCB, SDTIB, SCLA and SDAA pins. Note 49. BICK, LRCK SDTO, SDTOA and SDTOB pins Note 50. SYNCB, BICKB, SDTIB, SDTI, LRCK, MCKI, BICK, SCLA, SDAA, SDTIA, BICKA and SYNCA pins. I/O pins (LRCK, BICK and SDAA pins) are at the time of Input state. Parameter Symbol min typ max Unit High level input voltage VIH 70%TVDDE - - V Low level input voltage VIL - - 30%TVDDE V High level output voltage Iout=-200μA (Note 51) VOH TVDDE-0.2 - - V Low level output voltage Iout= 200μA (Note 51) VOL - - 0.2 V Low-level Output Voltage (SDAE pin, TVDDE ≥ 2.0V: Iout=3mA) VOL - - 0.4 V (SDAE pin, TVDDE < 2.0V: Iout=3mA) VOL - - 20%TVDDE V Input leakage current Iin - - ±10 μA Note 51. Except for the SDAE pin.

[AK4679] MS1402-E-06 2013/02 - 23 - SWITCHING CHARACTERISTICS CL=20pF or 400pF (SDAA, SDAE pin); unless otherwise specified) Parameter Symbol min typ max Unit PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Output Timing Frequency fs - Table 7 - kHz DSP Mode: Pulse Width High tLRCKH - tBCK - ns Except DSP Mode: Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 8 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK−60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns

[AK4679] MS1402-E-06 2013/02 - 24 - Parameter Symbol min typ max Unit External Slave Mode MCKI Input Timing Frequency 256fs fCLK 2.048 - 12.288 MHz 512fs fCLK 4.096 - 12.288 MHz 1024fs fCLK 8.192 - 12.288 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Input Timing Frequency 256fs fs 8 - 48 kHz 512fs fs 8 - 24 kHz 1024fs fs 8 - 12 kHz DSP Mode: Pulse Width High tLRCKH tBCK−60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period ( Note 52) tBCK 312.5 or 1/(126fs) - - ns s Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns External Master Mode MCKI Input Timing Frequency 256fs fCLK 2.048 - 12.288 MHz 512fs fCLK 4.096 - 12.288 MHz 1024fs fCLK 8.192 - 12.288 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Output Timing Frequency fs 8 - 48 kHz DSP Mode: Pulse Width High tLRCKH - tBCK - ns Except DSP Mode: Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % Note 52. The minimum value is longer time between 312.5ns and 1/(126fs)s.

[AK4679] MS1402-E-06 2013/02 - 25 - Parameter Symbol min typ max Unit Audio Interface Timing (DSP Mode) Master Mode LRCK “↑” to BICK “↑” (Note 53) tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns LRCK “↑” to BICK “↓” (Note 54) tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns BICK “↑” to SDTO (BCKP bit = “0”) tBSD −70 - 70 ns BICK “↓” to SDTO (BCKP bit = “1”) tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK “↑” to BICK “↑” (Note 53) tLRB 0.4 x tBCK - - ns LRCK “↑” to BICK “↓” (Note 54) tLRB 0.4 x tBCK - - ns BICK “↑” to LRCK “↑” (Note 53) tBLR 0.4 x tBCK - - ns BICK “↓” to LRCK “↑” (Note 54) tBLR 0.4 x tBCK - - ns BICK “↑” to SDTO (BCKP bit = “0”) tBSD - - 80 ns BICK “↓” to SDTO (BCKP bit = “1”) tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Audio Interface Timing (Right/Left justified & I2S) Master Mode BICK “↓” to LRCK Edge (Note 55) tMBLR −40 - 40 ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD −70 ns BICK “↓” to SDTO tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK Edge to BICK “↑” (Note 55) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 55) tBLR 50 - - ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD ns BICK “↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Note 53. MSBS, BCKP bits = “00” or “11”. Note 54. MSBS, BCKP bits = “01” or “10”. Note 55. BICK rising edge must not occur at the same time as LRCK edge.

[AK4679] MS1402-E-06 2013/02 - 26 - Parameter Symbol min typ max Unit PCM Interface Timing (BICKA, SYNCA, SDTIA, SDTOA pins): SYNCA Timing Frequency fs2 8 - 16 kHz Serial Interface Timing at Short/long Frame Sync BICKA Frequency fBCK2 128 - 4096 kHz BICKA Period tBCK2 244 - - ns BICKA Pulse Width Low tBCKL2 100 - - ns Pulse Width High tBCKH2 100 - - ns SYNCA Edge to BICKA “↓” (Note 56) tSYB2 40 - - ns SYNCA Edge to BICKA “↑” (Note 57) tSYB2 40 - - ns BICKA “↓” to SYNCA Edge (Note 56) tBSY2 40 - - ns BICKA “↑” to SYNCA Edge (Note 57) tBSY2 40 - - ns SYNCA to SDTOA (MSB) (Except Short Frame) tSYD2 - - 60 ns BICKA “↑” to SDTOA (BCKPA bit = “0”) tBSD2 - - 60 ns BICKA “↓” to SDTOA (BCKPA bit = “1”) tBSD2 - - 60 ns SDTIA Hold Time tSDH2 25 - - ns SDTIA Setup Time tSDS2 25 - - ns SYNCA Pulse Width Low tSYL2 0.8 x tBCK2 - - ns Pulse Width High tSYH2 0.8 x tBCK2 - - ns Serial Interface Timing at MSB justified and I2S BICKA Frequency fBCK2 256 - 3072 kHz BICKA Period tBCK2 312.5 - - ns BICKA Pulse Width Low tBCKL2 130 - - ns Pulse Width High tBCKH2 130 - - ns SYNCA Edge to BICKA “↑” tSYB2 50 - - ns BICKA “↑” to SYNCA Edge tBSY2 50 - - ns SYNCA to SDTOA (MSB) (Except I2S mode) tSYD2 - - 80 ns BICKA “↓” to SDTOA tBSD2 - - 80 ns SDTIA Hold Time tSDH2 50 - - ns SDTIA Setup Time tSDS2 50 - - ns SYNCA Duty Cycle dSYC2 45 50 55 % Note 56. MSBSA, BCKPA bits = “00” or “11”. Note 57. MSBSA, BCKPA bits = “01” or “10”.

[AK4679] MS1402-E-06 2013/02 - 27 - Parameter Symbol min typ max Unit PCM Interface Timing (BICKB, SYNCB, SDTIB, SDTOB pins): SYNCB Timing Frequency fs3 8 - 48 kHz Serial Interface Timing at Short/long Frame Sync BICKB Frequency fBCK3 128 - 4096 kHz BICKB Period tBCK3 244 - - ns BICKB Pulse Width Low tBCKL3 100 - - ns Pulse Width High tBCKH3 100 - - ns SYNCB Edge to BICKB “↓” (Note 58) tSYB3 40 - - ns SYNCB Edge to BICKB “↑” (Note 59) tSYB3 40 - - ns BICKB “↓” to SYNCB Edge (Note 58) tBSY3 40 - - ns BICKB “↑” to SYNCB Edge (Note 59) tBSY3 40 - - ns SYNCB to SDTOB (MSB) (Except Short Frame) tSYD3 - - 60 ns BICKB “↑” to SDTOB (BCKPB bit = “0”) tBSD3 - - 60 ns BICKB “↓” to SDTOB (BCKPB bit = “1”) tBSD3 - - 60 ns SDTIB Hold Time tSDH3 25 - - ns SDTIB Setup Time tSDS3 25 - - ns SYNCB Pulse Width Low tSYL3 0.8 x tBCK3 - - ns Pulse Width High tSYH3 0.8 x tBCK3 - - ns Serial Interface Timing at MSB justified and I2S BICKB Frequency fBCK3 256 - 3072 kHz BICKB Period tBCK3 312.5 - - ns BICKB Pulse Width Low tBCKL3 130 - - ns Pulse Width High tBCKH3 130 - - ns SYNCB Edge to BICKB “↑” tSYB3 50 - - ns BICKB “↑” to SYNCB Edge tBSY3 50 - - ns SYNCB to SDTOB (MSB) (Except I2S mode) tSYD3 - - 80 ns BICKB “↓” to SDTOB tBSD3 - - 80 ns SDTIB Hold Time tSDH3 50 - - ns SDTIB Setup Time tSDS3 50 - - ns SYNCB Duty Cycle dSYC3 45 50 55 % Note 58. MSBSB, BCKPB bits = “00” or “11”. Note 59. MSBSB, BCKPB bits = “01” or “10”.

[AK4679] MS1402-E-06 2013/02 - 28 - Parameter Symbol min typ max Unit SYNC1/3, BCLK1/BCLK3 Input Timing SYNC1/3 Input Timing SYNC1/3 frequency fs 8 48 kHz BCLK1 Input Timing (Note 60, Note 61) fBCLK 64 3072 kHz Pulse width Low tBCKL1 0.4 x tBCLK ns Pulse width High tBCKH1 0.4x tBCLK ns Note 60. SYNC1 and BCLK1 or SYNC3 and BCLK3 should be synchronized and their sampling rates (fs) should be stable Note 61. fBCLK ≥ 4 x N x fs (N=1, 2, 3….) Parameter Symbol min typ max Unit SDIN1, SDIN3, SDIN4, SDOUT1, SDOUT3, SDOUT4 Delay Time from BICLK1 “↑” to SYNC1 “↑” (Note 62) tBSYD 20 ns Delay Time from SYNC1 “↓” to BICK1 “↑” (Note 62) tSYBD 100 ns Serial Data Input Latch Setup Time tB1IDS 40 ns Serial Data Input Latch Hold Time tB1IDH 40 ns Delay Time from SYNC1 to Serial Data Output tSY1OD 40 ns Delay Time from BICK1 “↓” to Serial Data Output (Note 63) tB1OD 40 ns SDIN2, SDOUT2 SYNC2 Duty cycle 50 % Serial Data Input Latch Setup Time tB2IDS 40 ns Serial Data Input Latch Hold Time tB2IDH 40 ns Delay Time from SYNC2 to Serial Data Outputs tSY2OD 40 ns Delay Time from BCLK2 “↓”to Serial Data Output (Note 64) tB2OD 40 ns SDINn → SDOUTn (n=1, 2, 3, 4) Delay time from SDINn to SDOUTn Output tIOD 60 ns Note 62. BICK1 edge must not occur at the same time as SYNC1 edge. Note 63. When the polarity of BICK1 is inverted, delay time is from BICK1 “↑”. Note 64. When the polarity of BICK2 is inverted, delay time is from BICK2 “↑”

[AK4679] MS1402-E-06 2013/02 - 29 - Parameter Symbol min typ max Unit Control Interface Timing (I2C Bus mode): (Note 65, Note 66) SCL Clock Frequency fSCL 30 - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μs Clock Low Time tLOW 1.3 - - μs Clock High Time tHIGH 0.6 - - μs Setup Time for Repeated Start Condition tSU:STA 0.6 - - μs SDA Hold Time from SCL Falling ( Note 67) tHD:DAT 0 - - μs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μs Rise Time of Both SDA and SCL Lines tR - - 0.3 μs Fall Time of Both SDA and SCL Lines tF - - 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 - - μs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppre ssed by Input Filter tSP 0 - 50 ns Digital Audio Interface Timing: CL=100pF DMCLK Output Timing Period tSCK - 1/(64fs) - ns Rising Time tSRise - - 10 ns Falling Time tSFall - - 10 ns Duty Cycle dSCK 45 50 55 % Audio Interface Timing DMDAT Setup Time tDMS 50 - - ns DMDAT Hold Time tDMH 0 - - ns Power-down & Reset Timing PDNA Accept Pulse Width (Note 68) PDNE Accept Pulse Width (Note 68) tAPDA tAPDE 1.5 0.6 μs μs PDN Reject Pulse Width (Note 68) tRPD - - 50 ns PMADL or PMADR “↑” to SDTO valid (Note 69) ADRST bit = “0” ADRST bit = “1” tPDV tPDV 1059 267 1/fs 1/fs PMDML or PMDMR “↑” to SDTO valid (Note 70) ADRST bit = “0” ADRST bit = “1” tPDV tPDV 1059 267 1/fs 1/fs PMSRAO “↑” to SDTOA valid (Note 71) tPDV2 - 164 1/fs2 PMSRBO “↑” to SDTOB valid (Note 72) tPDV3 - 164 1/fs3 Note 65. SDA means both SDAA and SDAE pins. SCL means both SCLA and SCLE pins. Note 66. I2C-bus is a registered trademark of NXP B.V. Note 67. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 68. The audio block of AK4679 can be reset by bringing PDNA pin = “L” to “H” only upon power up. The PDNA pin must held “L” for more than 1.5μs for a certain reset. The DSP block can be reset by bringing PDNE pin = “L” to “H” only upon power up. The PDNE pin must held “L” for more than 0.6μs for a certain reset. The AK4679 is not reset by the “L” pulse less than 50ns. Note 69. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. Note 70. This is the count of LRCK “↑” from the PMDML or PMDMR bit = “1”. Note 71. This is the count of SYNCA “↑” from the PMSRAO bit = “1”. Note 72. This is the count of SYNCB “↑” from the PMSRBO bit = “1”.

[AK4679] MS1402-E-06 2013/02 - 30 - Note 73. Except when input the eighth bit of the command code. Parameter Symbol min typ max Unit Control Interface Timing (SPI mode) SCLK Fall Time tSF 30 ns SCLK Rise Time tSR 30 ns SCLK Frequency fSCLK 4.0 MHz SCLK Low Level Width tSCLKL 120 ns SCLK High Level Width tSCLKH 120 ns CSN High Level Width tWRQH 500 ns tRST1 tIRRQ 600 100 ns μs From SCLK “↑” to CSN “↑” tWSC 500 ns From SCLK “↑” to CSN “↑” tSCW 800 ns SI Latch Setup Time tSIS 100 ns SI Latch Hold Time tSIH 100 ns Delay Time from SCLK “↓”to SO Output tSOS 100 ns Hold Time from SCLK “↑” to SO Output (Note 73) tSOH 100 ns

Figure 31. μP Interface 1 (SPI)

Base-band must be supplied to the AK4679 during an operation. Figure 38. Connection Diagram Example

Table 2. Clock Mode Setting (x: Don’t care) Table 3. Clock pins state in Clock Mode to master mode by changing M/S bit = “1”.

0 Slave Mode (default)

1 Master Mode

Table 4. Select Master/Slave Mode

PLL is powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency changes. **Table 5. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)** Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (N/A: Not available) clock input, the sampling frequency generated by PLL is the same sampling frequency of mode name.

Note 75. These are rounded off to six decimal places. Table 7. Sampling Frequency at PLL mode (Reference clock is MCKI)

Note 75. These are rounded off to six decimal places. Table 7. Sampling Frequency at PLL mode (Reference clock is MCKI) (2)

Table 8. Clock Operation in PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) bit (Table 9). Sampling frequency mode is selected by FS3-0 bits (Table 6, Table 7). Figure 39. PLL Master Mode (x=1 to 4) Table 9. BICK Output Frequency in Master Mode

by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5). BICK input should be synchronized to LRCK input. Sampling frequency can be selected by FS3-0 bits (Table 6). Figure 40. PLL Slave Mode (PLL Reference Clock: BICK pin) (x=1 to 4)

Table 10) and sampling frequency is selected by FS3-0 bits (Table 11). case, BICK and LRCK can be stopped. Table 10. MCKI Frequency in EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) Table 11. Setting of Sampling Frequency (N/A: Not available) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 41. EXT Slave Mode (x=1 to 4)

Table 13. MCKI Frequency in EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) Table 14. Setting of Sampling Frequency (N/A: Not available) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. LOUT/ROUT pins at fs=8kHz is shown in Table 15. Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 42. EXT Master Mode (x=1 to 4) Table 16. BICK Output Frequency in Master Mode

Figure 54). Digital microphone input is selected when DMIC bit = “1”. Table 20. MIC-Amp Input Signal at DMIC bit = “0” (N/A: Not available)

the MGNL3-0 and MGNR3-0 bits (Table 21). Table 21. Mic Input Gain (N/A: Not available)

Table 22). The load resistance is minimum 1kΩ for each MPWR1 pin and MPWR2 pin. connected directly to the MPWR1 pin (MPWR2 pin) (Figure 56). Table 22. MIC Power 1, MC Power 2 Output Level

0 Hi-Z (default)

1 Output

Table 23. MIC Power 1 Status Table 24. MIC Power 2 Status Figure 56. MIC Block Circuit

and positive full-scale with the 100% 1’s density of 1bit output data.

0 Rch Lch (default)

1 Lch Rch

Table 25. Data In/Output Timing with Digital MIC Figure 59. Data In/Output Timing with Digital MIC (DCLKP bit = “1”) Figure 60. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)

PMADR, PMDAL, PMDAR, PMPFIL, PMEQ, PMDRC, PMSRAI, PMSRAO, PMSRBI and PMSRBO bits). Figure 61. Path Select of Digital Block

[AK4679] MS1402-E-06 2013/02 - 67 - 1. ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”. 2. HPF1: Include the Digital Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”. 3. DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”. 4. HPF2: High Pass Filter. Applicable to use as Wind-Noise Reduction Filter. (See “Digital Programmable Filter”.) 5. LPF: Low Pass Filter (See “Digital Programmable Filter”.) 6. Stereo Separation: Stereo Separation Emphasis Filter & Gain Compensation. (See “Digital Programmable Filter”.) Gain Compensation is composed with EQ0 and Gain blocks. This block adjusts the frequency response after Stereo Separation Emphasis. 7. 3-Band Notch: Applicable to use as Equalizer or Notch Filter. (See “Digital Programmable Filter”.) 8. ALC: Input Digital Volume with ALC function. (See “Input Digital Volume” and “ALC Operation”.) 9. SVOLA: Side Tone Volume at Internal MIC/SPK or External Headset Phone Call. (See “Side Tone Volume”.) 10. 5-Band EQ: Equalizer for playback path. (See “5-band Equalizer”.) 11. DATT-A: Digital Volume for playback path. (See “Digital Output Volume”.) 12. SMUTE: Soft mute. (See “Soft Mute”.) 13. DRC: Dynamic Range Control for playback path. (See “Dynamic Range Control”.) 14. DATT-B: Digital Volume for Recording of Received Voice. (See “Digital Volume for Recording of Received Voice”) 15. DATT-C: Digital Volume of Received Voice. (See “Digital Volume for Received Voice”) 16. SVOLB: Side Tone Volume at B/T Headset Phone Call. (See “Side Tone Volume for B/T Phone Call”.)

Table 26. Recode/Playback Mode (x: Don’t care) Figure 62. Path at Recording Mode 1

5 Band

Figure 63. Path at Recording Mode 1 & Playback Mode 2 Figure 64. Path at Playback Mode 1 Figure 65. Path at Playback Mode 2

[AK4679] MS1402-E-06 2013/02 - 69 - ■ Digital Programmable Filter (1) High Pass Filter (HPF2) Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when HPF bit = “0” or PMPFIL bit = “0”. The HPF2 starts operation 4/fs(max) after when HPF bit = “1” and PMPFIL bit = “1” are set. fs: Sampling frequency fc: Cut-off frequency Register setting ( Note 77) HPF: F1A[13:0] bits =A, F1B[13:0] bits =B (MSB=F1A13, F1B13; LSB=F1A0, F1B0) A = 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 − z −1 1 + Bz −1 The cut-off frequency should be set as below. fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz) (2) Low Pass Filter (LPF) This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when LPF bit = “0” or PMPFIL bit = “0”. The LPF starts operation 4/fs(max) after when LPF bit = “1” and PMPFIL bit = “1” are set. fs: Sampling frequency fc: Cut-off frequency Register setting ( Note 77) LPF: F2A[13:0] bits =A, F2B[13:0] bits =B (MSB=F2A13, F1B13; LSB=F2A0, F2B0) A = 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 + z −1 1 + Bz −1 The cut-off frequency should be set as below. fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)

[AK4679] MS1402-E-06 2013/02 - 70 - (3) Stereo Separation Emphasis Filter (FIL3) FIL3 is used to emphasize the stereo separation of stereo mic recording data or playback data. F3A13-0 and F3B13-0 bits set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at F3AS bit = “1”. FIL3 bit controls ON/OFF of FIL3. When Stereo Separation Emphasis Filter is OFF, the audio data passes this block by 0dB gain. The coefficient should be set when FIL3 bit = “0” or PMPFIL bit = “0”. The FIL3 starts operation 4/fs(max) after when FIL3 bit = “1” and PMPFIL bit = “1” are set. 1) When FIL3 is set to “HPF” fs: Sampling frequency fc: Cut-off frequency K: Filter gain [dB] (0dB ≥ K ≥ −10dB) Register setting ( Note 77) FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F3A13, F3B13; LSB=F3A0, F3B0) A = 10K/20 x 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 − z −1 1 + Bz −1 2) When FIL3 is set to “LPF” fs: Sampling frequency fc: Cut-off frequency K: Filter gain [dB] (0dB ≥ K ≥ −10dB) Register setting ( Note 77) FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F3A13, F3B13; LSB= F3A0, F3B0) A = 10K/20 x 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 + z −1 1 + Bz −1

Figure 66. EQ0 Frequency Response Table 27. Gain select of gain block (x: Don’t care)

[AK4679] MS1402-E-06 2013/02 - 72 - (5) 3-band Equalizer This block can be used as Equalizer or Notch Filter. 3-band Equalizer (EQ1, EQ2 and EQ3) is selected ON/OFF independently by EQ1, EQ2 and EQ3 bits. When Equalizer is OFF, the audio data passes this block by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. The EQx (x=1∼3) coefficient must be set when EQx bit = “0” or PMPFIL bit = “0”. EQ1-3 start operation 4/fs(max) after when (EQx (x=1~3) = “1”) and PMPFIL bit = “1” is set fs: Sampling frequency fo 1 ~ fo3: Center frequency fb1 ~ fb3: Band width where the gain is 3dB different from center frequency K1 ~ K3 : Gain (−1 ≤ Kn ≤ 3) Register setting (Note 77) EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1 EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2 EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3 (MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0) An = Kn x tan (πfbn/fs) 1 + tan (πfbn/fs) Bn = cos(2π fon/fs) x 1 + tan (πfbn/fs) , C n = 1 − tan (πfbn/fs) 1 + tan (πfbn/fs) (n = 1, 2, 3) Transfer function hn (z) = An 1 − z −2 1− Bnz −1− Cnz −2 H(z) = 1 + h1(z) + h2(z) + h3(z) (n = 1, 2, 3) The center frequency should be set as below. 0.003 < fon / fs < 0.497 Note 77. [Translation the filter coefficient calculated by th e equations above from real num ber to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 2 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit.

and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 29). at the zero crossing timeout. by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting LMAT1-0 bits. the input signal level exceeds LMTH1-0 bits. Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level Table 29. ALC Limiter ATT Step Table 30. ALC Zero Crossing Timeout Period

The ALC recovery operation waits for the WTM2-0 bits (Table 31) to be set after completing the ALC limiter operation. to the set reference level (Table 33) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 30). WTM2-0 bits and no zero crossing occurs, the ALC recovery operation is executed in a period set by ZTM1-0 bits. the IVL and IVR values exceed the reference level (REF7-0 bits), the IVL and IVR values are not increased. the waiting timer of ALC recovery operation starts. Table 31. ALC Recovery Operation Waiting Period Table 32. ALC Recovery GAIN Step

Table 33. Reference Level at ALC Recovery Operation Table 34. Fast Recovery Speed Setting (N/A: Not available)

Table 35 and Table 36 show the examples of the ALC setting for mic recording and playback, respectively. Table 35. Example of the ALC setting (Recording Path) Table 36. Example of the ALC setting (Playback Path)

operation is finished by ALC bit = “0”.

• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0, LFST and FR bits Manual Mode * The value of IVOL should be the same or smaller than REF’s WR (IVL7-0) WR (IVR7-0) WR (REF7-0) WR (LMTH1-0, RGAIN1-0, LMAT1-0, ZELMN, LFST) Example: Limiter = Zero crossing Enable Recovery Cycle = 32ms@8kHz Zero Crossing Timeout Period = 32ms@8kHz Limiter and Recovery Step = 1 Fast Recovery = Enable (4 step) Gain of IVOL = +30dB Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” (1) Addr=11H, Data=E1H (2) Addr=12H, Data=E1H (5) Addr=16H, Data=01H (3) Addr=13H, Data=E1H WR (ALC = “1”) WR (ZTM1-0, WTM2-0, RFST1-0, FR) (4) Addr=15H, Data=05H (6) Addr=17H, Data=03H ALC Operation Note : WR : Write

Figure 67. Registers set-up sequence at ALC operation

The input digital volume becomes a manual mode when ALC bit is “0”. This mode is used in the case shown below.

1. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH1-0 bits and etc)
2. When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed.

For example, in case of changing the sampling frequency.

1. When IVOL is used as a manual volume.

values at the end of the ADC initialization cycle after PMADL, PMADR, PMDML or PMMDR bit is changed to “1”. Table 37. Input Digital Volume Setting

44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (Recommend HPF enable). Table 38. HPF1 Cut-off Frequency Table 39. Side Tone Volume A Code Table (N/A: Not available)

[AK4679] MS1402-E-06 2013/02 - 80 - ■ 5-Band Equalizer The AK4679 has 5-Band Equalizer before DAC of Stereo CODEC. The 5-band Equalizer is selected ON/OFF by 5EQ bit. When 5-band Equalizer is OFF, the audio data passes this block by 0dB gain. Each coefficient and transfer function of 5-band Equalizer is as follows. The coefficient must be set when 5EQ bit = “0” or PMEQ bit = “0”. Gain range of 5-band equalizer is set from +12dB to -12dB (0.5dB step) independently by 5EQ1G5-0, 5EQ2G5-0, 5EQ3G5-0, 5EQ4G5-0 or 5EQ5G5-0 bits. The 5-band Equalizer starts operation 4/fs(max) after when 5EQ bit = “1” and PMEQ bit = “1” is set. 1. EQ1: 1st order Low Pass Filter <Low Pass Filter> fs: Sampling frequency fc: Cut-off frequency k: Filter gain Register setting ( Note 78) 5E1A[13:0] bits =A, 5E1B[13:0] bits =B (MSB=5E1A13, 5E1B13; LSB=5E1A0, 5E1B0) A = k x 1 + 1 / tan (πfc/ fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function 1 + z −1 1 + Bz −1 h1L (z) = A The cut-off frequency should be set as below. fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)

[AK4679] MS1402-E-06 2013/02 - 81 - 2. EQ2, EQ3, EQ4: Equalizer 5E2A15-0, 5E2B15-0 and 5E2C15-0 bits set the coefficient of EQ2. 5E3A15-0, 5E3B15-0 and 5E3C15-0 bits set the coefficient of EQ3. 5E4A15-0, 5E4B15-0 and 5E4C15-0 bits set the coefficient of EQ4. fs: Sampling frequency fo2 ~ fo4: Center frequency fb2 ~ fb4: Band width where the gain is 3dB different from center frequency k2 ~ k4: Filter gain Register setting (Note 78) EQ2: 5E2A[15:0] bits =A1, 5E2B[15:0] bits =B1, 5E2C[15:0] bits =C2 EQ3: 5E3A[15:0] bits =A2, 5E3B[15:0] bits =B2, 5E3C[15:0] bits =C3 EQ4: 5E4A[15:0] bits =A3, 5E4B[15:0] bits =B3, 5E4C[15:0] bits =C4 (MSB=5E2A15, 5E2B15, 5E2C15, 5E3A15, 5E3B15, 5E3C15, 5E4A15, 5E4B15, 5E4C15; LSB= 5E2A0, 5E2B0, 5E2C0, 5E3A0, 5E3B0, 5E3C0, 5E4A0, 5E4B0, 5E4C0) An = kn x tan (πfbn/fs) 1 + t an (πfbn/fs) Bn = cos(2π fon/fs) x 1 + tan (πfbn/fs) , C n = 1 − tan (πfbn/fs) 1 + tan (πfbn/fs) (n = 2, 3, 4) Transfer function hn (z) = An 1 − z −2 1− Bnz −1− Cnz −2 (n = 2, 3, 4) The center frequency should be set as below. fon / fs < 0.497

[AK4679] MS1402-E-06 2013/02 - 82 - 3. EQ5: 1st order High Pass Filter <High Pass Filter> fs: Sampling frequency fc: Cut-off frequency k: Filter gain Register setting ( Note 78) 5E5A[13:0] bits =A, 5E5B[13:0] bits =B (MSB=5E5A13, 5E5B13; LSB=5E5A0, 5E5B0) A = k x 1 / t an (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer Function h5H (z) = A 1 − z −1 1 + Bz −1 The cut-off frequency should be set as below. fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz) Note 78. [Translation the filter coefficient calculated by th e equations above from real num ber to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 213 X should be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit. Total Transfer Function: H(z) = K1 x h1L(z) + K2 x h2(z) + K3 x h3(z) + K4 x h4(z) + K5 x h5H(z) K1 ~ 5: EQ Gain (+12 ~ -12dB, 0.5dB step). This value is changed by control register. K1: 5EQ1G5-0 bits (Addr=6AH) K2: 5EQ2G5-0 bits (Addr=6BH) K3: 5EQ3G5-0 bits (Addr=6CH) K4: 5EQ4G5-0 bits (Addr=6DH) K5: 5EQ5G5-0 bits (Addr=6EH) Default Center Frequency (Sampling Frequency = 44.1kHz): EQ1: fc=100Hz E Q 2 : f o 2=250Hz (fb2=50Hz) E Q 3 : f o 3=1kHz (fb3=200Hz) E Q 4 : f o 4=3.5kHz (fb4=700Hz) EQ5: fc=10kHz

Table 40. 5-band Equalizer Gain Setting (Default: 0dB)

Figure 68. DRC Functions and Signal Path DRCM1-0 bits select stereo or mono of DRC input data. In case of mono mode, the same data is input to both channels. Table 41. DRC Stereo/Mono Select (N/A: Not available) The cut-off frequency should be set as below.

The cut-off frequency should be set as below. bit = “1”). This function attenuates output signal level automatically when minute amount of the signal is input. “Noise Suppression Threshold Low Level” set by NSTHL4-0 bits (Table 43) during the normal operation. transition of the attenuation speed set by NSATT2-0 bits (Table 45). Table 42. Moving Average Parameter Setting at Noise Suppression Off

Table 43. Noise Suppression Threshold Low Level Table 44. Reference Value Setting when Noise Suppression is ON Table 45. Noise Suppression ATT Speed Setting (N/A: Not available)

noise suppressing operation. Table 46. Moving Average Parameter Setting at Noise Suppression On Table 47. Noise Suppression Threshold High Level Table 48. Recovery Speed Setting from Noise Suppression to Normal Operation (N/A: Not available)

1. Dynamic Volume Control Block

band (Low, Middle, High) and controls independently. Figure 69. DVLC Functions and Signal Path for Low Frequency Range “01” or “10” and PMDRC bit = “1” are set. Table 49. DLLPF Mode Setting (N/A: Not available) The cut-off frequency should be set as below.

(X3L, Y3L) in dB. The inflection points should be set in such a way that VL1X ≤ VL2X ≤ VL3X, VL1Y ≤ VL2Y ≤ VL3Y. L4G value. The initial value of the DVLC gain is set by the L1G. Figure 70. DVLC Curve for Low Frequency Range Table 50. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available) Table 51. DVLC Point Setting for X/Y3

The results calculated by the equations above should be rounded off to integer. These integers are slope data. Table 52. DVLC Slope Setting for Low Frequency Range

Figure 71. DVLC Functions and Signal Path for Middle Frequency Range DMHPF1-0 bits = “01” or “10” and PMDRC bit = “1” are set. Table 53. DMHPF Mode Setting (N/A: Not available) The cut-off frequency should be set as below.

bits = “01” or “10” and PMDRC bit = “1” are set. Table 54. DMLPF Mode Setting (N/A: Not available) The cut-off frequency should be set as below.

(DMHPF1-0 = DMLPF1-0 bits = “00”), the audio data passes this block by 0dB gain. Figure 72. DVLC Curve for Middle Frequency Range Table 55. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available) Table 56. DVLC Point Setting for X/Y3

The results calculated by the equations above should be rounded off to integer. These integers are slope data. Table 57. DVLC Slope Setting for Middle Frequency Range

Figure 73. DVLC Functions and Signal Path for High Frequency Range “01” or “10” and PMDRC bit = “1” are set. Table 58. DHHPF Mode Setting (N/A: Not available) The cut-off frequency should be set as below.

calculated by the H4G value. The initial value of the DVLC gain is set by the H1G. Figure 74. DVLC Curve for High Frequency Range Table 59. DVLC Point Setting for X/Y1, X/Y2 (N/A: Not available) Table 60. DVLC Point Setting for X/Y3

The results calculated by the equations above should be rounded off to integer. These integers are slope data. Table 61. DVLC Slope Setting for High Frequency Range

is reached the output level of the DVLC curve set by each frequency range. Table 62. DVLC Moving Average Parameter Setting Table 63. DVLC ATT Speed Setting (N/A: Not available) Table 64. DVLC Recovery Speed Setting (N/A: Not available)

1. Dynamic Range Control Block

recovery operation is always ON. The compression level must be set when PMDRC bit = “0”. Figure 75. DRC Gain Curve Table 65. DRC Compression Level Setting Table 66. DRC ATT Speed Setting (N/A: Not available)

Table 67. DRC Recovery Speed Setting

Table 68. Digital Volume A Code Table Table 69. Transition Time Setting of Digital Output Volume A

The AK4679 has a digital output volume control (DATT-B: 128 levels, 0.5dB step, Mute) for recording of received voice. @ fs=44.1kHz, PMMIX bit = “1”) from 00H (+6dB) to 7FH (MUTE). Table 70. Digital Volume B Table Table 71. Transition Time Setting of Digital Output Volume B The AK4679 has a digital output volume control (DATT-C: 128 levels, 0.5dB step, Mute) for recording of received voice. Table 72. Digital Volume C Table Table 73. Transition Time Setting of Digital Output Volume C

SVB2-0 bits. The volume range is from 0dB to -24dB. Table 74. Side Tone Volume B Table (N/A: Not available) bits .The volume rage is from 0 to –24dB. Table 75. SDTIB Volume Table (N/A: Not available)

mono operation, the same data is output to both channel slots. Table 76. ADC Mono/Stereo Select (Analog MIC: DMIC bit = “0”) Table 77. ADC Mono/Stereo Select (Digital MIC: DMIC bit = “1) PFSEL bit select the input data of programmable filter.

0 ADC Output (selected by Table 76) (default)

1 SDTI Input (selected by Table 84)

Table 78. Programmable Filter Input Signal Select When ADM bit is “1”, ALC output data is output to both channels of SDTO and SVOLA as (L+R)/2, respectively.

0 L R (default)

Table 79. ALC Output Mono Mixing PFSDO bit select the input data both SDTO and SVOLA.

0 ADC Output (selected by Table 76)

1 Programmable Filter Output (selected by Table 79) (default)

Table 80. SDTO, SVOLA Input Signal Select

Table 81. SDTO Lch Output Mixing Table 82. SDTO Rch Output Mixing When SDOD bit is “1”, SDTO output data can be disabled (fixed to “L”). Input data of SVOLA is not disabled.

0 Enable (Output) (default)

1 Disable (“L” Output)

Table 83. SDTO Disable SDIM1-0 bits select stereo or mono of SDTI input data. In case of mono mode, the same data is input to both channels. Table 84. SDTI Stereo/Mono Select (N/A: Not available) Table 85. 5-band EQ Lch Input Mixing 1 (N/A: Not available) Table 86. 5-band EQ Rch Input Mixing 1 (N/A: Not available)

/Table 86 and MIX1L/R output data. Table 87. 5-band EQ Lch Input Mixing 2 (N/A: Not available) Table 88. 5-band EQ Rch Input Mixing 2 (N/A: Not available) DASEL1-0 bits select the input data of DAC. Table 89. DAC Input Signal Select (N/A: Not available) MX1L2-0 bits set the data mixing for Audio I/F Lch input. Table 90. Audio I/F Lch Input Mixing (N/A: Not available) MX1R2-0 bits set the data mixing for Audio I/F Rch input. Table 91. Audio I/F Rch Input Mixing (N/A: Not available)

MX2A1-0 bits set the data mixing for MIX2C input. Table 92. MIX2C Input Mixing 1 MX2B1-0 bits set the data mixing for MIX2C input. Table 93. MIX2C Input Mixing 2 MX2C1-0 bits set the data mixing for SRCAO and SVOLB input. Table 94. SRCAO/SVOLB Input Mixing MXSB2-0 bits set the data mixing for SRCBO input. Table 95. SRCBO Input Mixing When SDOAD bit is “1”, SDTOA output data can be disabled (fixed to “L”). Input data of SVOLB is not disabled. Table 96. SDTOA Disable

SBMX1-0 bits set the data mixing from SDTIA input and SVOLB output. The mixed data is input to DATT-C. Table 97. SDTOB Mixing (N/A: Not available) When SDOBD bit is “1”, SDTOB output data can be disabled (fixed to “L”). Table 98. SDTOB Disable

When DACL and DACR bits are “1”, Lch/Rch signal of DAC is output from the LOUT/ROUT pins in single-ended. LOUT/ROUT. When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R) mono signal. Figure 77. Stereo Line Output

0 Power-down Pull-down to VSS1 (default) 0 1 Normal Operation Normal Operation

0 Power-save Fall down to VSS1 1 1 Power-save Rise up to common voltage

Table 99. Stereo Line Output Mode Select (LOUT) Table 100. Stereo Line Output Mode Select (ROUT) Table 101. Stereo Line Output Volume Setting (N/A: Not available)

LIN1/RIN1/LIN2/RIN2/LIN3/RIN3/LIN4/RIN4 is output from the LOP/LON pins in full-differential as (L+R) signal. normal operation. LVL2-0 bits set the volume of mono line output. Figure 80. Full-differential Mono Line Output Table 102. Mono Line Output Gain Setting (N/A: Not available)

0 Power-down Pull-down to VSS1 (default)0 1 Normal Operation Normal Operation

Table 103. Mono Line Output Mode Setting

Figure 81. Mono Line Output Control Sequence (in case of using Pop Noise Reduction Circuit) (1) Set LOPS bit = “1”. Mono line output enters power-save mode. (2) Set PMLO = PMRO bits = “1”. Mono line output exits power-down mode. (3) Set LOPS3 bit = “0” after LOP and LON pins rise up. Mono line output exits power-save mode. Mono line output is enabled. (4) Set LOPS bit = “1”. Mono line output enters power-save mode. (5) Set PMLO = PMRO bits = “0”. Mono line output enters power-down mode. LOP and LON pins fall down to VSS1. Fall time is 200ms (max 300ms) at C=1μF and AVDD=1.8V. (6) Set LOPS bit = “0” after LOP and LON pins fall down. Mono line output exits power-save mode.

receiver output enters in normal operation. RCVG3-0 bits control the volume of mono receiver output. Figure 82. Mono Receiver Output Table 104. Mono Receiver Output Volume Setting

1 Power-save Hi-Z Common Voltage

0 Normal Operation Normal Operation Normal Operation

Table 105. Receiver-Amp Mode Setting (x: Don’t care)

Figure 83. Power-up/Power-down Timing for Receiver-Amp

switched between VDD mode and 1/2VDD mode by the output level of the headphone amplifiers. HPG = -4dB) and 25mW (@ 0dBFS, RL =32Ω, AVDD=1.8V, HPG=0dB). LOHM bit = “1”, the headphone-amp output to HPL and HPR pins as (L+R) mono signal. Figure 84. Stereo Headphone Output Table 106. Headphone-Amp Volume Setting (Default: 0dB, N/A: Not available)

Table 107. Headphone-Amp Volume Zero Crossing Timeout Period Table 108. Charge Pump Mode Setting (N/A: Not available) Table 109. VDD Mode Waiting Period (N/A: Not available)

possibility that Headphone-Amp oscillates. Figure 85. HP-Amp oscillation prevention circuit example pulled-down resistor is 120Ω (typ). Table 110. Headphone-Amp Mode Setting (x: Don’t’ care)

DAC. SPKG3-0 bits control the volume of SPP/SPN. Figure 86. Mono Speaker Output Table 111. Speaker Output Volume Setting

0 Power-down & Hi-Z (default)

1 Power-up & Output

Table 112. Speaker-Amp output state SPK-Amp block should be powered-up again with an interval of 0.5ms or more.

[AK4679] MS1402-E-06 2013/02 - 120 - ■ Thermal Shutdown Function When PMVCM bit is “1” and the internal device temperature rises up irregularly (E.g. Output pins of speaker amplifier are shortened.), all amplifier blocks are automatically powered-down (PMLO, PMRO, PMRCV, PMHPL, PMHPR and PMSPK bits = “0”) and then THDET bit becomes “1”. The other control registers are not initialized. When the internal device temperature falls down, THDET bit becomes “0”, but the amplifier blocks do not return to normal operation unless the amplifier blocks are powered-up (PMLO, PMRO, PMRCV, PMHPL, PMHPR or PMSPK bits = “1”). The device status can be monitored by THDET bit.

PMPCMA bit is “1”, PCM I/F A port is powered-up. When PMPCMB bit is “1”, PCM I/F B port is powered-up. Figure 87. PCM I/F A and B and SDTOB output data as shown in Table 113. Ratio of Input / Output is decided by PMMIX bit. Table 113. SDTOA and SDTOB pins Output Data (PMSRx: PMSRAI, PMSRAO, PMSRBI, PMSRBO) Table 114. PCM I/F Input Output rate

μ-Law) independently (Table 115 and Table 116). Table 115. PCM I/F A Mode (N/A: Not available) Table 116. PCM I/F B Mode (N/A: Not available) Table 117. PCM I/F A Format Table 118. PCM I/F B Format SDTIA is latched on the rising edge (“↑”). MSBSA bit can shift the MSB position of SDTOA and SDTIA by half period of BICKA. SDTIB is latched on the rising edge (“↑”). MSBSB bit can shift the MSB position of SDTOB and SDTIB by half period of BICKB.

Figure 104. Timing of MSB justified (PCM I/F A)

14 Don't Care

Figure 105. Timing of MSB justified (PCM I/F B)

Figure 106. Timing of I2S (PCM I/F A)

15 Don't Care

Figure 107. Timing of I2S (PCM I/F B)

sampling rate), fs2 is output at the same timing of fs1 input. Table 123. Setting of Sampling Frequency (N/A: Not available) JX0 and JX1 pins function respectively. Figure 108. Port#1/2/3 Signal Setting (PT2N bit = “0”)

Figure 109. Output Selector of Port#1, Port#2 and Port#3 (Red: hardware reset)

and supporting 2channel data only. The data length supports 16/24bit Linear, 8bit μ-Law, and 8bit A-Law ( Table 125). 16bit Linear. The AK4679 can support 16bit PCM (short frame, long frame), Left justified and I2S mode (Table 126). When the data format of Port#1 and Port#2 is 8bit A-Law or 8bitμ-Law, the data format of Port#3 will be 16bit Linear. BCLK1 and BCLK3 input frequency to the Port#1, 3 are dependent on DIFD mode as shown below. Table 124. BCLK Setting Table 125. PCM Data Format Setting Table 126. PCM Interface Format Setting edge select is valid on any digital interface format. Set BCKP1 bit = “0” (falling edge) for Left justified and I2S formats. Refer to: Figure 110-Figure 113 for selectable format of BCLK against SYNC1/2 edge.

0 Falling (FE) Figure 110

1 Rising (RE) Figure 111

Table 127. PCM Interface format in (DIFD[1:0] = “00”, “01”)

state by bringing the PDNE pin = “H”. Figure 109. The frame sync SYNC1 goes through SYNC2, and BCLK1 through BCLK2. The dital set to “1”. Control registers are reset and the DSP block goes into sleep state. 3, SYNC1 or 3) are not necessary when writing to PRAM or CRAM. After releasing DSP reset, DRAM and DLRAM data are cleared by “0” and the DSP block enters wait sync state. power up since an external clock cannot be received. becomes RUN state and CGU block starts to control clocks and DSP core. either Wait Sync state or Hardware Reset. in powere-down state until the clock is input again.

Table 128. Modes Definitions

Figure 118. DSP Block State Diagram

• Power-up, register setting, program download and RUN state sequence The DSP must be in sleep state when downloading the program. Set DLRDY bit to “1” to power-up the internal oscillation circuit, and after 100μs downloading becomes available. DLRDY bit must always be cleared when complete a download. Then DSPTRSTN bit is cleared, the DSP block enters wait sync mode. In this state, CGU block is locked when serial data clock input is detected and the DSP block becomes operating state. Power supply PDNE(pin) 0.6μs (min) 1μs (min) Glock Gen(int.) μP I/F DLRDY bit Device state BCLKx,SYNCx pin Input Device Operational State Wait Sync Power Down PWSW bit Setting Register Download DSP program DSPRSTN bit Sleep State Power OFF Hardware Reset→Suspend (x= 1 or 3) 100 μs(min) 100 μs(min) MRSTN bit Don’t care

Figure 119. DSP Block Status

RAM and accelerator are cleared by “0” (RAM clear). The required time to clear RAM is about 400µs. Figure 122. RAM Clear Sequence result output is enabled by DSP instruction setting. Table 129. STO pin Configuration

controlled by DSP programs. SELDO3 and SELDO4 bits control SDOUT3/GP0 and SDOUT4/GP1 pins respectively. initial state of the GP0 and GP1 pins are “L”.

0 DSP DOUT3 (default) 0 1 DSP GP output 0

Table 130. SDOUT3/GP0 pin Select

0 DSP DOUT4 (default) 0 1 DSP GP output 1

Table 131. SDOUT4/GP1 pin Select

Figure 134. Bit Transfer on the I2C-Bus

Figure 137. Echo-Back Mode Reading

[AK4679] MS1402-E-06 2013/02 - 154 - ■ Register Map (Audio block) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 0 PMADR PMADL 0 0 PMPFIL PMVCM 01H Power Management 1 0 0 0 0 PMDAR PMDAL PMDRC PMEQ 02H Power Management 2 ADRST 0 0 0 MICL2 PMMP2 MICL1 PMMP1 03H PLL Mode Select 0 FS3 FS2 FS1 FS0 PLL3 PLL2 PLL1 PLL0 04H PLL Mode Select 1 CM1 CM0 BCKO 0 0 0 M/S PMPLL 05H Audio I/F Format Select 0 0 0 SDOD MSBS BCKP DIF1 DIF0 06H MIC Signal Select 0 MDIF3 MDIF2 MDIF1 INR1 INR0 INL1 INL0 07H MIC Amp Gain MGNR3 MGNR 2 MGNR1 MGNR0 MGNL3 MGNL2 MGNL1 MGNL0 08H Digital MIC 0 0 PMDMR PMDML DCLKE 0 DCLKP DMIC 09H DAC Signal Pass Select DAC SR DACSL DACRR DACRL 0 0 DACR DACL 0AH LINEOUT Power Management 0 0 0 LODIF LOM LOPS PMRO PMLO 0BH HP Power Management HPTM 1 HPTM0 0 0 LOMH 0 PMHPR PMHPL 0CH Charge Pump Control 0 VDDTM2 VDDTM1 VDDTM0 0 0 CPMODE1 CPMODE0 0DH SPK&RCV Power Management THDET 0 TEST PMSPK 0 0 RCVPS PMRCV 0EH LINEOUT Volume Control 0 0 0 0 0 LVL2 LVL1 LVL0 0FH HP Volume Control 0 0 HPG5 HPG4 HPG3 HPG2 HPG1 HPG0 10H SPK & RCV Volume Control RCVG3 RCVG2 RCVG1 RCVG0 SPKG3 SPKG2 SPKG1 SPKG0 11H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 12H Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 13H ALC Reference Select REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 14H Digital Mixing Control SRMXR1 SRMXR0 SRMXL1 SRMXL0 PFMXR1 PFMXR0 PFMXL1 PFMXL0 15H ALC Timer Select FR RFST1 RFST0 WTM2 WTM1 WTM0 ZTM1 ZTM0 16H ALC Mode Control LFST ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH1 LMTH0 17H Mode Control 0 0 0 SDIM1 SDIM0 5EQ ADM IVOLC ALC 18H Mode Control 1 0 OVTMB BIV2 BIV1 BIV0 SMUTE OVTM OVOLC 19H Digital Filter Select 0 0 HPFC1 HPFC0 HPFAD DASEL1 DASEL0 PFSDO PFSEL 1AH Digital Filter Select 1 GN1 GN0 LPF HPF EQ0 FIL3 0 0 1BH Digital Filter Select 2 0 0 0 EQ5 EQ4 EQ3 EQ2 EQ1 1CH Side Tone Volume A Control 0 SVAR2 SVAR1 SVAR0 0 SVAL2 SVAL1 SVAL0 1DH Lch Output Volume Control 0 OVL6 OVL5 OVL4 OVL 3 OVL2 OVL1 OVL0 1EH Rch Output Volume Control 0 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 1FH PCM I/F Power Management PMMIX PMSRBO PMSRBI PMPCMB PMOSC PMSRAO PMSRAI PMPCMA 20H PCM I/F Control 0 SDOAD 0 MSBSA BCKPA LAWA1 LAWA0 FMTA1 FMTA0 21H PCM I/F Control 1 SDOBD 0 MSBSB BCKPB LAWB1 LAWB0 FMTB1 FMTB0 22H Side Tone Volume B Control 0 0 0 0 0 SVB2 SVB1 SVB0 23H Digital Volume B Control 0 BVL6 BVL5 BVL4 BVL3 BVL2 BVL1 BVL0 24H Digital Volume C Control 0 CVL6 CVL5 CVL4 CVL3 CVL2 CVL1 CVL0 25H Digital Mixing Control 0 0 0 MX1R2 MX1R1 MX1R0 MX1L2 MX1L1 MX1L0 26H Digital Mixing Control 1 0 0 MX2C1 MX2C0 MX2B1 MX2B0 MX2A1 MX2A0 27H Digital Mixing Control 2 0 0 0 0 0 MXSB2 MXSB1 MXSB0 28H Digital Mixing Control 3 SDOR1 SDOR0 SDOL1 SDOL0 0 0 SBMX1 SBMX0 29H FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 2AH FIL1 Co-efficient 1 0 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 2BH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 2CH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 2DH FIL2 Co-efficient 0 F2A7 F2A6 F2A5 F2A4 F2A3 F2A2 F2A1 F2A0 2EH FIL2 Co-efficient 1 0 0 F2A13 F2A12 F2A11 F2A10 F2A9 F2A8 2FH FIL2 Co-efficient 2 F2B7 F2B6 F2B5 F2B4 F2B3 F2B2 F2B1 F2B0 30H FIL2 Co-efficient 3 0 0 F2B13 F2B12 F2B11 F2B10 F2B9 F2B8 31H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 32H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 33H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 34H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 35H EQ Co-efficient 0 E0A7 E0A6 E0A5 E0A4 E0A3 E0A2 E0A1 E0A0 36H EQ Co-efficient 1 E0A15 E0A14 E0 A13 E0A12 E0A11 E0A10 E0A9 E0A8 37H EQ Co-efficient 2 E0B7 E0B6 E0B5 E0B4 E0B3 E0B2 E0B1 E0B0 38H EQ Co-efficient 3 0 0 E0B13 E0B12 E0B11 E0B10 E0B9 E0B8 39H EQ Co-efficient 4 E0C7 E0C6 E0C5 E0C4 E0C3 E0C2 E0C1 E0C0 3AH EQ Co-efficient 5 E0C15 E0C14 E0C13 E0C12 E0C11 E0C10 E0C9 E0C8

[AK4679] MS1402-E-06 2013/02 - 155 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 3BH E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 3CH E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 3DH E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 3EH E1 Co-efficient 3 E1B15 E1B14 E1B13 E1B12 E1B11 E1B10 E1B9 E1B8 3FH E1 Co-efficient 4 E1C7 E1C6 E1C5 E1C4 E1C3 E1C2 E1C1 E1C0 40H E1 Co-efficient 5 E1C15 E1C14 E1C13 E1C12 E1C11 E1C10 E1C9 E1C8 41H E2 Co-efficient 0 E2A7 E2A6 E2A5 E2A4 E2A3 E2A2 E2A1 E2A0 42H E2 Co-efficient 1 E2A15 E2A14 E2 A13 E2A12 E2A11 E2A10 E2A9 E2A8 43H E2 Co-efficient 2 E2B7 E2B6 E2B5 E2B4 E2B3 E2B2 E2B1 E2B0 44H E2 Co-efficient 3 E2B15 E2B14 E2B13 E2B12 E2B11 E2B10 E2B9 E2B8 45H E2 Co-efficient 4 E2C7 E2C6 E2C5 E2C4 E2C3 E2C2 E2C1 E2C0 46H E2 Co-efficient 5 E2C15 E2C14 E2C13 E2C12 E2C11 E2C10 E2C9 E2C8 47H E3 Co-efficient 0 E3A7 E3A6 E3A5 E3A4 E3A3 E3A2 E3A1 E3A0 48H E3 Co-efficient 1 E3A15 E3A14 E3 A13 E3A12 E3A11 E3A10 E3A9 E3A8 49H E3 Co-efficient 2 E3B7 E3B6 E3B5 E3B4 E3B3 E3B2 E3B1 E3B0 4AH E3 Co-efficient 3 E3B15 E3B14 E3B13 E3B12 E3B11 E3B10 E3B9 E3B8 4BH E3 Co-efficient 4 E3C7 E3C6 E3C5 E3C4 E3C3 E3C2 E3C1 E3C0 4CH E3 Co-efficient 5 E3C15 E3C14 E3C13 E3C12 E3C11 E3C10 E3C9 E3C8 4DH Reserved 0 0 0 0 0 0 0 0 4EH Reserved 0 0 0 0 0 0 0 0 4FH Reserved 0 0 0 0 0 0 0 0 50H 5band E1 Co-efficient 0 5E1A7 5E1A6 5E1A5 5E1A4 5E1A3 5E1A2 5E1A1 5E1A0 51H 5band E1 Co-efficient 1 0 0 5E1A 13 5E1A12 5E1A11 5E1A10 5E1A9 5E1A8 52H 5band E1 Co-efficient 2 5E1B7 5E1B6 5E1B5 5E1B4 5E1B3 5E1B2 5E1B1 5E1B0 53H 5band E1 Co-efficient 3 0 0 5E1B13 5E1B12 5E1B11 5E1B10 5E1B9 5E1B8 54H 5band E2 Co-efficient 0 5E2A7 5E2A6 5E2A5 5E2A4 5E2A3 5E2A2 5E2A1 5E2A0 55H 5band E2 Co-efficient 1 5E2A15 5E2A14 5E2A13 5E2A12 5E2A11 5E2A10 5E2A9 5E2A8 56H 5band E2 Co-efficient 2 5E2B7 5E2B6 5E2B5 5E2B4 5E2B3 5E2B2 5E2B1 5E2B0 57H 5band E2 Co-efficient 3 5E2B15 5E2B14 5E2B13 5E2B12 5E2B11 5E2B10 5E2B9 5E2B8 58H 5band E2 Co-efficient 4 5E2C7 5E2C6 5E2C5 5E2C4 5E2C3 5E2C2 5E2C1 5E2C0 59H 5band E2 Co-efficient 5 5E2C15 5E2C14 5E2C13 5E2C12 5E2C11 5E2C10 5E2C9 5E2C8 5AH 5band E3 Co-efficient 0 5E3A7 5E3A6 5E3A5 5E3A4 5E3A3 5E3A2 5E3A1 5E3A0 5BH 5band E3 Co-efficient 1 5E3A15 5E3A14 5E3A13 5E3A12 5E3A11 5E3A10 5E3A9 5E3A8 5CH 5band E3 Co-efficient 2 5E3B7 5E3B6 5E3B5 5E3B4 5E3B3 5E3B2 5E3B1 5E3B0 5DH 5band E3 Co-efficient 3 5E3B15 5E3B14 5E3B13 5E3B12 5E3B11 5E3B10 5E3B9 5E3B8 5EH 5band E3 Co-efficient 4 5E3C7 5E3C6 5E3C5 5E3C4 5E3C3 5E3C2 5E3C1 5E3C0 5FH 5band E3 Co-efficient 5 5E3C15 5E3C14 5E3C13 5E3C12 5E3C11 5E3C10 5E3C9 5E3C8 60H 5band E4 Co-efficient 0 5E4A7 5E4A6 5E4A5 5E4A4 5E4A3 5E4A2 5E4A1 5E4A0 61H 5band E4 Co-efficient 1 5E4A15 5E4A14 5E4A13 5E4A12 5E4A11 5E4A10 5E4A9 5E4A8 62H 5band E4 Co-efficient 2 5E4B7 5E4B6 5E4B5 5E4B4 5E4B3 5E4B2 5E4B1 5E4B0 63H 5band E4 Co-efficient 3 5E4B15 5E4B14 5E4B13 5E4B12 5E4B11 5E4B10 5E4B9 5E4B8 64H 5band E4 Co-efficient 4 5E4C7 5E4C6 5E4C5 5E4C4 5E4C3 5E4C2 5E4C1 5E4C0 65H 5band E4 Co-efficient 5 5E4C15 5E4C14 5E4C13 5E4C12 5E4C11 5E4C10 5E4C9 5E4C8 66H 5band E5 Co-efficient 0 5E5A7 5E5A6 5E5A5 5E5A4 5E5A3 5E5A2 5E5A1 5E5A0 67H 5band E5 Co-efficient 1 0 0 5E5A 13 5E5A12 5E5A11 5E5A10 5E5A9 5E5A8 68H 5band E5 Co-efficient 2 5E5B7 5E5B6 5E5B5 5E5B4 5E5B3 5E5B2 5E5B1 5E5B0 69H 5band E5 Co-efficient 3 0 0 5E5B13 5E5B12 5E5B11 5E5B10 5E5B9 5E5B8 6AH 5band EQ1 Gain 0 0 EQ1G5 EQ1G4 EQ1G3 EQ1G2 EQ1G1 EQ1G0 6BH 5band EQ2 Gain 0 0 EQ2G5 EQ2G4 EQ2G3 EQ2G2 EQ2G1 EQ2G0 6CH 5band EQ3 Gain 0 0 EQ3G5 EQ3G4 EQ3G3 EQ3G2 EQ3G1 EQ3G0 6DH 5band EQ4 Gain 0 0 EQ4G5 EQ4G4 EQ4G3 EQ4G2 EQ4G1 EQ4G0 6EH 5band EQ5 Gain 0 0 EQ5G5 EQ5G4 EQ5G3 EQ5G2 EQ5G1 EQ5G0 6FH Reserved 0 0 0 0 0 0 0 0

[AK4679] MS1402-E-06 2013/02 - 156 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 70H DRC Mode Control 0 DLMAT2 DLMAT1 DLMAT0 DRGAIN1 DRGAIN0 DRCC1 DRCC0 71H NS Control 0 0 DRCM1 DRCM0 0 NSLPF NSHPF NSCE 72H NS Gain & ATT Control 0 NSGAIN2 NSGAIN1 NSGAIN0 0 NSATT2 NSATT1 NSATT0 73H NS On Level NSIAF1 NSIAF0 0 NSTHL4 NSTHL3 NSTHL2 NSTHL1 NSTHL0 74H NS Off Level NSOAF1 NSOAF0 0 NSTHH

4 NSTHH3 NSTHH

75H NS Reference Select 0 0 0 0 NSREF3 NSREF2 NSREF1 NSREF0 76H NS LPF Co-efficient 0 NSLA7 NS LA6 NSLA5 NSLA4 NSLA3 NSLA2 NSLA1 NSLA0 77H NS LPF Co-efficient 1 0 0 NS LA13 NSLA12 NSLA11 NSLA10 NSLA9 NSLA8 78H NS LPF Co-efficient 2 NSLB7 NSLB6 NSLB5 NSLB4 NSLB3 NSLB2 NSLB1 NSLB0 79H NS LPF Co-efficient 3 0 0 NSLB13 NSLB12 NSLB11 NSLB10 NSLB9 NSLB8 7AH NS HPF Co-efficient 0 NSHA7 NSHA6 NSHA5 NSHA4 NSHA3 NSHA2 NSHA1 NSHA0 7BH NS HPF Co-efficient 1 0 0 NSHA13 NSHA12 NSHA11 NSHA10 NSHA9 NSHA8 7CH NS HPF Co-efficient 2 NSHB7 NSHB6 NSHB5 NSHB4 NSHB3 NSHB2 NSHB1 NSHB0 7DH NS HPF Co-efficient 3 0 0 NSHB13 NSHB12 NSHB11 NSHB10 NSHB9 NSHB8 7EH Reserved 0 0 0 0 0 0 0 0 7FH Reserved 0 0 0 0 0 0 0 0 80H DVLC Filter Select DLLPF1 DLLPF0 DMHPF1 DMHPF0 DMLPF1 DMLPF0 DHHPF1 DHHPF0 81H DVLC Mode Control DVRGAIN2 DVRGAIN1 DVRGAIN 0 DVLMAT2 DVLMAT1 DVLMAT0 DAF1 DAF0 82H DVLCL Curve X1 0 0 VL1X5 VL1X4 VL1X3 VL1X2 VL1X1 VL1X0 83H DVLCL Curve Y1 0 0 VL1Y5 VL1Y4 VL1Y3 VL1Y2 VL1Y1 VL1Y0 84H DVLCL Curve X2 0 0 VL2X5 VL2X4 VL2X3 VL2X2 VL2X1 VL2X0 85H DVLCL Curve Y2 0 0 VL2Y5 VL2Y4 VL2Y3 VL2Y2 VL2Y1 VL2Y0 86H DVLCL Curve X3 0 0 0 VL3X4 VL3X3 VL3X2 VL3X1 VL3X0 87H DVLCL Curve Y3 0 0 0 VL3Y4 VL3Y3 VL3Y2 VL3Y1 VL3Y0 88H DVLCL Slope 1 0 L1G6 L1G5 L1G4 L1G3 L1G2 L1G1 L1G0 89H DVLCL Slope 2 0 L2G6 L2G5 L2G4 L2G3 L2G2 L2G1 L2G0 8AH DVLCL Slope 3 0 L3G6 L3G5 L3G4 L3G3 L3G2 L3G1 L3G0 8BH DVLCL Slope 4 0 L4G6 L4G5 L4G4 L4G3 L4G2 L4G1 L4G0 8CH DVLCM Curve X1 0 0 VM1X5 VM1X4 VM1X3 VM1X2 VM1X1 VM1X0 8DH DVLCM Curve Y1 0 0 VM1Y5 VM1Y4 VM1Y3 VM1Y2 VM1Y1 VM1Y0 8EH DVLCM Curve X2 0 0 VM2X5 VM2X4 VM2X3 VM2X2 VM2X1 VM2X0 8FH DVLCM Curve Y2 0 0 VM2Y5 VM2Y4 VM2Y3 VM2Y2 VM2Y1 VM2Y0 90H DVLCM Curve X3 0 0 0 VM3X4 VM3X3 VM3X2 VM3X1 VM3X0 91H DVLCM Curve Y3 0 0 0 VM3Y4 VM3Y3 VM3Y2 VM3Y1 VM3Y0 92H DVLCM Slope 1 0 M1G6 M1G5 M1G4 M1G3 M1G2 M1G1 M1G0 93H DVLCM Slope 2 0 M2G6 M2G5 M2G4 M2G3 M2G2 M2G1 M2G0 94H DVLCM Slope 3 0 M3G6 M3G5 M3G4 M3G3 M3G2 M3G1 M3G0 95H DVLCM Slope 4 0 M4G6 M4G5 M4G4 M4G3 M4G2 M4G1 M4G0 96H DVLCH Curve X1 0 0 VH1X5 VH1X4 VH1X3 VH1X2 VH1X1 VH1X0 97H DVLCH Curve Y1 0 0 VH1Y5 VH1Y4 VH1Y3 VH1Y2 VH1Y1 VH1Y0 98H DVLCH Curve X2 0 0 VH2X5 VH2X4 VH2X3 VH2X2 VH2X1 VH2X0 99H DVLCH Curve Y2 0 0 VH2Y5 VH2Y4 VH2Y3 VH2Y2 VH2Y1 VH2Y0 9AH DVLCH Curve X3 0 0 0 VH3X4 VH3X3 VH3X2 VH3X1 VH3X0 9BH DVLCH Curve Y3 0 0 0 VH3Y4 VH3Y3 VH3Y2 VH3Y1 VH3Y0 9CH DVLCH Slope 1 0 H1G6 H1G5 H1G4 H1G3 H1G2 H1G1 H1G0 9DH DVLCH Slope 2 0 H2G6 H2G5 H2G4 H2G3 H2G2 H2G1 H2G0 9EH DVLCH Slope 3 0 H3G6 H3G5 H3G4 H3G3 H3G2 H3G1 H3G0 9FH DVLCH Slope 4 0 H4G6 H4G5 H4G4 H4G3 H4G2 H4G1 H4G0

[AK4679] MS1402-E-06 2013/02 - 157 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 A0H DVLCL LPF Co-efficient 0 DLLA7 DLLA6 DLLA5 DLLA4 DLLA3 DLLA2 DLLA1 DLLA0 A1H DVLCL LPF Co-efficient 1 0 0 DLLA13 DLLA12 DLLA11 DLLA10 DLLA9 DLLA8 A2H DVLCL LPF Co-efficient 2 DLLB7 DLLB6 DLLB5 DLLB4 DLLB3 DLLB2 DLLB1 DLLB0 A3H DVLCL LPF Co-efficient 3 0 0 DLLB13 DLLB12 DLLB11 DLLB10 DLLB9 DLLB8 A4H DVLCM HPF Co-efficient 0 DMHA7 DMHA6 DMHA5 DMHA4 DMHA3 DMHA2 DMHA1 DMHA0 A5H DVLCM HPF Co-efficient 1 0 0 DMHA13 DMHA12 DMHA11 DMHA10 DMHA9 DMHA8 A6H DVLCM HPF Co-efficient 2 DMHB7 DMHB6 DMHB5 DMHB4 DMHB3 DMHB2 DMHB1 DMHB0 A7H DVLCM HPF Co-efficient 3 0 0 DMHB13 DMHB12 DMHB11 DMHB10 DMHB9 DMHB8 A8H DVLCM LPF Co-efficient 0 DMLA7 DMLA6 DMLA5 DMLA4 DMLA3 DMLA2 DMLA1 DMLA0 A9H DVLCM LPF Co-efficient 1 0 0 DMLA13 DMLA12 DMLA11 DMLA10 DMLA9 DMLA8 AAH DVLCM LPF Co-efficient 2 DMLB7 DMLB6 DMLB5 DMLB4 DMLB3 DMLB2 DMLB1 DMLB0 ABH DVLCM LPF Co-efficient 3 0 0 DMLB13 DMLB12 DMLB11 DMLB10 DMLB9 DMLB8 ACH DVLCH HPF Co-efficient 0 DHHA7 DHHA6 DHHA5 DHHA4 DHHA3 DHHA2 DHHA1 DHHA0 ADH DVLCH HPF Co-efficient 1 0 0 DHHA13 DHHA12 DHHA11 DHHA10 DHHA9 DHHA8 AEH DVLCH HPF Co-efficient 2 DHHB7 DHHB6 DHHB5 DHHB4 DHHB3 DHHB2 DHHB1 DHHB0 AFH DVLCH HPF Co-efficient 3 0 0 DHHB13 DHHB12 DHHB11 DHHB10 DHHB9 DHHB8 Note 80. PDNA pin = “L” resets the registers to their default values. Note 81. The bits defined as 0 must contain a “0” value. Note 82. For Addresses B0H to FFH, data must not be written.

[AK4679] MS1402-E-06 2013/02 - 158 - ■ Register Definition Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 0 PMADR PMADL 0 0 PMPFIL PMVCM R/W R R R/W R/W R R R/W R/W Default 0 0 0 0 0 0 0 0 PMVCM: VCOM Power Management 0: Power down (default) 1: Power up When any blocks are powered-up, th e PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only when all power management bits are “0”. PMPFIL: Programmable Filter Block Power Management 0: Power down (default) 1: Power up PMADL: MIC-Amp Lch & ADC Lch Power Management 0: Power down (default) 1: Power up When the PMADL(PMDML) or PMADR(PMDMR) bit is changed from “0” to “1”, the digital initialization cycle (1059/fs=24ms @ 44.1kHz, ADRST bit = “0”) starts . After initializing, digital data of the ADC is output. PMADR: MIC-Amp Rch & ADC Rch Power Management 0: Power down (default) 1: Power up Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDNA pin is “L”, Audio blocks are powered-down regardless of setting of this address. In this case, CODEC register is initialized to the default value. When all power management bits are “0”, Audio blocks are powered-down. The register values remain unchanged. Power supply current is 50μA(typ) in this case. For fully shut down (typ. 1μA), PDNA pin should be “L”.

[AK4679] MS1402-E-06 2013/02 - 159 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 1 0 0 0 0 PMDAR PMDAL PMDRC PMEQ R/W R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMEQ: 5-band Parametric Equalizer Block Power Management 0: Power down (default) 1: Power up PMDRC: Dynamic Range Control Block Power Management 0: Power down (default) 1: Power up PMDAL: DAC Lch Power Management 0: Power down (default) 1: Power up PMDAR: DAC Rch Power Management 0: Power down (default) 1: Power up Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDNA pin is “L”, all blocks are powered-down regardless of setting of this address. In this case, register is initialized to the default value. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Power Management 1 ADRST 0 0 0 MICL2 PMMP2 MICL1 PMMP1 R/W R/W R R R R/ W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMMP1: MPWR1 pin Power Management 0: Power down: Hi-Z (default) 1: Power up MICL1: MIC Power (MPWR1 pin) Output Level select Default “0”, typ. 2.5V (Table 22) PMMP2: MPWR2 pin Power Management 0: Power down: Hi-Z (default) 1: Power up MICL2: MIC Power (MPWR2 pin) Output Level Select Default “0”, typ. 2.5V (Table 22) ADRST: ADC Initialization Cycle Setting 0: 1059/fs (default) 1: 267/fs

[AK4679] MS1402-E-06 2013/02 - 160 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H PLL Mode Select 0 FS3 FS2 FS1 FS0 PLL3 PLL2 PLL1 PLL0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 1 0 1 1 0 PLL3-0: PLL Reference Clock Select ( Table 5) Default: “0110” (MCKI pin, 12MHz) FS3-0: Sampling Frequency Select ( Table 6, Table 11 and Table 14) Default: “1111” (fs=44.1kHz) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H PLL Mode Select 1 CM1 CM0 BCKO 0 0 0 M/S PMPLL R/W R/W R/W R/W R R R R/W R/W Default 0 0 0 0 0 0 0 0 PMPLL: PLL Power Management 0: EXT Mode and Power Down (default) 1: PLL Mode and Power up M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode BCKO: BICK Output Frequency Select at Master Mode ( Table 9) CM1-0: MCKI Frequency Select at EXT Mode ( Table 10 and Table 13) Default: “00” (256fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Audio I/F Format Select 0 0 0 SDOD MSBS BCKP DIF1 DIF0 R/W R R R R/W R/ W R/W R/W R/W Default 0 0 0 0 0 0 1 0 DIF1-0: Audio Interface Format ( Table 18) Default: “10” (24bit Left justified) BCKP: BICK Polarity at DSP Mode ( Table 19) “0”: SDTO is output by the rising edge (“↑”) of BICK and SDTI is latched by the falling edge (“↓”). (default) “1”: SDTO is output by the falling edge (“↓”) of BICK and SDTI is latched by the rising edge (“↑”). MSBS: LRCK Phase at DSP Mode ( Table 19) “0”: The rising edge (“↑”) of LRCK is half clock of BICK before the channel change. (default) “1”: The rising edge (“↑”) of LRCK is one clock of BICK before the channel change. SDOD: SDTO Disable ( Table 83) “0”: Enable (default) “1”: Disable (“L”)

[AK4679] MS1402-E-06 2013/02 - 161 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H MIC Signal Select 0 MDIF3 MDIF2 MDIF1 INR1 INR0 INL1 INL0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 INL1-0: MIC-Amp Lch Input Source Select ( Table 20) Default: “00” (LIN1) INR1-0: MIC-Amp Rch Input Source Select ( Table 20) Default: “00” (RIN1) MDIF1: Line1 Input Type Select 0: Single-ended input (LIN1/RIN1 pins: default) 1: Full-differential input (IN1+/IN1 − pins) MDIF2: Line2 Input Type Select 0: Single-ended input (LIN2/RIN2 pins: default) 1: Full-differential input (IN2 −/IN2+ pins) MDIF3: Line3 Input Type Select 0: Single-ended input (LIN3/RIN3 pins: default) 1: Full-differential input (IN3+/IN3 − pins) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H MIC Amp Gain MGNR3 MGNR2 M GNR1 MGNR0 MGNL3 MGNL2 MGNL1 MGNL0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 1 0 1 0 1 0 1 MGNL3-0: MIC-Amp Lch Gain Control ( Table 21) Default: “0101” (0dB) MGNR3-0: MIC-Amp Rch Gain Control ( Table 21) Default: “0101” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Digital MIC 0 0 PMDMR PMDML DCLKE 0 DCLKP DMIC R/W R R R/W R/W R/W R R/W R/W Default 0 0 0 0 0 0 0 0 DMIC: Digital Microphone Connection Select 0: Analog Microphone (default) 1: Digital Microphone DCLKP: Data Latching Edge Select 0: Lch data is latched on the DMCLK rising edge (“ ↑”). (default) 1: Lch data is latched on the DMCLK falling edge (“ ↓”). DCLKE: DMCLK pin Output Clock Control 0: “L” Output (default) 1: 64fs Output PMDML/R: Input Signal Select with Digital Microphone ( Table 77) Default: “0” When DMIC bit is “1”, these registers are enabled. ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input (DMIC bit = “1”).

[AK4679] MS1402-E-06 2013/02 - 162 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H DAC Signal Pass Select DACSR DACSL DACRR DACRL 0 0 DACR DACL R/W R/W R/W R/W R/W R R R/W R/W Default 0 0 0 0 0 0 0 0 DACL: Switch Control from DAC Lch to LOUT 0: OFF (default) 1: ON DACR: Switch Control from DAC Rch to ROUT 0: OFF (default) 1: ON DACRL: Switch Control from DAC Lch to RCV-Amp 0: OFF (default) 1: ON DACRR: Switch Control from DAC Rch to RCV-Amp 0: OFF (default) 1: ON DACSL: Switch Control from DAC Lch to SPK-Amp 0: OFF (default) 1: ON DACSR: Switch Control from DAC Rch to SPK-Amp 0: OFF (default) 1: ON

[AK4679] MS1402-E-06 2013/02 - 163 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH LINEOUT Power Management 0 0 0 LODIF LOM LOPS PMRO PMLO R/W R R R R/W R/ W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMLO: LOUT Power Management 0: Power down (default) 1: Power up PMRO: ROUT Power Management 0: Power down (default) 1: Power up LOPS: LOUT/ROUT Power Management 0: Normal Operation (default) 1: Power Save Mode LOM: Mono Mixing from DAC to LOUT/ROUT 0: Stereo Mixing (default) 1: Mono Mixing LODIF: Lineout Mode Select 0: Stereo Single-ended Line Output (LOUT/ROUT pins) (default) 1: Mono Full-differential Output (LOP/LON pins) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH HP Power Management HPTM 1 HPTM0 0 0 LOMH 0 PMHPR PMHPL R/W R/W R/W R R R/W R R/W R/W Default 0 0 0 0 0 0 0 0 PMHPL: HPL Power Management 0: Power down (default) 1: Power up PMHPR: HPR Power Management 0: Power down (default) 1: Power up LOMH: Mono Mixing from DAC to HPL/HPR 0: Stereo Mixing (default) 1: Mono Mixing HPTM1-0: Headphone-Amp Volume Zero Crossing Timeout Period ( Table 107) Default: “00” (128/fs)

[AK4679] MS1402-E-06 2013/02 - 164 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH Charge Pump Control 0 VDDTM2 VDDTM1 VDDTM0 0 0 CPMODE1 CPMODE0 R/W R R/W R/W R/ W R R R/W R/W Default 0 1 0 1 0 0 0 0 CPMODE1-0: Charge-pump Mode Setting (Table 108) Default: “00” (Automatic Switching) VDDTM2-0: VDD Mode Waiting Period ( Table 109) Default: “101” (32768/fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH SPK & RCV Power Management THDET 0 TEST PMSPK 0 0 RCVPS PMRCV R/W R R R/W R/W R R R/W R/W Default 0 0 0 0 0 0 0 0 PMRCV: Receiver-Amp Power Management 0: Power down (default) 1: Power up RCVPS: Receiver-Amp Power Save Mode 0: Normal Operation (default) 1: Power Save Mode PMSPK: Speaker-Amp Power Management 0: Power down (default) 1: Power up TEST: Device TEST mode Enable. 0: Normal operation (default) 1: TEST mode TEST bit must be always “0”. THDET: Thermal Shutdown Detection 0: Normal Operation (default) 1: Thermal Shutdown status Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH LINEOUT Volume Control 0 0 0 0 0 LVL2 LVL1 LVL0 R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 1 1 LVL2-0: LINEOUT Volume Control (Table 101) Default: “3H” (0dB)

[AK4679] MS1402-E-06 2013/02 - 165 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH HP Volume Control 0 0 HPG5 HPG4 HPG3 HPG2 HPG1 HPG0 R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 1 1 HPG5-0: Headphone Volume Control (Table 106) Default: “23H” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H SPK & RCV Volume Control RCVG3 RCVG2 RCVG1 RCVG0 SPKG3 SPKG2 SPKG1 SPKG0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 0 1 1 1 0 1 1 SPKG3-0: Speaker Volume Control (Table 111) Default: “BH” (0dB) RCVG3-0: Receiver Volume Control ( Table 104) Default: “BH” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 12H Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 0 0 1 0 0 0 1 IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level ( Table 37) Default: “91H” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 13H ALC Reference Select REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 REF7-0: Reference Value at ALC Recovery Operation (Recording); 0.375dB step, 242 Level (Table 33) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 14H Digital Mixing Control SRMXR1 SRMXR0 SRMXL1 SRMXL0 PFMXR1 PFMXR0 PFMXL1 PFMXL0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PFMXL1-0: 5-band EQ Lch Input Mixing 1 (Table 85) Default: “00” (SDTI) PFMXR1-0: 5-band EQ Rch Input Mixing 1 (Table 86) Default: “00” (SDTI) SRMXL1-0: 5-band EQ Lch Input Mixing 2 (Table 87) Default: “00” (SDTI) SRMXR1-0: 5-band EQ Rch Input Mixing 2 (Table 88) Default: “00” (SDTI)

[AK4679] MS1402-E-06 2013/02 - 166 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 15H ALC Timer Select FR RFST1 RFST0 WTM2 WTM1 WTM0 ZTM1 ZTM0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 30) Default: “00” (128/fs) WTM2-0: ALC Recovery Waiting Period (Table 31) Default: “000” (128/fs) RFST1-0: ALC Fast recovery Speed (Table 34) Default: “00” (4times) FR: Fast recovery Enable 0: Enable (default) 1: Disable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 16H ALC Mode Control LFST ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH1 LMTH0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 28) Default: “00” RGAIN1-0: ALC Recovery GAIN Step (Table 32) Default: “00” LMAT1-0: ALC Limiter ATT Step (Table 29) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable LFST: ALC Limiter operation when the output level exceeds FS(full-scale) level. 0: The volume is changed at zero crossing or zero crossing time out (default) 1: When output of ALC is larger than FS, IVL/IVR values are changed immediately (1/fs).

[AK4679] MS1402-E-06 2013/02 - 167 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 17H Mode Control 0 0 0 SDIM1 SDIM0 5EQ ADM IVOLC ALC R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 ALC: ALC Enable 0: ALC Disable (default) 1 : A L C E n a b l e IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively. ADM: Mono Recording ( Table 79) 0: Stereo (default) 1: Mono: (L+R)/2 5EQ: Select 5-Band Equalizer 0: OFF (default) 1: ON SDIM1-0: SDTI Input Signal Select ( Table 84) Default: “00” (L=Lch, R=Rch) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 18H Mode Control 0 0 OVTMB BIV2 BIV1 BIV0 SMUTE OVTM OVOLC R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 0 0 1 1 OVOLC: Output Digital Volu me Control Mode Select 0: Independent 1: Dependent (default) When OVOLC bit = “1”, OVL6-0 bits control both Lch and Rch volume level, while register values of OVL6-0 bits are not written to OVR6-0 bits. When OVOL C bit = “0”, OVL6-0 bits control Lch level and OVR6-0 bits control Rch level, respectively. OVTM: Digital Volume Transition Time Setting 0: 128/fs 1: 256/fs (default) This is the transition time between OVL/R6-0 bits = 00H and 7FH. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted BIV2-0: SDTIB Input Volume Control ( Table 75) Default: “0H” (0dB) OVTMB: Digital Volume Control (DATT-B and DATT-C) Transition Time Setting 0: 128/fs 1: 256/fs (default) This is the transition time between BVL6-0 bits or CVL6-0 bits = 00H and 7FH.

[AK4679] MS1402-E-06 2013/02 - 168 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 19H Digital Filter Select 0 0 HPFC1 HPFC0 HPFAD DASEL1 DASEL0 PFSDO PFSEL R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 0 0 1 0 PFSEL: Signal Select of Programmable Filter Block ( Table 78) 0: ADC Output Data (default) 1: SDTI Input Data PFSDO: SDTO Output and SVOLA Input Signal Select ( Table 80) 0: ADC (+1st HPF) Output 1: Programmable Filter Output (default) DASEL1-0: DAC Input Signal Select ( Table 89) Default: “00” (L= DATT-A Lch, R= DATT-A Rch) HPFAD: HPF1 Control of ADC 0: OFF 1: ON (default) When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, HPFAD block is through (0dB). When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”. HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) ( Table 38) Default: “00” (3.4Hz @ fs = 44.1kHz)

[AK4679] MS1402-E-06 2013/02 - 169 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1AH Digital Filter Select 1 GN1 GN0 LPF HPF EQ0 FIL3 0 0 R/W R/W R/W R/W R/W R/W R/W R R Default 0 0 0 0 0 0 0 0 FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. When FIL3 bit is “0”, FIL3 block is OFF (MUTE). EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E0C15-0 bits are enabled. When EQ0 bit is “0”, EQ0 block is through (0dB). HPF: HPF Coefficient Setting Enable 0: Disable (default) 1: Enable When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block is through (0dB). LPF: LPF Coefficient Setting Enable 0: Disable (default) 1: Enable When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block is through (0dB). GN1-0: Gain Select at GAIN block ( Table 27) Default: “00” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1BH Digital Filter Select 2 0 0 0 0 0 EQ3 EQ2 EQ1 R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 EQ1: Equalizer 1 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”, EQ1 block is through (0dB). EQ2: Equalizer 2 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”, EQ2 block is through (0dB). EQ3: Equalizer 3 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”, EQ3 block is through (0dB).

[AK4679] MS1402-E-06 2013/02 - 170 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1CH Side Tone A Control 0 S VAR2 SVAR1 SVAR0 0 SVAL2 SVAL1 SVAL0 R/W R R/W R/W R/ W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 SVAL2-0, SVAR2-0: Side Tone Volume A (SVOLA) (Table 39) Default: “000” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1DH Lch Output Volume Control 0 OVL6 OVL5 OVL4 OVL 3 OVL2 OVL1 OVL0 1EH Rch Output Volume Control 0 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 OVL6-0, OVR6-0: Output Digital Volume ( Table 68) Default: “0CH” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1FH PCM I/F Power Management PMMIX PMSRBO PMSRBI PMPCMB PMOS C PMSRAO PMSRAI PMPCMA R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMPCMA: PCM I/F A Power Management 0: Power down (default) 1: Power up PMSRAI: SRCAI Power Management 0: Power down (default) 1: Power up PMSRAO: SRCAO Power Management 0: Power down (default) 1: Power up PMOSC: Internal Oscillator Power Management 0: Power down (default) 1: Power up PMPCMB: PCM I/F B Power Management 0: Power down (default) 1: Power up PMSRBI: SRCBI Power Management 0: Power down (default) 1: Power up PMSRBO: SRCBO Power Management 0: Power down (default) 1: Power up PMMIX: MIX1 Block Power Management 0: Power down (default) 1: Power up

[AK4679] MS1402-E-06 2013/02 - 171 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 20H PCM I/F Control 0 SDOAD 0 MSBSA BCKPA LAWA1 LAWA0 FMTA1 FMTA0 R/W R/W R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 FMTA1-0: PCM I/F A Format (Table 117) Default: “00” (Mode 0) LAWA1-0: PCM I/F A Mode (Table 115) Default: “00” (Mode 0) BCKPA: P BICKA Polarity of PCM I/F A ( Table 119) “0”: SDTOA is output by the rising edge (“↑”) of BICKA and SDTIA is latched by the falling edge (“↓”). (default) “1”: SDTOA is output by the falling edge (“↓”) of BICKA and SDTIA is latched by the rising edge (“↑”). MSBSA: SYNCA Phase of PCM I/F A ( Table 119) “0”: The rising edge (“↑”) of SYNCA is half clock of BICKA before the channel change. (default) “1”: The rising edge (“↑”) of SYNCA is one clock of BICKA before the channel change. SDOAD: SDTOA Disable ( Table 96) “0”: Enable (default) “1”: Disable (“L”) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 21H PCM I/F Control 1 SDOBD 0 MSBSB BCKPB LAWB1 LAWB0 FMTB1 FMTB0 R/W R/W R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 FMTB1-0: PCM I/F B Format (Table 118) Default: “00” (Mode 0) LAWB1-0: PCM I/F B Mode (Table 116) Default: “00” (Mode 0) BCKPB: BICKB Polarity of PCM I/F B ( Table 120) “0”: SDTOB is output by the rising edge (“↑”) of BICKB and SDTIB is latched by the falling edge (“↓”). (default) “1”: SDTOB is output by the falling edge (“↓”) of BICKB and SDTIB is latched by the rising edge (“↑”). MSBSB: SYNCB Phase of PCM I/F B ( Table 120) “0”: The rising edge (“↑”) of SYNCB is half clock of BICKB before the channel change. (default) “1”: The rising edge (“↑”) of SYNCB is one clock of BICKB before the channel change. SDOBD: SDTOB Disable ( Table 98) “0”: Enable (default) “1”: Disable (“L”) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 22H Side Tone Volume B Control 0 0 0 0 0 SVB2 SVB1 SVB0 R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 SVB2-0: Side Tone Volume B ( Table 74) Default: “0H” (0dB)

[AK4679] MS1402-E-06 2013/02 - 172 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 23H Digital Volume B Control 0 BVL6 BVL5 BVL4 BVL3 BVL2 BVL1 BVL0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 BVL6-0: Digital Volume B ( Table 70) Default: “0CH” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 24H Digital Volume C Control 0 CVL6 CVL5 CVL4 CVL3 CVL2 CVL1 CVL0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 CVL6-0: Digital Volume C ( Table 72) Default: “0CH” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 25H Digital Mixing Control 0 0 0 MX1R2 MX1R1 MX1R0 MX1L2 MX1L1 MX1L0 R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MX1L2-0: MIX1 Lch Output Signal Select (Table 90) Default: “000” (DATT-B) MX1R2-0: MIX1 Rch Output Signal Select (Table 91) Default: “000” (DATT-B) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 26H Digital Mixing Control 1 0 0 MX2C1 MX2C0 MX2B1 MX2B0 MX2A1 MX2A0 R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MX2A1-0: MIX2A Output Signal Select (Table 92) Default: “00” (BIVOL Lch) MX2B1-0: MIX2B Output Signal Select (Table 93) Default: “00” (DATT-A Lch) MX2C1-0: MIX2C Output Signal Select (Table 94) Default: “00” (MIX2A) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 27H Digital Mixing Control 2 0 0 0 0 0 MXSB2 MXSB1 MXSB0 R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 MXSB2-0: MIX3 Output Signal Select (Table 95) Default: “000” (DATT-A Lch, DATT-A Rch)

[AK4679] MS1402-E-06 2013/02 - 173 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 28H Digital Mixing Control 3 SDOR1 SDOR0 SDOL1 SDOL0 0 0 SBMX1 SBMX0 R/W R/W R/W R/W R/W R R R/W R/W Default 0 0 0 0 0 0 0 0 SBXM1-0: DATT-C Input Signal Selec (Table 97) Default: “00” (SRCAI) SDOL1-0: SDTO Lch Output Mixing (Table 81) Default: “00” (Lch Signal Selected by Table 80) SDOR1-0: SDTO Rch Output Mixing (Table 82) Default: “00” (Rch Signal Selected by Table 80)

[AK4679] MS1402-E-06 2013/02 - 174 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 29H FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 2AH FIL1 Co-efficient 1 0 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 2BH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 2CH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” F1A13-0, F1B13-B0: FIL1 (Wind-noise Reduction Filter) Coefficient (14bit x 2) Default: F1A13-0 bits = “1FA9H”, F1B13-0 bits = “20ADH” (fc=150Hz@fs=44.1kHz) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 2DH FIL2 Co-efficient 0 F2A7 F2A6 F2A5 F2A4 F2A3 F2A2 F2A1 F2A0 2EH FIL2 Co-efficient 1 0 0 F2A13 F2A12 F2A11 F2A10 F2A9 F2A8 2FH FIL2 Co-efficient 2 F2B7 F2B6 F2B5 F2B4 F2B3 F2B2 F2B1 F2B0 30H FIL2 Co-efficient 3 0 0 F2B13 F2B12 F2B11 F2B10 F2B9 F2B8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 F2A13-0, F2B13-B0: FIL2 (LPF) Coefficient (14bit x 2) Default: “0000H” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 31H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 32H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 33H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 34H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 35H EQ Co-efficient 0 E0A7 E0A6 E0A5 E0A4 E0A3 E0A2 E0A1 E0A0 36H EQ Co-efficient 1 E0A15 E0A14 E0A13 E0A12 E0A11 E0A10 E0A9 E0A8 37H EQ Co-efficient 2 E0B7 E0B6 E0B5 E0B4 E0B3 E0B2 E0B1 E0B0 38H EQ Co-efficient 3 0 0 E0B13 E0B12 E0B11 E0B10 E0B9 E0B8 39H EQ Co-efficient 4 E0C7 E0C6 E0C5 E0C4 E0C3 E0C2 E0C1 E0C0 3AH EQ Co-efficient 5 E0C15 E0C14 E0C13 E0C12 E0C11 E0C10 E0C9 E0C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3(Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF E0A15-0, E0B13-0, E0C15-C0: EQ0 (Gain Compensation Filter) Coefficient (14bit x 1 + 16bit x 2) Default: “0000H”

[AK4679] MS1402-E-06 2013/02 - 175 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 3BH E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 3CH E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 3DH E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 3EH E1 Co-efficient 3 E1B15 E1B14 E1B13 E1B12 E1B11 E1B10 E1B9 E1B8 3FH E1 Co-efficient 4 E1C7 E1C6 E1C5 E1C4 E1C3 E1C2 E1C1 E1C0 40H E1 Co-efficient 5 E1C15 E1C14 E1C13 E1C12 E1C11 E1C10 E1C9 E1C8 41H E2 Co-efficient 0 E2A7 E2A6 E2A5 E2A4 E2A3 E2A2 E2A1 E2A0 42H E2 Co-efficient 1 E2A15 E2A14 E2A13 E2A12 E2A11 E2A10 E2A9 E2A8 43H E2 Co-efficient 2 E2B7 E2B6 E2B5 E2B4 E2B3 E2B2 E2B1 E2B0 44H E2 Co-efficient 3 E2B15 E2B14 E2B13 E2B12 E2B11 E2B10 E2B9 E2B8 45H E2 Co-efficient 4 E2C7 E2C6 E2C5 E2C4 E2C3 E2C2 E2C1 E2C0 46H E2 Co-efficient 5 E2C15 E2C14 E2C13 E2C12 E2C11 E2C10 E2C9 E2C8 47H E3 Co-efficient 0 E3A7 E3A6 E3A5 E3A4 E3A3 E3A2 E3A1 E3A0 48H E3 Co-efficient 1 E3A15 E3A14 E3A13 E3A12 E3A11 E3A10 E3A9 E3A8 49H E3 Co-efficient 2 E3B7 E3B6 E3B5 E3B4 E3B3 E3B2 E3B1 E3B0 4AH E3 Co-efficient 3 E3B15 E3B14 E3B13 E3B12 E3B11 E3B10 E3B9 E3B8 4BH E3 Co-efficient 4 E3C7 E3C6 E3C5 E3C4 E3C3 E3C2 E3C1 E3C0 4CH E3 Co-efficient 5 E3C15 E3C14 E3C13 E3C12 E3C11 E3C10 E3C9 E3C8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3) Default: “0000H” E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3) Default: “0000H” E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3) Default: “0000H”

[AK4679] MS1402-E-06 2013/02 - 176 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 50H 5band E1 Co-efficient 0 5E1A7 5E1A 6 5E1A5 5E1A4 5E1A3 5E1A2 5E1A1 5E1A0 51H 5band E1 Co-efficient 1 0 0 5E1A 13 5E1A12 5E1A11 5E1A10 5E1A9 5E1A8 52H 5band E1 Co-efficient 2 5E1B7 5E1B6 5E1B5 5E1B4 5E1B3 5E1B2 5E1B1 5E1B0 53H 5band E1 Co-efficient 3 0 0 5E1B13 5E1B12 5E1B11 5E1B10 5E1B9 5E1B8 54H 5band E2 Co-efficient 0 5E2A7 5E2A 6 5E2A5 5E2A4 5E2A3 5E2A2 5E2A1 5E2A0 55H 5band E2 Co-efficient 1 5E2A15 5E2A14 5E2A13 5E2A12 5E2A11 5E2A10 5E2A9 5E2A8 56H 5band E2 Co-efficient 2 5E2B7 5E2B6 5E2B5 5E2B4 5E2B3 5E2B2 5E2B1 5E2B0 57H 5band E2 Co-efficient 3 5E2B15 5E2B14 5E2B13 5E2B12 5E2B11 5E2B10 5E2B9 5E2B8 58H 5band E2 Co-efficient 4 5E2C7 5E2C6 5E2C5 5E2C4 5E2C3 5E2C2 5E2C1 5E2C0 59H 5band E2 Co-efficient 5 5E2C15 5E2C14 5E2C13 5E2C12 5E2C11 5E2C10 5E2C9 5E2C8 5AH 5band E3 Co-efficient 0 5E3A7 5E3A 6 5E3A5 5E3A4 5E3A3 5E3A2 5E3A1 5E3A0 5BH 5band E3 Co-efficient 1 5E3A15 5E3A14 5E3A13 5E3A12 5E3A11 5E3A10 5E3A9 5E3A8 5CH 5band E3 Co-efficient 2 5E3B7 5E3B6 5E3B5 5E3B4 5E3B3 5E3B2 5E3B1 5E3B0 5DH 5band E3 Co-efficient 3 5E3B15 5E3B14 5E3B13 5E3B12 5E3B11 5E3B10 5E3B9 5E3B8 5EH 5band E3 Co-efficient 4 5E3C7 5E3C 6 5E3C5 5E3C4 5E3C3 5E3C2 5E3C1 5E3C0 5FH 5band E3 Co-efficient 5 5E3C15 5E3C14 5E3C13 5E3C12 5E3C11 5E3C10 5E3C9 5E3C8 60H 5band E4 Co-efficient 0 5E4A7 5E4A 6 5E4A5 5E4A4 5E4A3 5E4A2 5E4A1 5E4A0 61H 5band E4 Co-efficient 1 5E4A15 5E4A14 5E4A13 5E4A12 5E4A11 5E4A10 5E4A9 5E4A8 62H 5band E4 Co-efficient 2 5E4B7 5E4B6 5E4B5 5E4B4 5E4B3 5E4B2 5E4B1 5E4B0 63H 5band E4 Co-efficient 3 5E4B15 5E4B14 5E4B13 5E4B12 5E4B11 5E4B10 5E4B9 5E4B8 64H 5band E4 Co-efficient 4 5E4C7 5E4C6 5E4C5 5E4C4 5E4C3 5E4C2 5E4C1 5E4C0 65H 5band E4 Co-efficient 5 5E4C15 5E4C14 5E4C13 5E4C12 5E4C11 5E4C10 5E4C9 5E4C8 66H 5band E5 Co-efficient 0 5E5A7 5E5A 6 5E5A5 5E5A4 5E5A3 5E5A2 5E5A1 5E5A0 67H 5band E5 Co-efficient 1 0 0 5E5A 13 5E5A12 5E5A11 5E5A10 5E5A9 5E5A8 68H 5band E5 Co-efficient 2 5E5B7 5E5B6 5E5B5 5E5B4 5E5B3 5E5B2 5E5B1 5E5B0 69H 5band E5 Co-efficient 3 0 0 5E5B13 5E5B12 5E5B11 5E5B10 5E5B9 5E5B8 R/W R/W R/W R/W R/W R/W R/W R/W R/W 5E1A13-0, 5E1B13-B0: 5-band Equalizer 1 Coefficient (14bit x 2) Default: 5E1A13-0 bits = “003AH”, 5E1B13-0 bits = “2074H” (fc=100Hz@fs=44.1kHz) 5E2A15-0, 5E2B15-0, 5E2C15-0: 5-band Equalizer 2 Coefficient (16bit x3) Default: 5E2A15-0 bits = “001DH”, 5E2B15-0 bits = “ 3FBB H”, 5E2C15-0 bits = “E03AH” (fo2=250Hz, fb2=50Hz@fs=44.1kHz) 5E3A15-0, 5E3B15-0, 5E3C15-0: 5-band Equalizer 3 Coefficient (16bit x3) Default: 5E3A15-0 bits = “0073H”, 5E3B15-0 bits = “3E76H”, 5E3C15-0 bits = “E0E6H” (fo3=1kHz, fb3=200Hz@fs=44.1kHz) 5E4A15-0, 5E4B15-0, 5E4C15-0: 5-band Equalizer 4 Coefficient (16bit x3) Default: 5E4A15-0 bits = “0185H”, 5E4B15-0 bits = “3589H”, 5E4C15-0 bits = “E30BH” (fo4=3.5kHz, fb4=700Hz@fs=44.1kHz) 5E5A13-0, 5E5B13-B0: 5-band Equalizer 5 Coefficient (14bit x 2) Default: 5E5A13-0 bits = “112CH”, 5E5B13-0 bits = “3DA9H” (fc=10kHz@fs=44.1kHz)

[AK4679] MS1402-E-06 2013/02 - 177 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 6AH 5band EQ1 Gain 0 0 5EQ1G5 5E Q1G4 5EQ1G3 5EQ1G2 5EQ1G1 5EQ1G0 6BH 5band EQ2 Gain 0 0 5EQ2G5 5E Q2G4 5EQ2G3 5EQ2G2 5EQ2G1 5EQ2G0 6CH 5band EQ3 Gain 0 0 5EQ3G5 5E Q3G4 5EQ3G3 5EQ3G2 5EQ3G1 5EQ3G0 6DH 5band EQ4 Gain 0 0 5EQ4G5 5E Q4G4 5EQ4G3 5EQ4G2 5EQ4G1 5EQ4G0 6EH 5band EQ5 Gain 0 0 5EQ5G5 5E Q5G4 5EQ5G3 5EQ5G2 5EQ5G1 5EQ5G0 R/W R R R/W R/W R/W R/W R/W R/W Default 0 0 0 1 1 0 0 0 5EQ1G5-0: 5-band Equalizer 1 Gain Setting Default: 18H (0dB) 5EQ2G5-0: 5-band Equalizer 2 Gain Setting Default: 18H (0dB) 5EQ3G5-0: 5-band Equalizer 3 Gain Setting Default: 18H (0dB) 5EQ4G5-0: 5-band Equalizer 4 Gain Setting Default: 18H (0dB) 5EQ5G5-0: 5-band Equalizer 5 Gain Setting Default: 18H (0dB) EQ gain: +12dB(00H) ~ -12dB(30H), 0.5dB step

[AK4679] MS1402-E-06 2013/02 - 178 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 70H DRC Mode Control 0 DLMAT2 DLMAT1 DLMAT0 DRGAIN1 DRGAIN0 DRCC1 DRCC0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DRCC1-0: DRC Enable (Table 65) 00: Disable (default) 01: Low 10: Middle 11: High When DRCC1-0 bits are “00”, DRC is through (0dB). DRGAIN1-0: DRC Recovery Speed Setting ( Table 67) Default: “00” DLMAT2-0: DRC ATT Speed Setting (Table 66) Default: “000” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 71H NS Control 0 0 DRCM1 DRCM0 0 NSLPF NSHPF NSCE R/W R R R/W R/W R R/W R/W R/W Default 0 0 0 0 0 0 0 0 NSCE: Noise Suppression Enable 0: Disable (default) 1: Enable When NSCE bit is “0”, Noise Suppression is through (0dB). NSHPF: HPF for Noise Suppression Coefficient Setting Enable 0: Disable (default) 1: Enable When NSHPF bit is “1”, the settings of NSHA13-0 and NSHB13-0 bits are enabled. When NSHPF bit is “0”, HPF block is through (0dB). NSLPF: LPF for Noise Suppression Coefficient Setting Enable 0: Disable (default) 1: Enable When NSLPF bit is “1”, the settings of NSLA13-0 and NSLB13-0 bits are enabled. When NSLPF bit is “0”, LPF block is through (0dB). DRCM1-0: DRC Input Signal Setting ( Table 41) Default: “00” (L = Lch, R = Rch) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 72H NS Gain & ATT Control 0 NSGAIN2 NSGAIN1 NSGAIN0 0 NSATT2 NSATT1 NSATT0 R/W R R/W R/W R/W R R/W R/W R/W Default 0 0 0 1 0 0 0 1 NSATT2-0: Noise Suppression ATT Speed Setting (Table 45) Default: “001” NSGAIN2-0: Noise Suppression Recovery Speed Setting (Table 48) Default: “001”

[AK4679] MS1402-E-06 2013/02 - 179 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 73H NS On Level NSIAF1 NSIAF0 0 NSTHL4 NSTHL3 NSTHL2 NSTHL1 NSTHL0 R/W R/W R/W R R/W R/W R/W R/W R/W Default 1 0 0 0 0 0 0 0 NSTHL4-0: Noise Suppression Threshold Low Level Setting (Table 43) Default: “00H” (-36dB) NSIAF1-0: Moving Average Parameter Setting at Noise Suppression Off (Table 42) Default: “10” (1024/fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 74H NS Off Level NSOAF1 NSOAF0 0 NSTHH4 NSTHH3 NST HH2 NSTHH1 NSTHH0 R/W R/W R/W R R/W R/W R/W R/W R/W Default 1 0 0 0 0 0 0 0 NSTHH4-0: Noise Suppression Threshold High Level Setting (Table 47) Default: “00H” (-36dB) NSOAF1-0: Moving Average Parameter Setting at Noise Suppression On (Table 46) Default: “10” (16/fs) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 75H NS Reference Select 0 0 0 0 NSREF3 NSREF2 NSREF1 NSREF0 R/W R R R R R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 NSREF3-0: Reference Value at Noise Suppression (Table 44) Default: “0H” (-9dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 76H NS LPF Co-efficient 0 NSLA7 NSLA 6 NSLA5 NSLA4 NSLA3 NSLA2 NSLA1 NSLA0 77H NS LPF Co-efficient 1 0 0 NSLA 13 NSLA12 NSLA11 NSLA10 NSLA9 NSLA8 78H NS LPF Co-efficient 2 NSLB7 NSLB 6 NSLB5 NSLB4 NSLB3 NSLB2 NSLB1 NSLB0 79H NS LPF Co-efficient 3 0 0 NSLB 13 NSLB12 NSLB11 NSLB10 NSLB9 NSLB8 7AH NS HPF Co-efficient 0 NSHA7 NS HA6 NSHA5 NSHA4 NSHA3 NSHA2 NSHA1 NSHA0 7BH NS HPF Co-efficient 1 0 0 NSHA13 NSHA12 NSHA11 NSHA10 NSHA9 NSHA8 7CH NS HPF Co-efficient 2 NSHB7 NSHB6 NSHB5 NSHB4 NSHB3 NSHB2 NSHB1 NSHB0 7DH NS HPF Co-efficient 3 0 0 NSHB13 NSHB12 NSHB11 NSHB10 NSHB9 NSHB8 R/W R/W R/W R/W R/W R/W R/W R/W R/W NSLA13-0, NSLB13-0: Noise Suppression LPF Coefficient (14bit x 2) Default: “0000H” NSHA13-0, NSHB13-0: Noise Suppression HPF Coefficient (14bit x 2) Default: “0000H”

[AK4679] MS1402-E-06 2013/02 - 180 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 80H DVLC Filter Select DLLPF1 DLLPF0 DMHPF1 DMHPF0 DMLPF1 DMLPF0 DHHPF1 DHHPF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DHHPF1-0: DVLC High Frequency Range HPF Coefficient Setting Enable (Table 58) 00: Disable (default) 01: 1st order HPF 10: 2nd order HPF 11: N/A When DHHPF1-0 bits are “01” or “10”, the settings of DHHA13-0 and DHHB13-0 bits are enabled. When DHHPF1-0 bits are “00”, HPF block outputs “0” data. DMLPF1-0: DVLC Middle Frequency Range LPF Coefficient Setting Enable ( Table 54) 00: Disable (default) 01: 1st order LPF 10: 2nd order LPF 11: N/A When DMLPF1-0 bits are “01” or “10”, the settings of DMLA13-0 and DMLB13-0 bits are enabled. When DMLPF1-0 bits are “00”, LPF block of DVLC middle frequency range is through (0dB). DMHPF1-0: DVLC Middle Frequency Range HPF Coefficient Setting Enable ( Table 53) 00: Disable (default) 01: 1st order HPF 10: 2nd order HPF 11: N/A When DMHPF1-0 bits are “01” or “10”, the settings of DMHA13-0 and DMHB13-0 bits are enabled. When DMHPF1-0 bits are “00”, HPF block of DVLC middle frequency range is through (0dB). DLLPF1-0: DVLC Low Frequency Range LPF Coefficient Setting Enable ( Table 49) 00: Disable (default) 01: 1st order LPF 10: 2nd order LPF 11: N/A When DLLPF1-0 bits are “01” or “10”, the settings of DLLA13-0 and DLLB13-0 bits are enabled. When DLLPF1-0 bits are “00”, LPF block outputs “0” data. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 81H DVLC Mode Control DVRGAIN2 DVRGAIN1 DVRGAIN0 DVLMAT2 DVLMAT1 DVLMAT0 DAF1 DAF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 1 0 1 1 1 1 DAF1-0: Moving Average Parameter Setting for DVLC ( Table 62) Default: “11” (Default: 2048/fs) DVLMAT2-0: DVLC ATT Speed Setting ( Table 63) Default: “011” DVRGAIN2-0: DVLC Recovery Speed Setting ( Table 64) Default: “011”

[AK4679] MS1402-E-06 2013/02 - 181 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 82H DVLCL Curve X1 0 0 VL1X5 VL1X4 VL1X3 VL1X2 VL1X1 VL1X0 83H DVLCL Curve Y1 0 0 VL1Y5 VL1Y4 VL1Y3 VL1Y2 VL1Y1 VL1Y0 84H DVLCL Curve X2 0 0 VL2X5 VL2X4 VL2X3 VL2X2 VL2X1 VL2X0 85H DVLCL Curve Y2 0 0 VL2Y5 VL2Y4 VL2Y3 VL2Y2 VL2Y1 VL2Y0 86H DVLCL Curve X3 0 0 0 VL3X4 VL3X3 VL3X2 VL3X1 VL3X0 87H DVLCL Curve Y3 0 0 0 VL3Y4 VL3Y3 VL3Y2 VL3Y1 VL3Y0 88H DVLCL Slope 1 0 L1G6 L1G5 L1G4 L1G3 L1G2 L1G1 L1G0 89H DVLCL Slope 2 0 L2G6 L2G5 L2G4 L2G3 L2G2 L2G1 L2G0 8AH DVLCL Slope 3 0 L3G6 L3G5 L3G4 L3G3 L3G2 L3G1 L3G0 8BH DVLCL Slope 4 0 L4G6 L4G5 L4G4 L4G3 L4G2 L4G1 L4G0 8CH DVLCM Curve X1 0 0 VM1X5 VM1X4 VM1X3 VM1X2 VM1X1 VM1X0 8DH DVLCM Curve Y1 0 0 VM1Y5 VM1Y4 VM1Y3 VM1Y2 VM1Y1 VM1Y0 8EH DVLCM Curve X2 0 0 VM2X5 VM2X4 VM2X3 VM2X2 VM2X1 VM2X0 8FH DVLCM Curve Y2 0 0 VM2Y5 VM2Y4 VM2Y3 VM2Y2 VM2Y1 VM2Y0 90H DVLCM Curve X3 0 0 0 VM3X4 VM3X3 VM3X2 VM3X1 VM3X0 91H DVLCM Curve Y3 0 0 0 VM3Y4 VM3Y3 VM3Y2 VM3Y1 VM3Y0 92H DVLCM Slope 1 0 M1G6 M1G5 M1G4 M1G3 M1G2 M1G1 M1G0 93H DVLCM Slope 2 0 M2G6 M2G5 M2G4 M2G3 M2G2 M2G1 M2G0 94H DVLCM Slope 3 0 M3G6 M3G5 M3G4 M3G3 M3G2 M3G1 M3G0 95H DVLCM Slope 4 0 M4G6 M4G5 M4G4 M4G3 M4G2 M4G1 M4G0 96H DVLCH Curve X1 0 0 VH1X5 VH1X4 VH1X3 VH1X2 VH1X1 VH1X0 97H DVLCH Curve Y1 0 0 VH1Y5 VH1Y4 VH1Y3 VH1Y2 VH1Y1 VH1Y0 98H DVLCH Curve X2 0 0 VH2X5 VH2X4 VH2X3 VH2X2 VH2X1 VH2X0 99H DVLCH Curve Y2 0 0 VH2Y5 VH2Y4 VH2Y3 VH2Y2 VH2Y1 VH2Y0 9AH DVLCH Curve X3 0 0 0 VH3X4 VH3X3 VH3X2 VH3X1 VH3X0 9BH DVLCH Curve Y3 0 0 0 VH3Y4 VH3Y3 VH3Y2 VH3Y1 VH3Y0 9CH DVLCH Slope 1 0 H1G6 H1G5 H1G4 H1G3 H1G2 H1G1 H1G0 9DH DVLCH Slope 2 0 H2G6 H2G5 H2G4 H2G3 H2G2 H2G1 H2G0 9EH DVLCH Slope 3 0 H3G6 H3G5 H3G4 H3G3 H3G2 H3G1 H3G0 9FH DVLCH Slope 4 0 H4G6 H4G5 H4G4 H4G3 H4G2 H4G1 H4G0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 VL1X5-0, VL2X5-0, VL3X4-0: Input Gain Setting for Low Range DVLC Point (Table 50, Table 51) Default: “00H” (0dB) VL1Y5-0, VL2Y5-0, VL3Y4-0: Output Gain Setting for Low Range DVLC Point (Table 50, Table 51) Default: “00H” (0dB) L1G6-0, L2G6-0, L3G6-0, L4G6-0: DVLC Slope Setting for Low Range (Table 52) Default: “00H” VM1X5-0, VM2X5-0, VM3X4-0: Input Gain Setting for Middle Range DVLC Point (Table 50, Table 51) Default: “00H” (0dB) VM1Y5-0, VM2Y5-0, VM3Y4-0: Output Gain Setting for Middle Range DVLC Point ( Table 50, Table 51) Default: “00H” (0dB) M1G6-0, M2G6-0, M3G6-0, M4G6-0: DVLC Slope Setting for Middle Range (Table 52) Default: “00H” VH1X5-0, VH2X5-0, VH3X4-0: Input Gain Setting for High Range DVLC Point (Table 50, Table 51) Default: “00H” (0dB) VH1Y5-0, VH2Y5-0, VH3Y4-0: Output Gain Setting for High Range DVLC Point ( Table 50, Table 51) Default: “00H” (0dB) H1G6-0, H2G6-0, H3G6-0, H4G6-0: DVLC Slope Setting for High Range (Table 52) Default: “00H”

[AK4679] MS1402-E-06 2013/02 - 182 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 A0H DVLCL LPF Co-efficient 0 DLLA7 DLLA6 DLLA5 DLLA4 DLLA3 DLLA2 DLLA1 DLLA0 A1H DVLCL LPF Co-efficient 1 0 0 DLLA13 DLLA12 DLLA11 DLLA10 DLLA9 DLLA8 A2H DVLCL LPF Co-efficient 2 DLLB7 DLLB6 DLLB5 DLLB4 DLLB3 DLLB2 DLLB1 DLLB0 A3H DVLCL LPF Co-efficient 3 0 0 DLLB13 DLLB12 DLLB11 DLLB10 DLLB9 DLLB8 A4H DVLCM HPF Co-efficient 0 DMHA7 DMHA6 DMHA5 DMHA4 DMHA3 DMHA2 DMHA1 DMHA0 A5H DVLCM HPF Co-efficient 1 0 0 DMHA13 DMHA12 DMHA11 DMHA10 DMHA9 DMHA8 A6H DVLCM HPF Co-efficient 2 DMHB7 DMHB6 DMHB5 DMHB4 DMHB3 DMHB2 DMHB1 DMHB0 A7H DVLCM HPF Co-efficient 3 0 0 DMHB13 DMHB12 DMHB11 DMHB10 DMHB9 DMHB8 A8H DVLCM LPF Co-efficient 0 DMLA7 DMLA6 DMLA5 DMLA4 DMLA3 DMLA2 DMLA1 DMLA0 A9H DVLCM LPF Co-efficient 1 0 0 DMLA13 DMLA12 DMLA11 DMLA10 DMLA9 DMLA8 AAH DVLCM LPF Co-efficient 2 DMLB7 DMLB6 DMLB5 DMLB4 DMLB3 DMLB2 DMLB1 DMLB0 ABH DVLCM LPF Co-efficient 3 0 0 DMLB13 DMLB12 DMLB11 DMLB10 DMLB9 DMLB8 ACH DVLCH HPF Co-efficient 0 DHHA7 DHHA6 DHHA5 DHHA4 DHHA3 DHHA2 DHHA1 DHHA0 ADH DVLCH HPF Co-efficient 1 0 0 DHHA13 DHHA12 DHHA11 DHHA10 DHHA9 DHHA8 AEH DVLCH HPF Co-efficient 2 DHHB7 DHHB6 DHHB5 DHHB4 DHHB3 DHHB2 DHHB1 DHHB0 AFH DVLCH HPF Co-efficient 3 0 0 DHHB13 DHHB12 DHHB11 DHHB10 DHHB9 DHHB8 R/W R/W R/W R/W R/W R/W R/W R/W R/W DLLA13-0, DLLB13-0: DVLC Low Frequency Range LPF Coefficient (14bit x 2) Default: “0000H” DMHA13-0, DMHB13-0: DVLC Middle Frequency Range HPF Coefficient (14bit x 2) Default: “0000H” DMLA13-0, DMLB13-0: DVLC Middle Frequency Range LPF Coefficient (14bit x 2) Default: “0000H” DHHA13-0, DHHB13-0: DVLC High Frequency Range HPF Coefficient (14bit x 2) Default: “0000H”

[AK4679] MS1402-E-06 2013/02 - 183 - ■ Register Map (DSP block) The DSP block control register settings are executed through a microcontroller interface. All registers below are initialized by the power down (PDNE pin = “L”). To ensure control register settings, this power-down (PDNE pin= “L”) must always be made when power up the AK4679. Control register settings should be made during DSP reset (DSPRSTN bit = “0”). Name D7 D6 D5 D4 D3 D2 D1 D0 PCONT0 0 0 0 SOCFG 0 0 0 PWSW PCONT1 0 0 0 0 0 0 0 MRSTN Name D7 D6 D5 D4 D3 D2 D1 D0 CONT0 FSD[3] FSD[2] FSD[1] FSD[0] 0 0 0 0 CONT1 LAW[1] LAW[0] DIFD[1] DIFD[0] BCKPD 0 TESTB TESTA CONT2 BANK[3] BANK[2] BANK[1] BANK[0 ] LOCKE CRCE WDTN EFEN CONT3 POMOD E DRMS[1] DRMS[0] DRAD[1 ] DRAD[0] 0 WAVP1[1] WAVP1[0 CONT4 LPDO4 LPDO3 LPDO2 LPDO1 SELDO4 SELDO3 PT2N SELPT CONT5 OUT4N OUT3N OUT 2N OUT1N 0 0 0 STRDY CONT6 0 0 DLRDY 0 0 DSPRST N 0 0 CONT7 SYDET CGLK 0 0 0 0 0 0 CONT8 TESTC 0 0 0 0 0 0 0 Note 83. The bits defined as 0 must set a “0” value. Note 84. Default value is the value after power-down release.

[AK4679] MS1402-E-06 2013/02 - 184 - Power Control: Internal Power Supply Control PCONT0: Internal power supply control Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address PCONT0 0 0 0 SOCFG 0 0 0 PWSW W R R/W R R R R/W R R R R/W D0h 50h Default 0 0 0 0 0 0 0 0 PWSW bit: Internal power supply switch control 0: power control SW off (default) 1: power control SW on SOCFG: SO pin configuration (this bit is valid for I2C pin = “L”) 0: CMOSL (default) 1: Wired ‘OR’ (Hi-impedance) Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address PCONT1 0 0 0 0 0 0 0 MRSTN W R R/W R R R R R R R R/W D1h 51h Default 0 0 0 0 0 0 0 0 MRSTN: Internal power supply reset control 0: Reset state (Default) 1: Reset Released

[AK4679] MS1402-E-06 2013/02 - 185 - Device Control Register CONT0: Initial Setting1 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT0 FSD[3:0] 0 0 0 0 W R R/W R/W R/W R/W R/W R R R R C0h 40h Default 0 0 0 0 0 0 0 0 FSD3-0: Sampling Frequency Select (Table 6) 00: fs1=fs2=8kHz (default) Write “0” into the “0” registers. CONT1: Initial Setting 2 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT1 LAW[1:0] DIFD[1:0] BCKPD 0 TESTB TESTA W R R/W R/W R/W R/ W R/W R/W R R R C1h 41h Default 0 0 0 0 0 0 0 0 LAW[1:0]: PCM I/F Port#1 Data Format (Table 125) 00:16 bit Linear (default) DIFD[1:0]: PCM I/F Port#1 SYNC Format Setting ( Table 126) 00: PCM Short Frame (default) BCKPD: PCM Format BCLK Edge Select ( Table 124) 0: Falling Edge (default) 1: Rising Edge TESTB, TESTA: Must write “0” into these bits.

[AK4679] MS1402-E-06 2013/02 - 186 - CONT2: Initial Setting 3 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT2 BANK[3:0] LOCKE CRCE WDTN EFEN W R R/W R/W R/W R/W R/W R/W R/W R/W R/W C2h 42h Default 0 0 0 0 0 0 0 0 BANK[3:0]: DSP DLRAM Mode Setting DSP Delay RAM Bank0 Bank1 Bank2 DLRAM Partition Mode BANK [3:0] Bit Ring 20.4f Linear 20.4f Linear 8bit μ-law codec 0 0000b 16384 words 0 0 (default) 1 0001b 14336 words 2048 words 0 2 0010b 12288 words 4096 words 0 3 0011b 10240 words 6144 words 0 4 0100b 8192 words 8192 words 0 5 0101b 6144 words 10240 words 0 6 0110b 4096 words 12288 words 0 7 0111b 2048 words 14336 words 0 8 1000b 0 16384 words 0 9 1001b 10240 words 0 18432words 10 1010b 8192 words 2048 words 18432words 11 1011b 6144 words 4096 words 18432words 12 1100b 4096 words 6144 words 18432words 13 1101b 2048 words 8192 words 18432words 14 1110b 0 10240 words 18432words 15 1111b N/A (N/A: Not available) LOCKE: Clock Generator Unit Lock Error status selects ( Table 129) 0: lock status monitor invalid (default) 1: lock status monitor Enable CRCE: DSP CRC status selects ( Table 129) 0: CRC status monitor invalid (default) 1: CRC status monitor enable WDTN: WDT Disable Switch of DSP ( Table 129) 0: WDT Enable (default) 1: WDT Disable EFEN: Extended Instruction Enable of DSP 0: Valid (default) 1: Invalid

[AK4679] MS1402-E-06 2013/02 - 187 - CONT3: DSP Setting 1 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT3 POMODE DRMS[1:0] DRAD[1:0] 0 WAVP[1:0] W R R/W R/W R/W R/W R/W R/W R R/W R/W C3h 43h Default 0 0 0 0 0 0 0 0 POMODE1: DLYRAM Pointer 0 Select 0: OFREG (default) 1: DBUS Immediate Data DRAM: DATA RAM Size Setting DSP Data RAM Bank1 Bank0 DRAM Mode DRMS[1:0] Bit Memory size [words] Memory size [words] 0 00 512 1536 (default) 1 01 1024 1024 2 10 1536 512 others others N/A (N/A: Not available) Addressing Mode Setting bit [1:0] DSP Data RAM Addressing mode DRAD Pointer Bank1 DP1 Bank0 DP0 0 00 Ring Ring 1 01 Ring Linear 2 10 Linear Ring 3 11 Linear Linear (default) WAVP[1:0]: CRAM Memory Assignment of DSP WAVP Mode WAVP[1] WAVP[0] FFT point 0 0 0 33word 128 (default) 1 0 1 65word 256 2 1 0 129word 512 3 1 1 257word 1024

[AK4679] MS1402-E-06 2013/02 - 189 - CONT5: Signal Setting 1 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT5 OUT4N OUT3N OUT2N OUT1N 0 0 0 STRDY W R R/W R/W R/W R/ W R/W R R R R/W C5h 45h Default 0 0 0 0 0 0 0 0 OUT4N: SDOUT4 pin output enable (active low) 0: SDOUT4 Output Enable (default) 1: SDOUT4 pin = “L” OUT3N: SDOUT3 pin output enable (active low) 0: SDOUT3 Output Enable (default) 1: SDOUT3 pin = “L” OUT2N: SDOUT2 pin output enable (active low) 0: SDOUT2 Output Enable (default) 1: SDOUT2 pin = “L” OUT1N: SDOUT1 pin output enable (active low) 0: SDOUT1 Output Enable (default) 1: SDOUT1 pin = “L” STRDY: STO/RDY pin select 0: STO Output (default) 1: RDY Output

[AK4679] MS1402-E-06 2013/02 - 190 - CONT6: Signal Setting 2 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT6 0 0 DLRDY 0 0 DSPRSTN 0 0 W R R/W R R R/W R R R/W R R C6h 46h Default 0 0 0 0 0 0 0 0 DLRDY: DSP Download Preparation 0: download inhibit (default) 1: download ready This bit is used when start to download the DSP programs. The bit must be cleared after downloading programs are completed. DSPRSTN: DSP Reset 0: DSP Reset (default) 1: DSP Reset Release CONT7: State Signal (Read only) Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT7 SYDET CGLK 0 0 0 0 0 0 W R R/W R R R R R R R R C7h 47h Default 0 0 0 0 0 0 0 0 DSP status output from the wait sync state to operational state (Run State) SYDET: SYNC Signal Detection flag 0: No SYNC1 pin Signal (Low or High fixed) (default) 1: SYNC1 pin Signal Detect This bit outputs DSP status in Wait Sync State until DSP Operational state (RUN). CGLK: Clock Generator Unit Lock Status 0: Clock Generator Unlocked State (default) 1: Clock Generator Locked State CONT8: Initial Setting 4 Register Name D7 D6 D5 D4 D3 D2 D1 D0 Register Address CONT8 TESTC 0 0 0 0 0 0 0 W R R/W R/W R R R R R R R C8h 48h Default 0 0 0 0 0 0 0 0 TESTC bit must be set “1”. (i.e. set the 80h value in this register) The TESTC bit is set after writing the power control register with the power suplly on.

[AK4679] MS1402-E-06 2013/02 - 191 - ■ Command Code map for the DSP 1. Command Code BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W flag Area to be accessed Acco mpanying data to the access area R/W Flag Write at “1”, Read at “0”. Access data and accompanying data BIT6 BIT5 BIT4 BIT3~0 0 0 0 Number of Write Write preparation to CRAM during RUN 0 0 1 Number of Write Write preparation to OFREG during RUN 0 1 0 0100 0010 Write operation to CRAM during RUN Write operation to OFREG during RUN 0 1 1 1000 0100 0010 Write operation to PRAM during DSP reset Write operation to CRAM during DSP reset Write operation to OFREG during DSP reset 1 0 0 Register Address Internal control registers 00h~08h 1 0 1 Register Address System power registers 00h~01h 1 1 0 0000 Device Identification (Read only) 1 1 1 0000 0010 0100 0110 1000 1010 1100 Error Status Read CRC Write/Read Write operation of JX code Read operation from MIR1 Read operation from MIR2 Read operation from MIR3 Read operation from MIR4 2. Address Address description is always LSB justified. Accessing command code BIT[6:4]= “000” to “011” requires 16bit address. Accessing command code BIT[6:4]= “100” to “111” requires no address. 3. Data Length of write data is depending on the writing area size. When accessing RAM, data may be written to sequential address locations by writing data continuously.

[AK4679] MS1402-E-06 2013/02 - 192 - ■ Write Command Code Address Data Length Description 0x80~0x8F 16bit 24bit×n Write preparation to CRAM during RUN. Command code BIT3~BIT0 bits determines the amount of write operation. (0x80 # of write: 1, 0x81 # of write: 2, ----, 0x8F # of write: 16) If the actual amount of write operations exceeds the defined amount, that data will be ignored. 0x90~0x9F 16bit 24bit×n Write preparation to OFREG during RUN Command code BIT3~BIT0 bits determines the amount of write operation. (0x90 # of write: 1, 0x91 # of write: 2, ----, 0x9F # of write: 16) If the actual amount of write operations exceeds the defined amount, that data will be ignored. 0xA2 16bit None Write operation to OFREG dur ing RUN. 0 address should be written. 0xA4 16bit None Write operation to CRAM duri ng RUN. 0 address should be written. 0xB2 16bit 24bit×n Write operation to OFREG during DSP reset 0xB4 16bit 24bit×n Write operation to CRAM during DSP reset 0xB8 16bit 40bit×n Write operation to PRAM during DSP reset 0xC0~0xC8 None 8bit Write operation to Register 0h~8h (except 7h) 0xD0~0xD None 8bit System Power Supply Registers 0h~1h Write 0xF2 None 16bit CRC Write 0xF4 None 8bit Write operation of DSP JX code Data length is defined by the command code which specifies the area to be accessed. When accessing RAM, data may be read from sequential address locations by reading data continuously. Writing other than the above-mentioned command code is prohibited. Table 132. List of Usable Command Codes in Write Sequence

Description

0x24 16bit 24bit×n CRAM/OFREG Write preparation data Read during RUN 0x32 16bit 24bit×n Read operation form OFREG during DSP reset 0x34 16bit 24bit×n Read operation from CRAM during DSP reset 0x38 16bit 40bit×n Read operation from PRAM during DSP reset 0x40~0x48 None 8bit Read operation from Register 0h~8h 0x50~0x 51 None 8bit Read operation from System Power Supply Register 0h~1h 0x60 None 8bit Device Identification 0x70 None 8bit DSP Error Status Read 0x72 None 16bit CRC result Read 0x76 None 32bit Read operation from MIR1 28-bit is upper-bit justified. Lower 4-bits are for validity flags. 0x78 None 32bit Read operation from MIR2 28-bit is upper-bit justified. Lower 4-bits are for validity flags. 0x7A None 32bit Read operation from MIR3 28-bit is upper-bit justified. Lower 4-bits are for validity flags. 0x7C None 32bit Read operation from MIR4 28-bit is upper-bit justified. Lower 4-bits are for validity flags. Reading other than the above-mentioned command code is prohibited. Table 133. List of Usable Command Codes in Read Sequence

[AK4679] MS1402-E-06 2013/02 - 193 - ■ Command Format DLRDY bit must be set “1” when the PRAM, CRAM, OFFREG will access on the sleep state. 1. Write Operation during DSP Reset 1-1. Program RAM (PRAM) Write (during DSP Reset) Field Write data (1) COMMAND Code 0xB8 (2) ADDRESS1 0 0 0 0 A11 A10 A9 A8 (3) ADDRESS2 A7 A6 A5 A4 A3 A2 A1 A0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24 (6) DATA3 D23~D16 (7) DATA4 D15~D8 (8) DATA5 D7~D0 Five bytes of data may be wr itten continuously for each address. 426H438H Note 79. SOPCFG bit selects SO output (Hi-z or Low) during CSN = “H”. 1-2. Coefficient RAM (CRAM) Write (during DSP Reset) Field Write data (1) COMMAND Code 0xB4 (2) ADDRESS1 0 0 0 0 0 A10 A9 A8 (3) ADDRESS2 A7 A6 A5 A4 A3 A2 A1 A0 (4) DATA1 D19~D12 (5) DATA2 D11~D4 (6) DATA3 D3~D0 0 0 0 0 Two bytes of data may be wr itten continuously for each address. 1-3. Offset REG (OFREG) Write (during DSP Rest) Field Write data (1) COMMAND Code 0xB2 (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 A4 A3 A2 A1 A0 (4) DATA1 0 0 0 0 0 0 0 0 (5) DATA2 0 D14 D13 D12 D11 D10 D9 D8 (6) DATA3 D7~D0 Three bytes of data may be wr itten continuously for each address. 2. Write Operation during DSP Reset (DLRDY bit = “1”) and RUN 2-1. Control Register Write (during DSP reset and RUN) Field Write data (1) COMMAND Code 0xC0~0xC8 (2) DATA D7~D0 Note 85. Write operation may be limited depending on register settings. (C7: read only register) 2-2. System Power Supply Register Write (during DSP Reset and RUN) Field Write data (1) COMMAND Code 0xD0~0xD1 (2) DATA D7~D0 Note 86. Write operation may be limited depending on register settings.

[AK4679] MS1402-E-06 2013/02 - 194 - 2-3. External Conditional Jump Code Write (during DSP Reset and RUN) Field Write data (1) COMMAND Code 0xF4 (2) DATA D7~D0 2-4. CRC Code Write (during DSP Reset and RUN) Field Write data (1) COMMAND Code 0xF2 (2) DATA D15~D8 (3) DATA D7~D0 3. Write Operation during RUN 3-1. Coefficient RAM (CRAM) Write Preparation (during Run) Preparation Write data (1) COMMAND Code 0x80~0x8F (one data at 80h, sixteen data at 8Fh) (2) ADDRESS1 0 0 0 0 0 A10 A9 A8 (3) ADDRESS2 A7 ~ A0 (4) DATA1 D19~D12 (5) DATA2 D11~D4 (6) DATA3 D3~D0 0 0 0 0 Three bytes of data may be wr itten continuously for each address. 3-2. Coefficient RAM (CRAM) Write Operation (during RUN) Execute Write data (1) COMMAND Code 0xA4 (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 Note 87. The COMMAND determines the length of the da ta. If the written data exceeds the allotted amount, the excess data is ignored. 3-3. Offset REG (OFREG) Write Preparation (during RUN) Preparation Write data (1) COMMAND Code 0x90~0x9F (one data at 0x90, sixteen data at 0x9F) (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 A4 A3 A2 A1 A0 (4) DATA1 0 0 0 0 0 0 0 0 (5) DATA2 0 D14 D13 D12 D11 D10 D9 D8 (6) DATA3 D7~D0 Three bytes of data may be wr itten continuously for each address. 3-4. Offset REG (OFREG) Write Operation (during RUN) Execute Write data (1) COMMAND Code 0xA2 (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 0 0 0 0 0 Note 88. The COMMAND determines the length of the da ta. If the written data exceeds the allotted amount, the excess data is ignored.

[AK4679] MS1402-E-06 2013/02 - 195 - 4. Read Operation (DLRDY bit = “1”) 4-1. Program RAM (PRAM) Read (during DSP Reset) Field Write data Readout data (1) COMMAND Code 0x38 (2) ADDRESS1 0 0 0 0 A11 A10 A9 A8 (3) ADDRESS2 A7 A6 A5 A4 A3 A2 A1 A0 (4) DATA1 0 0 0 0 D35 D34 D33 D32 (5) DATA2 D31~D24 (6) DATA3 D23~D16 (7) DATA4 D15~D8 (8) DATA5 D7~D0 Five bytes of data may be wr itten continuously for each address. 4-2. Coefficient RAM (CRAM) Read (during DSP Reset) Field Write data Readout data (1) COMMAND Code 0x34 (2) ADDRESS1 0 0 0 0 0 A10 A9 A8 (3) ADDRESS2 A7 ~ A0 (4) DATA1 D19~D12 (5) DATA2 D11~D4 (6) DATA3 D3~D0 0 0 0 0 Three bytes of data may be wr itten continuously for each address. 4-3. Offset REG (OFREG) Read (DSP Reset) Field Write data Readout data (1) COMMAND Code 0x32 (2) ADDRESS1 0 0 0 0 0 0 0 0 (3) ADDRESS2 0 0 0 A4 A3 A2 A1 A0 (4) DATA1 0 0 0 0 0 0 0 0 (5) DATA2 0 D14 D13 D12 D11 D10 D9 D8 (6) DATA3 D7~D0 Three bytes of data may be wr itten continuously for each address. 5. Read Operation (DLRDY bit = “1” and RUN state) 5-1. Control Register Read (during DSP Reset and RUN) Field Write data Readout data (1) COMMAND Code 0x40~0x47h (2) DATA D7~D0 5-2. System Power Supply Register Read (during DSP Reset and RUN) Field Write data Readout data (1) COMMAND Code 0x50~0x51 (2) DATA D7~D0 5-3. Device Identification (during DSP Reset and RUN) Field Write data Readout data (1) COMMAND Code 0x60 (2) DATA D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 1 1 0 0 1 1 9

[AK4679] MS1402-E-06 2013/02 - 196 - 5-4. CRC Code Reading (during DSP Reset and RUN) Field Write data Readout data (1) COMMAND Code 0x72 (2) DATA1 D15~D8 (3) DATA2 D7~D0 5-5. Error and GPO statuses Reading (DSP Reset and RUN) Field Write data Output (1) COMMAND Code 0x70 (2) DATA Active low output D7: CRCERRN 0: CRC error D6: WDTERRN 0: Watch Dog Timer error D5: CGERRN 0: Clock Generator unit lock error D4: GP0 0: clear 1: set D3: GP1 0: clear 1: set 6. Read Operation during RUN 6-1. CRAM Write Preparation Read (during RUN) Field Write data Readout data (1) COMMAND Code 0x24 (2) ADDRESS1 A15~A8 (3) ADDRESS2 A8~A0 (4) DATA1 D19~D12 (5) DATA2 D11~D4 (6) DATA3 D3~D0 0 0 0 0 6-2. OFREG Write Preparation Read (during RUN) Field Write data Readout data (1) COMMAND Code 0x24 (2) ADDRESS1 A15~A8 (3) ADDRESS2 A8~A0 (4) DATA1 0 0 0 0 0 0 0 0 (5) DATA2 0 0 0 D12~D8 (6) DATA3 D7~D0 6-3. MIR1/2/3/4 Read (during RUN) Field Write data Readout data (1) COMMAND Code 0x76(MIR1) 0x78(MIR2) 0x7A(MIR3) 0x7C(MIR4) (2) DATA1 D27~D20 (3) DATA2 D19~D12 (4) DATA3 D11~D4 (5) DATA4 D3 D2 D1 D0 (fl ag3) (flag2) (flag1) (flag0) Note 89. Data is valid only when all flags are zero.

address of write (16-bit all 0) and the number of data assigned by command code in this order.

1. Write Preparation Data Confirmation

preparation data. Execute write preparation again when the address and data are garbled by external noise. and address (16-bit all “0”) in this order. example, when 5 Data are written, from RAM address “10”, it is executed as shown below. Note: Address “13” is not executed until rewriting address “12”. Figure 140. CRAM/OFREG Write Preparation

demonstrates the optimum layout, power supply arrangements and measurement results. capacitors must be connected as close as possible to the pins. Figure 147. Typical Connection Diagram (Power Supply Block)

Figure 148. Typical Connection Diagram (Analog Input/Output Block) Typical signal connections are shown in 441H Figure 38.

[AK4679] MS1402-E-06 2013/02 - 204 - 1. Grounding and Power Supply Decoupling The AK4679 requires careful attention to power supply and grounding arrangements. AVDD, PVDD and SVDD are usually supplied from the system’s analog supply, and DVDD, TVDDA, TVDDE and VDDE are supplied from the system’s digital power supply. The power-up sequence between supplies (AVDD, PVDD, SVDD, DVDD, TVDDA, TVDDE or VDDE) is not critical. PDNA and PDNE pins should be held “L” when power supplies are tuning on. PDNA and PDNE pins are allowed to be “H” after all power supplies are applied and settled. To avoid pop noise at receiver output, headphone outputs, speaker output and line outputs, the AK4679 should be operated along the following recommended power-up/down sequence. 1) Power-up - PDNA and PDNE pins should be held “L” when power supplies are turning on. The AK4679 can be reset by keeping the PDNA pin “L” for 1.5μs or longer after all power supplies are applied and settled. - In the case that the power supplies are separated in two or more groups, SVDD should be powered ON first. 2) Power-down - Each of power supplies can be powered OFF after PDNA and PDNE pins are set to “L”. - In the case that the power supplies are separated in two or more groups, SVDD should be powered OFF last. VSS1~5 of the AK4679 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near the AK4679 as possible. Especially, the small value ceramic capacitor is to be closest. 2. Voltage Reference VCOM is a signal ground of this chip. A 1μF electrolytic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current is allowed to be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4679. 3. Charge Pump 2.2μF±50% capacitors between the CPA to CNA pins, the CPB to CNB pins and the VEE to VSS5 pins should be low ESR ceramic capacitors. These capacitors must be connected as close as possible to the pins. No load current may be drawn from the VEE pin. 4. Analog Inputs The input signal range scales with 1.0 x AVDD Vpp (typ) at MGNL=MGNR=0dB, AVDD=1.8V and single-ended input, centered around the internal common voltage (typ. 0.47 x AVDD). The input signal must be AC coupled using a capacitor. The cut-off frequency (fc) is 1/(2πRC). 5. Analog Outputs Stereo Line outputs and Mono Receiver output are centered at typ. 0.8 x AVDD. Stereo line output (LOUT/ROUT pins) must be AC –coupled using a capacitor. Receiver output (RCP/RCN pins) should be connected directly to a receiver. Headphone outputs (HPL/HPR pin) are centered at 0V and should be directly connected to a headphone. Speaker output is PWM output (Class-D) and it is not necessary to add an external filter such as LC filters.

When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. Figure 149. Clock Set Up Sequence (1) (1) After Power Up, PDNA pins = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679. (2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set. DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits should be set during this period. 1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.

1. PLL Slave Mode (BICK pin)

Figure 150. Clock Set Up Sequence (2) (1) After Power Up, PDNA pin = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679. PLL3-0 bits should be set during this period. 1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF. (5) Normal operation starts after that the PLL is locked.

Figure 151. Clock Set Up Sequence (3) (1) After Power Up, PDNA pin = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679. (2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set. DIF1-0, CM1-0 and FS3-0 bits should be set during this period. (max) when the external capacitance is 1μF. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied.

Figure 152. Clock Set Up Sequence (4) (1) After Power Up, PDNA pin = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679. (3) Dummy command (Addr:00H, Data:00H) must be executed before control register is set. After DIF1-0, CM1-0 and FS3-0 bits are set, M/S bit should be set to “1”. Then LRCK and BICK are output. 1.5ms when the exterenal capacitor connected to the VCOM pin is 1μF.

Figure 153. Stereo MIC Input Sequence “430H442H Example of the ALC setting (Recording Path)”. At first, clocks should be supplied according to “18H18H Clock Set Up” sequence. and then IVOL operation starts from the setting value when PMADL or PMADR bit is changed to “1”.

Figure 154. Headphone-Amp Output Sequence At first, clocks should be supplied according to “19H19H Clock Set Up” sequence.

Figure 155. Speaker-Amp Output Sequence At first, clocks should be supplied according to “20H20H Clock Set Up” sequence. VCOM rise time and PLL lock time after a sampling frequency is changed when the AK4679 is in PLL mode.

Figure 156. Stereo Lineout Sequence At first, clocks should be supplied according to “21H21H Clock Set Up” sequence. 300ms (max.) at C=1μF and AVDD=1.8V. LOUT and ROUT pins fall down to VSS1. Fall time is 300ms(max.) at C=1μF and AVDD=1.8V. LOPS bit should be set to “0” after LOUT and ROUT pins fall down.

Figure 161. Sequence of PCM I/F A to PCM I/F B (1) After Power Up, PDNA pin = “L” Æ “H”. “L” time of 1.5μs or more is needed to reset the AK4679. (2) Dummy command (Addr:00H, Data:00H) must be executed before control register is set. MX2C1-0, MXSB2-0, SBMX1-0 bits should be set during this period. VCOM should first be powered up before the other block operates. (4) Power Up Internal Oscillator, SRCAI, SRCAO, SRCBI, SRCBO, PCM I/F A port and PCM I/F B port. released by inputting SYNCA(SYNCB). (5) Power down Internal Oscillator, SRCAI, SRCAO, SRCBI, SRCBO, PCM I/F A port and PCM I/F B port.

Figure 162. Receiver-Amp Output Sequence → “1”. The initial time of SRCAI is 164/fs2 after SYNCA clock is supplied. After passing the initial time of SRCAI, the Receiver-Amp should enter power-save mode. The RCN pin rises up to VCOM voltage after PMRCV bit is changed to “1”. Receiver-Amp becomes to power-down mode. RCVPS bit should be set to “0” after Receiver-Amp power-down.

[AK4679] MS1402-E-06 2013/02 - 217 - PACKAGE 78pin BGA

0.9 MAX

0.4 Top View 0.4 4.5±0.1 4.5±0.1 4679 XXXX 78 φ 0.2 ~0.3 φ 0.08 S M Bottom View 0.08 S S 0.12∼0.2 AB AB 3.2 3.2 ■ Material & Lead finish Package molding compound: Epoxy, Halogen (bromine and chlorine) free Solder ball material: SnAgCu

[AK4679] MS1402-E-06 2013/02 - 218 - MARKING 4679 XXXX A XXXX: Date code (4 digit) Pin #A1 indication Date (Y/M/D) Revision Reason Page Contents 12/04/23 00 First Edition 12/05/15 01 Error Correction 4, 8-12, 58, 59, 159, 201 Pin names were corrected. LIN2/IN2+ → LIN2/IN2- RIN2/IN2- → RIN2/IN2+ 4 ■ Block Diagram Figure 1 was changed. 59 ■ MIC/LINE Input Selector Figure 53 was changed. 12/08/30 02 Error Correction

201 SYSTEM DESIGN

Figure 148: A connection to the microphone was changed. 12/11/02 03 Specification Change

24 Switching Characteristics

External Slave Mode, BICK Input Timing Period: 312.5ns → 312.5ns or 1/(126fs)s Note 52 was added. 12/11/22 04 Description Addition 138 ■ DSP STATE TRANSITION Sleep: The description was changed. Wait Sync: The description was changed. 13/01/28 05 Description Addition 48, 49, ■ PLL Mode A detailed description was added: Note 74 and Note 75 were added. Table 7 was added. 51 ■ PLL Master Mode The description was changed. 13/02/18 06 Error Correction 136 ■ PCM Audio Interface Format Description was changed. 137-139 Figure 110 ~ 117 were changed.

REVISION HISTORY

[AK4679] MS1402-E-06 2013/02 - 220 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.