AK4649

AK4649 AKM | Alldatasheet

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Technical content

[AK4649] MS1023-E-01 2010/08 - 1 - GENERAL DESCRIPTION The AK4649 features a stereo CODEC with a built-in Microphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit, and Output circuits include a Speaker-Amplifier. These ci rcuits are suitable for portable app lication with recording/playback function. The AK4649 is available in a 29pin CSP (3x3.3mm 0.5mm pitch), utilizing less board space than competitive offerings.

FEATURES

1. Recording Function

• Stereo Single-ended input with two Selector
• MIC Amplifier (+29dB/+26dB/+23dB/+20dB/+16dB/+12dB/+9dB/+6dB/+3dB/0dB)
• Digital ALC (Automatic Level Control) - Setting Range: +36dB ∼ −54dB, 0.375dB Step - Noise Suppression
• ADC Performance: S/(N+D): 80dB, DR, S/N: 89dB (MIC-Amp=+20dB, AVDD=3.3V) S/(N+D): 80dB, DR, S/N: 100dB (MIC-Amp=0dB, AVDD=3.3V)
• Wind-noise Reduction Filter
• 5 Band Notch Filter
• Stereo Separation Emphasis
• Digital MIC Interface 2. Playback Function
• Digital De-emphasis Filter (tc=50/15μs, fs=32kHz, 44.1kHz, 48kHz)
• Digital ALC (Automatic Level Control) - Setting Range: +36dB ∼ −54dB, 0.375dB Step - Noise Suppression
• Digital Volume Control: - 0dB ∼ −18dB, 6dB Step & 256 Linear Step (+0dB ∼ - 48.13dB & Mute)
• Stereo Separation Emphasis
• Stereo Line Output - S/(N+D): 87dB, S/N: 97dB
• Mono Speaker-Amp - SPK-AMP Performance: S/(N+D): 60dB@150mW, S/N: 98dB - BTL Output - Output Power: 400mW@8Ω (SVDD=3.3V)
• Analog Mixing: Mono Input Power Management 4. Master Clock: (1) PLL Mode
• Frequencies: 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin) 5. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
• PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz 24bit Stereo CODEC with MIC/SPK-AMP AK4649

• PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
• EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 6. μP I/F: 3-wire Serial, I2C Bus (Ver 1.0, 400kHz Fast-Mode) 7. Master/Slave mode 8. Audio Interface Format: MSB First, 2’s complement
• ADC: 24bit MSB justified, 16/24bit I2S
• DAC: 24bit MSB justified, 16bit LSB justified, 24bit LSB justified, 16/24bit I2S 9. Ta = −30 ∼ 85°C 10. Power Supply:
• Analog Power Supply (AVDD): 2.4 ∼ 3.6V
• Digital Power Supply (DVDD): 1.6 ∼ 3.6V
• Speaker Power Supply (SVDD): 2.4 ∼ 3.6V 11. Package : 29pin CSP (3 x 3.3mm, 0.5mm pitch) 12. Register Compatible with the AK4646 ■ Block Diagram MIC Power Supply MIC-Amp +20/+23/+26/+29dB A/D Stereo Separation HPF1 PMMP PMADL or PMADR Audio I/F D/A DATT SMUTE PMDAC Internal MIC External MIC Line Out PMSPK Speaker ALC PLL PMBP PMPLL Control Register MPWR/DMP LIN1/DMDAT RIN1/DMCLK LIN2 RIN2 SPP SPN SVDD VSS3 MIN AVDD VSS1 VCOM DVDD CCLK/SCL PDN CDTIO/CAD0 BICK LRCK SDTO SDTI MCKO MCKI VCOC PMLO LOUT ROUT VSS2 CSN/SDA 4-band EQ DEM PMPFIL LPF HPF2 1-band EQ I2C PMADL PMADR SDTI SDTO

Figure 1. Block Diagram

[AK4649] MS1023-E-01 2010/08 - 3 - ■ Ordering Guide AK4649ECB −30 ∼ +85°C 29 pin CSP (0.5mm pitch) AKD4649 Evaluation board for AK4649 ■ Pin Layout A BC E D Top View

6 VSS2 LRCK SDTI MCKO VSS3

5 DVDD MCKI BICK SDTO SVDD

4 CDTIO/

CAD0 CCLK/SCL CSN/SDA SPP SPN

3 PDN I2C ROUT LOUT

2 VCOC VSS1 MPWR/

1 VCOM AVDD RIN1/

[AK4649] MS1023-E-01 2010/08 - 4 - ■ Comparison with AK4646/AK4649 1. Function Function AK4646 AK4649 Resolution 16bit 24bit AVDD 2.2V ∼ 3.6V 2.4V ∼ 3.6V DVDD 1.6V ∼ 3.6V ← SVDD 2.2V ∼ 4.0V 2.4V ∼ 3.6V ADC DR, S/N 86dB @ MGAIN = 20dB 95dB @ MGAIN = 0dB 89dB @ MGAIN = 20dB 100dB @ MGAIN = 0dB DAC S/N 92dB 97dB Power Supply Current (PLL Master, All Power-Up) AVDD+DVDD: typ. 15mA AVDD+DVDD: typ. 12.5mA Output Voltage of MIC Power 0.8 x AVDD ← Input Level typ. 0.636 x AVDD @ MIC Gain=0dB typ. 0.7 x AVDD @ MIC Gain=0dB Output Level (line out) typ. 0.6 x AVDD @LOVL=0dB typ. 0.7 x AVDD @LOVL=0dB MIC-Amp 0dB/+10dB/+17dB/+20dB/+23dB/ +26dB/+29dB/+32dB 0dB/+3dB/+6dB/+9dB/+12dB/ +16dB/+20dB/+23dB/+26dB/+29dB HPF with ADC (HPF1) Programmable 4 values (fc = 3.4Hz/13.6Hz/108.8Hz/217.6Hz @ fs=44.1kHz) Notch Filter 5 Step 5 Step (4 Step + 1 Step) ALC Noise Suppression No Yes Programmable Filter Bypass Mode No Yes Digital MIC I/F No Yes Output Volume +36dB ∼ -54dB, 0.375dB Step(Note 1) & 0dB ∼ -18dB, 6dB Step +36dB ∼ -54dB, 0.375dB Step (Note 1) & 0dB ∼ -18dB, 6dB Step & +0dB ∼ -48.13dB, 256 Linear Step MIN Input Gain Setting External Resistor Extern al Resistor/Internal VOL MIN Feedback Resistance typ. 20kΩ typ. 33k Ω Piezo Speaker Support Yes No μP I/F 3-Wire Serial (Write/Read) 3- Wire Serial (Write/Read) + I2C Audio I/F DAC 24 bit LSB justified No Yes Master Clock frequency for PLL Mode 12MHz, 13.5MHz, 24MHz, 27MHz 11.2896MHz, 12MHz, 13.5MHz, 24MHz, 27MHz Package EN: 32QFN (5x5mm, 0.5mm pitch) EZ: 32QFN (4x4mm, 0.4mm pitch) 29 pin CSP (3x3.3mm, 0.5mm pitch) Note 1. ALC and Volume circuits are shared by input and output. Therefore, it is impossible to use ALC and Volume function at the same time for both recording and playback mode.

[AK4649] MS1023-E-01 2010/08 - 5 - 2. Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 PMPFIL PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL 01H Power Management 2 0 0 0 0 M/S 0 MCKO PMPLL 02H Signal Select 1 SPPSN BEEPS DACS DACL MGAIN3 PMMP MGAIN2 MGAIN0 03H Signal Select 2 0 LOPS MGAIN1 SPKG1 SPKG0 BEEPL LOVL1 LOVL0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0 06H Timer Select ADRST WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0 07H ALC Mode Control 1 LFST ALC2 ALC1 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 08H ALC Mode Control 2 IREF7 IREF6 IREF5 IREF4 IREF3 IREF2 IREF1 IREF0 09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0AH Output Volume Control OVL 7 OVL6 OVL5 OVL4 OVL 3 OVL2 OVL1 OVL0 0BH ALC Mode Control 3 RGAIN1 LMTH1 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 0DH ALC LEVEL VOL7 VOL6 VOL 5 VOL4 VOL3 VOL2 VOL1 VOL0 0EH Mode Control 3 READ 0 SMUTE OVOLC DATT1 DATT0 DEM1 DEM0 0FH Digital Volume Control DVOL7 DVOL6 DVOL5 DVOL4 DVOL3 DVOL2 DVOL1 DVOL0 10H Power Management 3 IVOLC 0 0 0 0 INR INL PMADR 11H Digital Filter Select 1 GN1 GN0 LPF HPF EQ0 FIL3 0 HPFAD 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ0-efficient 0 E0A7 E0A6 E0A5 E0A4 E0A3 E0A2 E0A1 E0A0 17H EQ0-efficient 1 E0A15 E0A14 E0 A13 E0A12 E0A11 E0A10 E0A9 E0A8 18H EQ0-efficient 2 E0B7 E0B6 E0B5 E0B4 E0B3 E0B2 E0B1 E0B0 19H EQ0-efficient 3 0 0 E0B13 E0B12 E0B11 E0B10 E0B9 E0B8 1AH EQ0-efficient 4 E0C7 E0C6 E0C5 E0C4 E0C3 E0C2 E0C1 E0C0 1BH EQ0-efficient 5 E0C15 E0C14 E0C13 E0C12 E0C11 E0C10 E0C9 E0C8 1CH HPF Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH HPF Co-efficient 1 0 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH HPF Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH HPF Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 20H Reserved 0 0 0 0 0 0 0 0 21H Reserved 0 0 0 0 0 0 0 0 22H Reserved 0 0 0 0 0 0 0 0 23H Reserved 0 0 0 0 0 0 0 0 24H BEEP Volume Control 0 0 0 0 0 BPLVL2 BPLVL1 BPLVL0 25H Rch Output Volume Control OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 26H Programmable Filter Mode 0 0 0 0 0 PFDAC ADCPF PFSDO 27H Digital MIC 0 MPDMP PMDMR PMDML DCLKE DMPE DCLKP DMIC 28H BEEP/HPF Mode Select HPFC1 HPFC0 0 0 0 0 0 BPM 29H Noise Suppression 1 0 NSCE NSTHH1 NSTHH0 NSTHL3 NSTHL2 NSTHL1 NSTHL0 2AH Noise Suppression 2 0 0 NATT1 NATT0 0 0 NSGAIN1 NSGAIN0 2BH Noise Suppression 3 NSREF7 NSREF6 NSREF5 NSREF4 NSREF3 NSREF2 NSREF1 NSREF 0 Note: Different registers from the AK4646 are Shaded. 2CH~4FH Address are the same as the AK4646’s.

[AK4649] MS1023-E-01 2010/08 - 6 - PIN/FUNCTION No. Pin Name I/O Function A1 VCOM O Common Voltage Output Pin Bias voltage of ADC inputs and DAC outputs. A2 VCOC O Output Pin for Loop Filter of PLL Circuit This pin must be connected to VSS1 with one resistor and capacitor in series. B1 AVDD - Analog Power Supply Pin B2 VSS1 - Ground 1 Pin E3 LOUT O Lch Analog Output Pin D3 ROUT O Lch An alog Output Pin C3 I2C I Control Mode Select Pin “H”: I 2C Bus, “L”: 3-wire Serial CSN I Chip Select Pin (I2C pin = “L”) C4 SDA I/O Control Data Input/Output Pin (I2C pin = “H”) C D T I O I / O C h i p S e l e c t P i n ( I 2 C p i n = “ L ” ) A4 CAD0 I Chip Address Select Pin (I2C pin = “H”) CCLK I Control Data Clock Pin (I2C pin = “L”) B4 SCL I Control Data Clock Pin (I2C pin = “H”) B6 LRCK I/O Input/Output Channel Clock Pin B5 MCKI I External Master Clock Input Pin C5 BICK I/O Audio Serial Data Clock Pin C6 SDTI I Audio Serial Data Input Pin D5 SDTO O Audio Serial Data Output Pin B3 PDN I Power-down & Reset When “L”, the AK4649 is in power-down mode and is held in reset. The AK4649 must be always reset upon power-up. D6 MCKO O Master Clock Output Pin A5 DVDD - Digital Power Supply Pin A6 VSS2 - Ground 2 Pin D4 SPP O Speaker Amp Positive Output Pin E5 SVDD - Speaker Amp Power Supply Pin E6 VSS3 - Ground 3 Pin E4 SPN O Speaker Amp Negative Output Pin E2 MIN I Mono Analog Signal Input Pin LIN1 I Lch Analog Input Line Input 1Pin (DMIC bit = “0”) D1 DMDAT I Digital Microphone Data Input Pin (DMIC bit = “1”) RIN1 I Rch Analog Input 1 Pin (DMIC bit = “0”) C1 DMCLK O Digital Microphone Clock pin (DMIC bit = “1”) D2 LIN2 I Lch Analog Input 2 pin E1 RIN2 I Rch Analog Input 2 Pin MPWR O MIC Power Supply Pin for Microphone (MPDMP bit = “0”) C2 DMP O MIC Power Supply pin for Digital Microphone (MPDMP bit = “1”) Note 2. All input pins except analog input pins (MIN, LIN1, RIN1, LIN2, RIN2) must not be left floating

[AK4649] MS1023-E-01 2010/08 - 7 - ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Pin Name Setting Analog MPWR/DMP, VCOC, SPN, SPP, ROUT, LOUT, MIN, RIN2, LIN2, LIN1/DMDAT, RIN1/DMCLK These pins must be open. MCKO These pins must be open. Digital MCKI This pin must be connected to VSS2. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=VSS3=0V; Note 3) Parameter Symbol min max Units Power Supplies: Analog AVDD −0.3 4.6 V Digital DVDD −0.3 4.6 V Speaker-Amp SVDD −0.3 4.6 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 5) VINA −0.3 AVDD+0.3 V Digital Input Voltage (Note 6) VIND −0.3 DVDD+0.3 V Ambient Temperature (powered applied) Ta −30 85 °C Storage Temperature Tstg −65 150 °C Maximum Power Dissipation (Note 7) Pd1 - 390 mW Note 3. All voltages are with respect to ground. Note 4. VSS1, VSS2 and VSS3 must be connected to the same analog ground plane. Note 5. MIN, LIN1, RIN1, LIN2 and RIN2 pins Note 6. PDN, CSN, CCLK, CDTIO, SDTI, LRCK, BICK and MCKI pins Note 7. In case that PCB wiring density is 200% over and surface wiring density is 50% over. This power is the AK4649 internal dissipation that does not include power dissipation of an externally connected speaker. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=VSS3=0V; Note 3) Parameter Symbol min typ Max Units Power Supplies Analog AVDD 2.4 3.3 3.6 V (Note 8) Digital DVDD 1.6 3.3 3.6 V SPK-Amp SVDD 2.4 3.3 3.6 V Difference DVDD-AVDD - - +0.6 V AVDD−SVDD - - +1.0 V Note 3. All voltages are with respect to ground. Note 8. The power-up sequence between AVDD, DVDD and SVDD is not critical. The PDN pin must be “L” upon power up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. * When DVDD is powered ON and the PDN pin is “L”, AVDD or SVDD can be powered OFF. However, when AVDD is powered OFF, the power supply current of DVDD at power-down mode may be increased. When the AK4649 is changed from power down state to power ON, the PDN pin must be “H” after all power supplies are ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4649] MS1023-E-01 2010/08 - 8 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=SVDD=3.3V; VSS1=VSS2=VSS3=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Units MIC Amplifier: LIN1, RIN1, LIN2, RIN2 pins Input Resistance 20 30 40 kΩ MGAIN3-0 bits = “0000” -1 0 +1 dB MGAIN3-0 bits = “0001” +19 +20 +21 dB MGAIN3-0 bits = “0010” +25 +26 +27 dB Gain MGAIN3-0 bits = “0100” +8 +9 +10 dB MGAIN3-0 bits = “0101” +15 +16 +17 dB MGAIN3-0 bits = “0110” +22 +23 +24 dB MGAIN3-0 bits = “0111” +28 +29 +30 dB MGAIN3-0 bits = “1000” +2 +3 +4 dB MGAIN3-0 bits = “1001” +5 +6 +7 dB MGAIN3-0 bits = “1010” +11 +12 +13 dB MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.38 2.64 2.90 V Load Resistance 0.5 - - kΩ Load Capacitance - - 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2 pins → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution - - 24 Bits (Note 11) 70 80 - dBFSS/(N+D) (−1dBFS) (Note 12) - 80 - dBFS (Note 11) 79 89 - dB D-Range (−60dBFS, A-weighted) (Note 12) - 100 - dB (Note 11) 79 89 - dB S/N (A-weighted) (Note 12) - 100 - dB (Note 11) 75 90 - dB Interchannel Isolation (Note 12) - 100 - dB (Note 11) - 0 0.8 dB Interchannel Gain Mismatch (Note 12) - 0 0.8 dB Note 9. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ) Note 10. Input voltage is proportional to AVDD voltage. Vin = 0.07 x AVDD (typ) @MGAIN3-0 bits = “0001” (+20dB), Vin = 0.7 x AVDD (typ) @MGAIN3-0 bits = “0000” (0dB) Note 11. MGAIN3-0 bits = “0001” (+20dB) Note 12. MGAIN3-0 bits = “0000” (0dB)

[AK4649] MS1023-E-01 2010/08 - 9 - Parameter min typ max Units DAC Characteristics: Resolution - - 24 Bits Stereo Line Output Characteristics: DAC → LOUT, ROUT pins, ALC=OFF, DVOL=OVOL=DATT=0dB, LOVL1-0 bit = “00”, RL=10kΩ Output Voltage (Note 13) LOVL1-0 bit = “00” 2.08 2.31 2.54 Vpp LOVL1-0 bit = “01” 2.62 2.91 3.20 Vpp S/(N+D) (−3dBFS) 77 87 - dBFS S/N (A-weighted) 87 97 - dB Interchannel Isolation 85 100 - dB Interchannel Gain Mismatch - 0 0.8 dB Load Resistance 10 - - kΩ Load Capacitance - - 30 pF Speaker-Amp Characteristics: DAC → SPP/SPN pins, ALC=OFF, DVOL=OVOL=DATT=0dB, RL=8Ω, BTL Output Voltage (Note 14) SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) - 3.18 - Vpp SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW) 3.20 4.00 4.80 Vpp SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW) - 1.79 - Vrms S/(N+D) SPKG1-0 bits = “00”, −0.5dBFS (Po=150mW) - 60 - dB SPKG1-0 bits = “01”, −0.5dBFS (Po=250mW) 20 50 - dB SPKG1-0 bits = “10”, −0.5dBFS (Po=400mW) - 20 - dB S/N (A-weighted) 88 98 - dB Load Resistance 8 - - Ω Load Capacitance - - 30 pF Note 13. Output voltage is proportional to AVDD voltage. Vout = 0.7 x AVDD (typ) @LOVL1-0 bit = “00”. Note 14. Output voltage is proportional to AVDD voltage. In case of Full-differential (DAC Input Level = 0dBFS), Vout = 1.02 x AVDD (typ) @SPKG1-0 bits = “00”, 1.28 x AVDD (typ) @SPKG1-0 bits = “01”, 1.62 x AVDD (typ ) @ SPKG1-0 bits = “10”. The output level is calculated by assuming that output signal is no clipped. In the actual case, output signal may be clipped when DAC outputs 0dBFS signal. Therefore, DAC output level should be set to lower level by setting digital volume so that Speaker-Amp output level is not clipped.

[AK4649] MS1023-E-01 2010/08 - 10 - Parameter min typ max Units Mono Input: MIN pin, External Resistance mode (BPM bit = “0”), External Input Resistance=33kΩ Maximum Input Voltage (Note 15) - 2.31 - Vpp Gain (Note 16) MIN Æ LOUT/ROUT LOVL1-0 bit = “00” -4.5 0 +4.5 dB LOVL1-0 bit = “01” - +2 - dB LOVL1-0 bit = “10” - +4 - dB LOVL1-0 bit = “11” - +6 - dB MIN Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” -1.2 +3.3 +7.8 dB ALC bit = “0”, SPKG1-0 bits = “01” - +5.3 - dB ALC bit = “0”, SPKG1-0 bits = “10” - +7.3 - dB ALC bit = “0”, SPKG1-0 bits = “11” - +9.3 - dB ALC bit = “1”, SPKG1-0 bits = “00” - +5.3 - dB ALC bit = “1”, SPKG1-0 bits = “01” - +7.3 - dB ALC bit = “1”, SPKG1-0 bits = “10” - +9.3 - dB ALC bit = “1”, SPKG1-0 bits = “11” - +11.3 - dB Mono Input: MIN pin, Internal Resistance Mode (BPM bit = “1”) Input Resistance 23 33 43 kΩ Maximum Input Voltage (Note 17) - 2.31 - Vpp Gain MIN Æ LOUT/ROUT LOVL1-0 bit = “00” -1 0 +1 dB LOVL1-0 bit = “01” - +2 - dB LOVL1-0 bit = “10” - +4 - dB LOVL1-0 bit = “11” - +6 - dB MIN Æ SPP/SPN ALC bit = “0”, SPKG1-0 bits = “00” +1.3 +3.3 +5.3 dB ALC bit = “0”, SPKG1-0 bits = “01” - +5.3 - dB ALC bit = “0”, SPKG1-0 bits = “10” - +7.3 - dB ALC bit = “0”, SPKG1-0 bits = “11” - +9.3 - dB ALC bit = “1”, SPKG1-0 bits = “00” - +5.3 - dB ALC bit = “1”, SPKG1-0 bits = “01” - +7.3 - dB ALC bit = “1”, SPKG1-0 bits = “10” - +9.3 - dB ALC bit = “1”, SPKG1-0 bits = “11” - +11.3 - dB Note 15. The Maximum input voltage is in proportion to both AVDD and external input resistance (Rin). Vin = 0.7 x AVDD x Rin / 33kΩ (typ). Note 16. The gain is in inverse proportion to external input resistance. Note 17. The Maximum input voltage is in proportion to AVDD. Vin = 0.7 x AVDD (typ) @ BPLVL = 0dB.

[AK4649] MS1023-E-01 2010/08 - 11 - Parameter min typ max Units Power Supplies: Power Up (PDN pin = “H”) All Circuit Power-up (Note 18) AVDD+DVDD - 12.5 19 mA AVDD+DVDD ( Note 19) - 8.0 - mA SVDD (No Load) - 4.0 12 mA MIC + ADC (Note 20) AVDD+DVDD - 5.0 - mA DAC + Lineout (Note 21) AVDD+DVDD - 2.6 - mA Power Down (PDN pin = “L”) (Note 22) AVDD+DVDD+SVDD - 1 5 μA Note 18. When PLL Master Mode (MCKI=12MHz), and PMADL = PMADR = PMDAC =PMPFIL = PMLO = PMSPK = PMVCM = PMPLL = MCKO = PMBP = PMMP = M/S bits = “1”. The MPWR pin outputs 0mA. AVDD = 6.8mA (typ), DVDD = 5.7mA (typ). Note 19. When DVDD=1.8V, EXT Slave Mode (PMPLL=M/S=MCKO bits =“0”), PMADL = PMADR = PMDAC = PMLO = PMSPK = PMVCM = PMBP = PMMP bits = “1”, and PMPFIL bit = “0”. The MPWR pin outputs 0mA. AVDD = 6.3mA (typ), DVDD = 1.7mA(typ). Note 20. When DVDD=1.8V, EXT Slave Mode (PMPLL = M/S = MCKO bits =“0”), PMADL = PMADR = PMVCM bits = “1”, and PMPFIL bit = “0”. AVDD = 3.8mA (typ), DVDD = 1.2mA(typ). Note 21. When DVDD=1.8V, EXT Slave Mode (PMPLL = M/S = MCKO bits =“0”), PMDAC = PMLO = PMVCM bits = “1”, and PMPFIL bit = “0”. AVDD = 1.6mA (typ), DVDD = 1.0mA(typ). Note 22. All digital input pins are fixed to DVDD or VSS2.

[AK4649] MS1023-E-01 2010/08 - 12 - FILTER CHARACTERISTICS Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 23) ±0.16dB PB 0 - 17.3 kHz −0.66dB - 19.4 - kHz −1.1dB - 19.9 - kHz −6.9dB - 22.1 - kHz Stopband SB 26.1 - - kHz Passband Ripple PR - - ±0.1 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 24) GD - 19 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): HPFC1-0 bits = “00” Frequency Response −3.0dB FR - 3.4 - Hz −0.5dB - 10 - Hz −0.1dB - 22 - Hz DAC Digital Filter (LPF): Passband (Note 23) ±0.05dB PB 0 - 20.0 kHz −6.0dB - 22.05 - kHz Stopband SB 24.1 - - kHz Passband Ripple PR - - ±0.02 dB Stopband Attenuation SA 54 - - dB Group Delay (Note 24) GD - 20 - 1/fs DAC Digital Filter (LPF) + SCF: Frequency Response: 0 ∼ 20.0kHz FR - ±1.0 - dB Note 23. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=20.0kHz (@−1.0dB) is 0.454 x fs (ADC). Each response refers to that of 1kHz Note 24. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 24-bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 24-bit data of both channels from the input register to the output of analog signal. For the signal through the programmable filters (First HPF + First LPF + 4-band Equalizer + ALC + Equalizer), group delay is increased 5/fs at Recording Mode or 7/fs at Playback Mode from the value above if there is no phase change by the IIR filter.

[AK4649] MS1023-E-01 2010/08 - 13 - DC CHARACTERISTICS Parameter Symbol min typ max Units Audio Interface & Serial µP Interface (CDTIO/CAD0, CSN/SDA, CCLK/SCL, I2C, PDN, BICK, LRCK, SDTI, MCKI pins ) High-Level Input Voltage (DVDD ≥ 2.2V) (DVDD < 2.2V) Low-Level Input Voltage (DVDD ≥ 2.2V) (DVDD < 2.2V) VIH VIL 70%DVDD 80%DVDD 30%DVDD 20%DVDD V V V V Audio Interface & Serial µP Interface (CDTIO, SDA MCKO, BICK, LRCK, SDTO pins Output) High-Level Output Voltage (Iout = −80μA) Low-Level Output Voltage (Except SDA pin : Iout = 80μA) (SDA pin, 2.0V ≤ DVDD ≤ 3.6V: Iout = 3mA) (SDA pin, 1.6V ≤ DVDD < 2.0V: Iout = 3mA) VOH VOL1 VOL2 VOL2 DVDD−0.2 0.2 0.4 20%DVDD V V V Input Leakage Current Iin - - ±10 μA Digital MIC Interface (DMDAT pin Input ; DMIC bit = “1”) High-Level Input Voltage Low-Level Input Voltage VIH3 VIL3 65%AVDD 35%AVDD V V Digital MIC Interface (DMCLK pin Output ; DMIC bit = “1”) High-Level Output Voltage (Iout=−80μA) Low-Level Output Voltage (Iout= 80μA) VOH3 VOL3 AVDD-0.4 0.4 V V Input Leakage Current Iin - - ±10 μA

[AK4649] MS1023-E-01 2010/08 - 14 - SWITCHING CHARACTERISTICS (Ta = 25°C; AVDD=SVDD=2.4 ∼ 3.6V, DVDD =1.6 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Output Timing Frequency fs 7.35 - 48 kHz Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Duty 45 - 55 % BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns

[AK4649] MS1023-E-01 2010/08 - 15 - Parameter Symbol min typ max Units PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Duty 45 - 55 % BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 240 - - ns Pulse Width High tBCKH 240 - - ns PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz Duty Duty 45 - 55 % BICK Input Timing Period PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns External Slave Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 - 12.288 MHz 512fs fCLK 3.7632 - 13.312 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Input Timing Frequency 256fs fs 7.35 - 48 kHz 512fs fs 7.35 - 26 kHz 1024fs fs 7.35 - 13 kHz Duty Duty 45 - 55 % BICK Input Timing Period tBCK 312.5 - - ns Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns External Master Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 - 12.288 MHz 512fs fCLK 3.7632 - 13.312 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Output Timing Frequency fs 7.35 - 48 kHz Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - %

[AK4649] MS1023-E-01 2010/08 - 16 - Parameter Symbol min typ max Units Audio Interface Timing Master Mode BICK “↓” to LRCK Edge (Note 25) tMBLR −40 - 40 ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD −70 ns BICK “↓” to SDTO tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK Edge to BICK “↑” (Note 25) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 25) tBLR 50 - - ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD ns BICK “↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Control Interface Timing (3-wire Mode): CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTIO Setup Time tCDS 40 - - ns CDTIO Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN Edge to CCLK “↑” (Note 26) tCSS 50 - - ns CCLK “↑” to CSN Edge (Note 26) tCSH 50 - - ns CCLK “↓” to CDTIO (at Read Command) tDCD - - 70 ns CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 28) tCCZ - - 70 ns Control Interface Timing (I2C Bus Mode): SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μs Clock Low Time tLOW 1.3 - - μs Clock High Time tHIGH 0.6 - - μs Setup Time for Repeated Start Condition tSU:STA 0.6 - - μs SDA Hold Time from SCL Falling ( Note 29) tHD:DAT 0 - - μs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μs Rise Time of Both SDA and SCL Lines tR - - 0.3 μs Fall Time of Both SDA and SCL Lines tF - - 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 - - μs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppre ssed by Input Filter tSP 0 - 50 ns Note 25. BICK rising edge must not occur at the same time as LRCK edge. Note 26. CCLK rising edge must not occur at the same time as CSN edge. Note 27. I 2C-bus is a trademark of NXP B.V. Note 28. RL=1kΩ/10% change (pull-up or DVDD) Note 29. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Note 30. The AK4649 can be reset by the PDN pin = “L”. Note 31. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”. Note 32. MCKO is not available at EXT Master mode. Figure 2. Clock Timing (PLL/EXT Master mode)

There are the following five clock modes to interface with external devices (Table 1, Table 2). clocks are output from the MCKO pin. Table 1. Clock Mode Setting (x: Don’t care)

0 L PLL Slave Mode

0 L GND

PMADL bit = PMADR bit = “0”. Table 2. Clock pins state in Clock Mode state, the AK4649 goes to master mode by changing M/S bit = “1”.

0 Slave Mode (default)

1 Master Mode

Table 3. Select Master/Slave Mode

powered-up (PMPLL bit = “0” → “1”) or when the sampling frequency is changed. Note 35. R has a tolerance of ± 5%, and C has a tolerance of ± 30%. **Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not Available)** Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin), Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2

Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) data when the PLL is unlocked. For DAC, the output signal can be muted by writing “0” to DACL and DACS bits. Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)

Figure 14. PLL Master Mode Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = “1”) Table 10. BICK Output Frequency at Master Mode

Table 9) and the output is enabled by MCKO bit. Figure 15. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)

Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. through LOUT/ROUT pins at fs=8kHz is shown in Table 12. Table 12. Relationship between MCKI and S/N of LOUT/ROUT pins mode (PMADL=PMADR=PMDAC = PMPFIL bits = “0”). Figure 18. EXT Slave Mode

Table 13. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. Table 14. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 19. EXT Master Mode Table 15. BICK Output Frequency at Master Mode

their initial value. The PDN pin recommends inputting “L” at power-up. complete. When using a digital microphone, the initialization cycle is the same as ADC’s. Table 16. ADC Initialization Cycle the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”). Table 17. Audio Interface Format “32768” at 24-bit(“128” at 16-bit) to 24-bit(16-bit) data before converting to 8-bit data.

Figure 23. Mode 3 Timing PMDMR bit is “1”, PMADL and PMADR bits setting are ignored. Table 18. Mono/Stereo ADC operation (Analog MIC) Table 19. Mono/Stereo ADC operation (Digital MIC)

“1”, digital microphone input is selected regardless of INL and INR bits. Table 20. MIC/Line In Path Select 21). The typical input impedance is 30kΩ (typ). Table 21. Input Gain (N/A: Not available)

resistance is minimum 2kΩ for each channel. Any capacitor must not be connected directly to the MPWR pin (Figure 24).

0 Hi-Z (default)

1 Output

Table 22. MIC Power (MPDMP bit = “0”) Figure 24. MIC Block Circuit

1. Connection to Digital MIC

output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is 0%~100%.

0 Rch Lch (default)

1 Lch Rch

Figure 27. Data In/Output Timing with Digital MIC (DCLKP bit = “0”) Figure 28. Data In/Output Timing with Digital MIC (DCLKP bit = “1”) Figure 29. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)

4 Band

1 Band

(1) ADC: Include the Digital Filter (LPF) for ADC as shown in “FILTER CHRACTERISTICS”. (2) HPF1: Include the Digital Filter (HPF) for ADC as shown in “FILTER CHRACTERISTICS”. (3) DAC: Include the Digital Filter (LPF) for DAC as shown in “FILTER CHRACTERISTICS”. frequency response and the gain after the Stereo Separation Emphasis Filter. Figure 30. Digital Block Path Select

Table 23. Recording Playback Mode (x: Don’t care) Figure 31. Path at Recording Mode 1 (default) Figure 32. Path at Playback Mode 1 Figure 33. Path at Recording Mode 2 & Playback Mode 2 Figure 34. Path at Loopback Mode

[AK4649] MS1023-E-01 2010/08 - 40 - ■ Digital Programmable Filter Circuit (1) High Pass Filter (HPF2) Normally, this HPF is used for Wind-Noise Reduction. This is composed 1st order HPF. The coefficient of HPF is set by F1A13-0 bits and F1B13-0 bits. HPF bit controls ON/OFF of the HPF2. When the HPF2 is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when HPF bit = “0” or PMPFIL bit = “0”. The HPF2 starts operation 4/fs(max) after when HPF bit=PMPFIL bit= “1” is set. fs: Sampling frequency fc: Cut-off frequency Register setting ( Note 36) HPF: F1A[13:0] bits =A, F1B[13:0] bits =B (MSB=F1A13, F1B13; LSB=F1A0, F1B0) A = 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 − z −1 1 + Bz −1 The cut-off frequency must be set as below. fc/fs ≥ 0.0001 (fc min = 4.41Hz at 44.1kHz) (2) Low Pass Filter (LPF) This is composed with 1st order LPF. F2A13-0 bits and F2B13-0 bits set the coefficient of LPF. LPF bit controls ON/OFF of the LPF. When the LPF is OFF, the audio data passes this block by 0dB gain. The coefficient must be set when LPF bit = “0” or PMPFIL bit = “0”. The LPF starts operation 4/fs(max) after when LPF bit =PMPFIL bit= “1” is set. fs: Sampling frequency fc: Cut-off frequency Register setting ( Note 36) LPF: F2A[13:0] bits =A, F2B[13:0] bits =B (MSB=F2A13, F1B13; LSB=F2A0, F2B0) A = 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 + z −1 1 + Bz −1 The cut-off frequency must be set as below. fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)

[AK4649] MS1023-E-01 2010/08 - 41 - (3) Stereo Separation Emphasis Filter (FIL3) FIL3 is used to emphasize the stereo separation of a stereo microphone recording data or playback data. F3A13-0 and F3B13-0 bits set the filter coefficient of FIL3. FIL3 becomes High Pass Filter (HPF) at F3AS bit = “0”, and Low Pass Filter (LPF) at F3AS bit = “1”. FIL3 bit controls ON/OFF of the FIL3. When Stereo Separation Emphasis Filter is OFF, the audio data passes this block by 0dB gain. The coefficient, must be set when FIL3 bit = “0” or PMPFIL bit = “0”. The FIL3 starts operation 4/fs(max) after when FIL3 bit= PMPFIL bit= “1” is set. 1) When FIL3 is set to “HPF” fs: Sampling frequency fc: Cut-off frequency K: Filter gain [dB] (0dB ≥ K ≥ −10dB) Register setting ( Note 36) FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F3A13, F3B13; LSB=F3A0, F3B0) A = 10K/20 x 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 − z −1 1 + Bz −1 2) When FIL3 is set to “LPF” fs: Sampling frequency fc: Cut-off frequency K: Filter gain [dB] (0dB ≥ K ≥ −10dB) Register setting ( Note 36) FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F3A13, F3B13; LSB= F3A0, F3B0) A = 10K/20 x 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) Transfer function H(z) = A 1 + z −1 1 + Bz −1

Emphasis Filter. Gain Compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+12dB/+24dB). Figure 35. EQ0 Frequency Response Table 24. Gain select of gain block (x: Don’t care)

[AK4649] MS1023-E-01 2010/08 - 43 - (5) 4-band Equalizer & 1-band Equalizer after ALC This block can be used as Equalizer or Notch Filter. 4-band Equalizer (EQ2, EQ3, EQ4 and EQ5) is selected ON/OFF independently by EQ2, EQ3, EQ4 and EQ5 bits. The equalizer after ALC (EQ1) is controlled by EQ1 bit. When Equalizer is OFF, the audio data passes this block by 0dB gain. E1A15-0, E1B15-0 and E1C15-0 bits set the coefficient of EQ1. E2A15-0, E2B15-0 and E2C15-0 bits set the coefficient of EQ2. E3A15-0, E3B15-0 and E3C15-0 bits set the coefficient of EQ3. E4A15-0, E4B15-0 and E4C15-0 bits set the coefficient of EQ4. E5A15-0, E5B15-0 and E5C15-0 bits set the coefficient of EQ5. The EQx (x=1∼5) coefficient must be set when EQx bit = “0” or PMPFIL bit = “0”. EQ1-5 start operation 4/fs(max) after when EQx (X=1~5) = PMPFIL bit = “1”is set. fs: Sampling frequency fo 1 ~ fo5: Center frequency fb1 ~ fb5: Band width where the gain is 3dB different from center frequency K1 ~ K5: Gain (−1 ≤ Kn ≤ 3) Register setting (Note 36) EQ1: E1A[15:0] bits =A1, E1B[15:0] bits =B1, E1C[15:0] bits =C1 EQ2: E2A[15:0] bits =A2, E2B[15:0] bits =B2, E2C[15:0] bits =C2 EQ3: E3A[15:0] bits =A3, E3B[15:0] bits =B3, E3C[15:0] bits =C3 EQ4: E4A[15:0] bits =A4, E4B[15:0] bits =B4, E4C[15:0] bits =C4 EQ5: E5A[15:0] bits =A5, E5B[15:0] bits =B5, E5C[15:0] bits =C5 (MSB=E1A15, E1B15, E1C15, E2A15, E2B15, E2C15, E3A15, E3B15, E3C15, E4A15, E4B15, E4C15, E5A15, E5B15, E5C15 ; LSB= E1A0, E1B0, E1C0, E2A0, E2B0, E2C0, E3A0, E3B0, E3C0, E4A0, E4B0, E4C0, E5A0, E5B0, E5C0) An = Kn x tan (πfbn/fs) 1 + tan (πfbn/fs) Bn = cos(2π fon/fs) x 1 + tan (πfbn/fs) , C n = 1 − tan (πfbn/fs) 1 + tan (πfbn/fs) Transfer function hn (z) = An 1 − z −2 1− Bnz −1− Cnz −2 The center frequency must be set as below. fon / fs < 0.497 When gain of K is set to “-1”, this equalizer becomes a notch filter. When EQ2 ∼EQ5 is used as a notch filter, central frequency of a real notch filter deviates from the above-mentioned calculation, if its central frequency of each band is near. The control soft that is att ached to the evaluation board has functions that revises a gap of frequency and calculates the coefficient. When its central frequency of each band is n ear, the central frequency should be revised and confirm the frequency response. Note 36. [Translation the filter coefficient calculated by th e equations above from real num ber to binary code (2’s complement)] X = (Real number of filter coefficient calculated by the equations above) x 2 X must be rounded to integer, and then should be translated to binary code (2’s complement). MSB of each filter coefficient setting register is sine bit.

ON/OFF of ALC operation at recording path, and ALC2 bit controls of ON/OFF of ALC operation at playback path. Note 37. In this section, VOL means IVL and IVR for recording path, OVL and OVR for playback path. Note 38. In this section, ALC bit means ALC1 bit for recording path, ALC2 bit for playback path. Note 39. In this section, REF means IREF for recording path, OREF for playback path. (same value for both L and R) is attenuated automatically by the amount defined by the ALC limiter ATT step (Table 26). The VOL is then set to the same value for both channels. full-scale, VOL values are changed at the individual zero crossing point of each channels or at the zero crossing timeout. limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. input signal level exceeds LMTH1-0 bits. Table 25. ALC Limiter Detection Level / Recovery Counter Reset Level Table 26. ALC Limiter ATT Step

Table 27. ALC Zero Crossing Timeout Period IVR are set to the same value for both channels. The ALC recovery operation is executed in a period set by WTM2-0 bits. reference level (REF7-0), the VOL values are not increased. the waiting timer of ALC recovery operation starts. Table 28. ALC Recovery Operation Waiting Period Table 29. ALC Recovery GAIN Step

Table 30. Reference Level at ALC Recovery Operation for Recoding Table 31. Reference Level at ALC Recovery Operation for Playback Table 32. First Recovery Speed Setting (N/A: Not available)

1. The Volume at ALC Operation

reading the register value of VOL7-0 bits. Table 33. Value of VOL7-0 bits Table 34 and Table 35 show the examples of the ALC setting for recording and playback path. Table 34. Example of the ALC Setting (Recording)

Table 35. Example of the ALC Setting (Playback) = “1”). This function attenuates output signal level automatically when minute amount of the signal is input. Level” set by NSTHL3-0 bits (Table 36) during the waiting time set by WTM2-0 bits (Table 28). which is set by ZTM1-0 bits (Table 27). It is executed in the cycle of WTM2-0 bits settings.

Table 36. Noise Suppression Threshold Low Level Note 41. 1step attenuated in 4 x “WTM cycles”. Note 42. 1step attenuated in 2 x “WTM cycles”. Table 37. Noise ATT Settings Table 27. ALC Zero Cross Timeout Period Settings Level >input signal level ≥ Noise Suppression Threshold Low Level) therefore the output signal level does not change. Table 38. Noise Suppression High Level Settings

during the operation switches to normal ALC operation from noise suppressing. Table 39. Fast Recovery Speed Setting from Noise Suppression to ALC Operation Table 40. Reference Value Setting when Noise Suppression is ON

1. Example of registers set-up sequence of ALC1 Operation

Figure 36. Registers Set-up Sequence at ALC1 Operation (recording path)

1. After exiting reset state, set-up the registers for ALC operation (ZTM1-0, LMTH and etc)
2. When the registers for ALC operation (Limiter period, Recovery period and etc) are changed.

For example; when the change of the sampling frequency.

1. When IVOL is used as a manual volume control.

IVR7-0 bits when IVOLC bit = “0”. IVL7-0 bits control both Lch and Rch volumes together when IVOLC bit = “1”. Table 41. Input Digital Volume Setting PMPFIL bit is changed to “1”.

crossing timeout period is set by ZTM1-0 bits. Table 42. Output Digital Volume Setting could be written in an interval less than zero crossing timeout. Table 43. This volume control is also available during ALC operation. Table 43. Output Digital Volume2 Setting

The AK4649 has a digital output volume control (256 levels, linear step, MUTE). It is processed before the DAC block. Table 45. This volume control is also available during ALC operation. Table 44. Output Digital Volume3 Setting Table 45. Output Digital Volume 3 Formula 44.1kHz). HPFAD bit controls the ON/OFF of the HPF1 (Recommend HPF enable). Table 46. HPF1 Cut-off Frequency

48kHz) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 47). Table 47. De-emphasis Control the signal source without stopping the signal transmission at playback path. Figure 37. Soft Mute Function (2) Analog output corresponding to digital input has group delay (GD).

a stereo line output amplifier. When BPM bit is set to “0”, the external resister Ri adjusts the signal level of MIN input.

0 External Resistance Mode (default)

1 Internal Resistance Mode

Table 48. BEEP Mode Setting

1. External Resistance Mode (BPM bit = “0”)

Figure 38. Block Diagram of MIN pin (BPM bit =“0”)

1. Internal Resistance Mode (BPM bit = “1”)

Table 51. BEEP Output Gain Setting (BPM bit = “1”) Figure 39. Block Diagram of MIN pin (BPM bit =“1”)

Figure 41. Rise/Fall time is 300ms (max) at C=1 μF and RL=10kΩ. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal operation. LOVL bit set the gain of stereo line output. Figure 40. Stereo Line Output

0 Power-down Pull-down to VSS1 (default) 0 1 Normal Operation Normal Operation

0 Power-save Fall down to VSS1 1 1 Power-save Rise up to VCOM

Table 52. Stereo Line Output Mode Select Table 53. Stereo Line Output Volume Setting Figure 41. External Circuit for Stereo Line Output (when using Pop Noise Reduction Circuit)

Figure 42. Stereo Line Output Control Sequence (when using Pop Noise Reduction Circuit) (1) Set LOPS bit = “1”. Stereo line output enters the power-save mode. (2) Set PMLO bit = “1”. Stereo line output exits the power-down mode. LOUT and ROUT pins rise up to 99% VCOM voltage. Rise time is 200ms (max 300ms) at C=1μF. (3) Set LOPS bit = “0”. After LOUT and ROUT pins rise up, stereo line output exits the power-save mode. Stereo line output is enabled. (4) Set LOPS bit = “1”. Stereo line output enters power-save mode. (5) Set PMLO bit = “0”. Stereo line output enters power-down mode. LOUT and ROUT pins fall down to 1% VCOM voltage. Fall time is 200ms (max 300ms) at C=1μF. set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits. Table 54. SPK-Amp Gain volume so that Speaker-Amp output level is 4.0Vpp or less and output signal is not clipped. Table 55. SPK-Amp Output Level

Speaker-Amp is powered-up/down by PMSPK bit. When PMSPK bit is “0”, both SPP and SPN pins are in Hi-Z state. placed in Hi-Z state and the SPN pin outputs SVDD/2 voltage. pop noise can be also reduced by first entering power-save-mode.

0 Power-save Hi-Z SVDD/2 1 1 Normal Operation Normal Operation Normal Operation

Figure 43. Power-up/Power-down Timing for Speaker-Amp

is 5MHz (max). The value of internal registers are initialized by the PDN pin = “L”. address 12H ∼ 23H, 2C~2FH, 32H~7FH, the register values are invalid. Figure 44. Serial Control I/F Timing

connected to (DVDD+0.3)V or less voltage. Figure 45 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by START condition. condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). indicates that the write operation is to be executed. generating stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten. Figure 45. Data Transfer Sequence at I2C Bus Mode Figure 46. The First Byte

0 A6 A5 A4 A3 A2 A1 A0

Figure 47. The Second Byte Figure 48. The Third Byte

[AK4649] MS1023-E-01 2010/08 - 65 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 PMPFIL PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL 01H Power Management 2 0 0 0 0 M/S 0 MCKO PMPLL 02H Signal Select 1 SPPSN BEEPS DACS DACL MGAIN3 PMMP MGAIN2 MGAIN0 03H Signal Select 2 0 LOPS MGAIN1 SPKG1 SPKG0 BEEPL LOVL1 LOVL0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0 06H Timer Select ADRST WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0 07H ALC Mode Control 1 LFST ALC2 ALC1 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 08H ALC Mode Control 2 IREF7 IREF6 IREF5 IREF4 IREF3 IREF2 IREF1 IREF0 09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0AH Lch Output Volume Control OVL7 OVL6 OVL5 OVL4 OVL3 OVL2 OVL1 OVL0 0BH ALC Mode Control 3 RGAIN1 LMTH1 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 0DH ALC LEVEL VOL7 VOL6 VOL 5 VOL4 VOL3 VOL2 VOL1 VOL0 0EH Mode Control 3 READ 0 SMUTE OVOLC DATT1 DATT0 DEM1 DEM0 0FH Digital Volume Control DVOL 7 DVOL6 DVOL5 DVOL4 DVOL 3 DVOL2 DVOL1 DVOL0 10H Power Management 3 I VOLC 0 0 0 0 INR INL PMADR 11H Digital Filter Select 1 GN1 GN0 LPF HPF EQ0 FIL3 0 HPFAD 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ0-efficient 0 E0A7 E0A6 E0A5 E0A4 E0A3 E0A2 E0A1 E0A0 17H EQ0-efficient 1 E0A15 E0A14 E0 A13 E0A12 E0A11 E0A10 E0A9 E0A8 18H EQ0-efficient 2 E0B7 E0B6 E0B5 E0B4 E0B3 E0B2 E0B1 E0B0 19H EQ0-efficient 3 0 0 E0B13 E0B12 E0B11 E0B10 E0B9 E0B8 1AH EQ0-efficient 4 E0C7 E0C6 E0C5 E0C4 E0C3 E0C2 E0C1 E0C0 1BH EQ0-efficient 5 E0C15 E0C14 E0C13 E0C12 E0C11 E0C10 E0C9 E0C8 1CH HPF2 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH HPF2 Co-efficient 1 0 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH HPF2 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH HPF2 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 20H Reserved 0 0 0 0 0 0 0 0 21H Reserved 0 0 0 0 0 0 0 0 22H Reserved 0 0 0 0 0 0 0 0 23H Reserved 0 0 0 0 0 0 0 0 24H BEEP Volume Control 0 0 0 0 0 BPLVL2 BPLVL1 BPLVL0 25H Rch Output Volume Control OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 26H Digital Filter Mode 0 0 0 0 0 PFDAC ADCPF PFSDO 27H Digital MIC 0 MPDMP PMDMR PMDML DCLKE DMPE DCLKP DMIC 28H BEEP/HPF Mode HPFC1 HPFC0 0 0 0 0 0 BPM 29H Noise Suppression 1 0 NSCE NSTHH1 NSTHH0 NSTHL3 NSTHL2 NSTHL1 NSTHL0 2AH Noise Suppression 2 0 0 NATT1 NATT0 0 0 NSGAIN1 NSGAIN0 2BH Noise Suppression 3 NSREF7 NSREF6 NS REF5 NSREF4 NSREF3 NSRE F2 NSREF1 NSREF 0 2CH LPF Co-efficient 0 F2A7 F2A6 F2A5 F2A4 F2A3 F2A2 F2A1 F2A0 2DH LPF Co-efficient 1 0 0 F2A13 F2A12 F2A11 F2A10 F2A9 F2A8 2EH LPF Co-efficient 2 F2B7 F2B6 F2B5 F2B4 F2B3 F2B2 F2B1 F2B0 2FH LPF Co-efficient 3 0 0 F2B13 F2B12 F2B11 F2B10 F2B9 F2B8

[AK4649] MS1023-E-01 2010/08 - 66 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 30H Digital Filter Select 2 0 0 0 EQ5 EQ4 EQ3 EQ2 EQ1 31H Reserved 0 0 0 0 0 0 0 0 32H E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 33H E1 Co-efficient 1 E1A15 E1A14 E1 A13 E1A12 E1A11 E1A10 E1A9 E1A8 34H E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 35H E1 Co-efficient 3 E1B15 E1B14 E1B13 E1B12 E1B11 E1B10 E1B9 E1B8 36H E1 Co-efficient 4 E1C7 E1C6 E1C5 E1C4 E1C3 E1C2 E1C1 E1C0 37H E1 Co-efficient 5 E1C15 E1C14 E1C13 E1C12 E1C11 E1C10 E1C9 E1C8 38H E2 Co-efficient 0 E2A7 E2A6 E2A5 E2A4 E2A3 E2A2 E2A1 E2A0 39H E2 Co-efficient 1 E2A15 E2A14 E2 A13 E2A12 E2A11 E2A10 E2A9 E2A8 3AH E2 Co-efficient 2 E2B7 E2B6 E2B5 E2B4 E2B3 E2B2 E2B1 E2B0 3BH E2 Co-efficient 3 E2B15 E2B14 E2B13 E2B12 E2B11 E2B10 E2B9 E2B8 3CH E2 Co-efficient 4 E2C7 E2C6 E2C5 E2C4 E2C3 E2C2 E2C1 E2C0 3DH E2 Co-efficient 5 E2C15 E2C14 E2C13 E2C12 E2C11 E2C10 E2C9 E2C8 3EH E3 Co-efficient 0 E3A7 E3A6 E3A5 E3A4 E3A3 E3A2 E3A1 E3A0 3FH E3 Co-efficient 1 E3A15 E3A14 E3 A13 E3A12 E3A11 E3A10 E3A9 E3A8 40H E3 Co-efficient 2 E3B7 E3B6 E3B5 E3B4 E3B3 E3B2 E3B1 E3B0 41H E3 Co-efficient 3 E3B15 E3B14 E3B13 E3B12 E3B11 E3B10 E3B9 E3B8 42H E3 Co-efficient 4 E3C7 E3C6 E3C5 E3C4 E3C3 E3C2 E3C1 E3C0 43H E3 Co-efficient 5 E3C15 E3C14 E3C13 E3C12 E3C11 E3C10 E3C9 E3C8 44H E4 Co-efficient 0 E4A7 E4A6 E4A5 E4A4 E4A3 E4A2 E4A1 E4A0 45H E4 Co-efficient 1 E4A15 E4A14 E4 A13 E4A12 E4A11 E4A10 E4A9 E4A8 46H E4 Co-efficient 2 E4B7 E4B6 E4B5 E4B4 E4B3 E4B2 E4B1 E4B0 47H E4 Co-efficient 3 E4B15 E4B14 E4B13 E4B12 E4B11 E4B10 E4B9 E4B8 48H E4 Co-efficient 4 E4C7 E4C6 E4C5 E4C4 E4C3 E4C2 E4C1 E4C0 49H E4 Co-efficient 5 E4C15 E4C14 E4C13 E4C12 E4C11 E4C10 E4C9 E4C8 4AH E5 Co-efficient 0 E5A7 E5A6 E5A5 E5A4 E5A3 E5A2 E5A1 E5A0 4BH E5 Co-efficient 1 E5A15 E5A14 E5A13 E5A12 E5A11 E5A10 E5A9 E5A8 4CH E5 Co-efficient 2 E5B7 E5B6 E5B5 E5B4 E5B3 E5B2 E5B1 E5B0 4DH E5 Co-efficient 3 E5B15 E5B14 E5B13 E5B12 E5B11 E5B10 E5B9 E5B8 4EH E5 Co-efficient 4 E5C7 E5C6 E5C5 E5C4 E5C3 E5C2 E5C1 E5C0 4FH E5 Co-efficient 5 E5C15 E5C14 E5C13 E5C12 E5C11 E5C10 E5C9 E5C8 Note 46. PDN pin = “L” resets the registers to their default values. Note 47. The bits defined as 0 must contain a “0” value. Note 48. Reading address 12H ~ 23H, 2CH ~ 2FH and 32H ~ 7FH is not possible. Note 49. Address 0DH is a read only register. Writing access to 0DH is ignored and does not effect the operation.

[AK4649] MS1023-E-01 2010/08 - 67 - ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 PMPFIL PMVCM PMBP PMSPK PMLO PMDAC 0 PMADL R/W R/W R/W R/W R/ W R/W R/W R R/W Default 0 0 0 0 0 0 0 0 PMADL: MIC-Amp Lch and ADC Lch Power Management 0: Power-down (default) 1: Power-up When the PMADL or PMADR bit is changed from “0 ” to “1”, the initialization cycle (1059/fs=24ms @44.1kHz) starts. After initializing, digital data of the ADC is output. PMDAC: DAC Power Management 0: Power-down (default) 1: Power-up PMLO: Stereo Line Out Power Management 0: Power-down (default) 1: Power-up PMSPK: Speaker-Amp Power Management 0: Power-down (default) 1: Power-up PMBP: MIN Input Power Management 0: Power-down (default) 1: Power-up Both PMDAC and PMBP bits must be set to “1” when DAC is powered-up for playback. After that, BEEPL or BEEPS bit is used to control each path when MIN input is used. PMVCM: VCOM Power Management 0: Power-down (default) 1: Power-up PMPFIL: Programmable Filter Block (HPF2/LPF/FIL3/EQ/5 Band EQ/ALC) Power Management 0: Power down (default) 1: Power up All blocks can be powered-down by writing “0” to the address “00H”, PMPLL, PMDML, PMDMR, DMPE, PMADR and MCKO bits. In this case, register values are maintained. PMVCM bit must be “1” when one of bocks is powered-up. PMVCM bit can only be “0” when the address “00H” and all power management bits (PMPLL, PMMP, PMDML, PMDMR, DMPE, PMADR and MCKO) are “0”. When using either ADC, DAC or Programmable Filter (PMADL bit = “1”, PMADR bit =”1”, PMDAC bit = “1” or PMPFIL bit = “1”), clock must be supplied.

[AK4649] MS1023-E-01 2010/08 - 68 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 0 0 0 0 M/S 0 MCKO PMPLL R/W R R R R R/W R R/W R/W Default 0 0 0 0 0 0 0 0 PMPLL: PLL Power Management 0: EXT Mode and Power-Down (default) 1: PLL Mode and Power-up MCKO: Master Clock Output Enable 0: Disable: MCKO pin = “L” (default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode Select 0: Slave Mode (default) 1: Master Mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Signal Select 1 SPPSN BEEPS DACS DACL MGAIN3 PMMP MGAIN2 MGAIN0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 MGAIN3-0: MIC-Amp Gain Control ( Table 21) MGAIN1 bit is D5 bit of 03H. PMMP: MPWR pin Power Management 0: Power-down: Hi-Z (default) 1: Power-up DACL: Switch Control from DAC to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, DACL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1. DACS: Switch Control from DAC to Speaker-Amp 0: OFF (default) 1: ON When DACS bit is “1”, DAC output signal is input to Speaker-Amp. BEEPS: Switch Control from MIN pin to Speaker-Amp 0: OFF (default) 1: ON When BEEPS bit is “1”, mono signal is input to Speaker-Amp. Set BEEP input mode by BPM bit. SPPSN: Speaker-Amp Power-Save Mode 0: Power-Save Mode (default) 1: Normal Operation When SPPSN bit is “0”, Speaker-Amp is on power-save mode. In this mode, the SPP pin goes to Hi-Z and outputs SVDD/2 voltage. When PMSPK bit = “1”, SPPSN bit is enabled. After the PDN pin is set to “L”, Speaker-Amp is in power-down mode since PMSPK bit is “0”.

[AK4649] MS1023-E-01 2010/08 - 69 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Signal Select 2 0 LOPS MGAIN1 SPKG1 SPKG0 BEEPL LOVL1 LOVL0 R/W R R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LOVL1-0 : Output Stereo Line Gain Select ( Table 53) Default: 00(0dB) BEEPL: Switch Control from MIN pin to Stereo Line Output 0: OFF (default) 1: ON When PMLO bit is “1”, BEEPL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to VSS1. SPKG1-0: Speaker-Amp Output Gain Select ( Table 54) MGAIN1: MIC-Amp Gain Control ( Table 21) LOPS: Stereo Line Ou tput Power-Save Mode 0: Normal Operation (default) 1: Power Save Mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 R/W R/W R/W R/W R/ W R/W R R/W R/W Default 0 0 0 0 0 0 1 0 DIF1-0: Audio Interface Format ( Table 17) Default: “10” (MSB) BCKO: BICK Output Frequency Select at Master Mode ( Table 10) PLL3-0: PLL Reference Clock Select ( Note 35) Default: “0000” (LRCK pin) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Mode Control 2 PS1 PS0 FS3 0 0 FS2 FS1 FS0 R/W R/W R/W R/W R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 FS3-0: Sampling Frequency Select ( Table 5, Table 6) and MCKI Frequency Select (Table 11) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. PS1-0: MCKO Output Frequency Select ( Table 9) Default: “00”(256fs)

[AK4649] MS1023-E-01 2010/08 - 70 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Timer Select ADRST WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ADRST: ADC Initialization Cycle Setting 0: 1059/fs (default) 1: 267/fs WTM2-0: ALC Recovery Waiting Period ( Table 28) A period of recovery operation when any limiter operation does not occur during ALC operation Default is “000” (128/fs). ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 27) In case of the μP WRITE operation or ALC1 recovery operation, the volume is changed at zero crossing or timeout. RFST1-0: ALC First recovery Speed (Table 32) Default: “00”(4times) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H ALC Mode Control 1 LFST ALC2 ALC1 ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 25) Default: “00” LMTH1 bit is D6 bit of 0BH. RGAIN1-0: ALC Recovery GAIN Step (Table 29) Default: “00” RGAIN1 bit is D7 bit of 0BH. LMAT1-0: ALC Limiter ATT Step (Table 26) Default: “00” ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable ALC1: ALC Enable for Recording 0: Recording ALC Disable (default) 1: Recording ALC Enable ALC2: ALC Enable for Playback 0: Playback ALC Disable (default) 1: Playback ALC Enable LFST: ALC Limiter operation when the output level exceed FS(Full-scale) level. 0: The volume is changed at zero crossing or zero crossing time out. (default) 1: When output of ALC is larger than FS, OVOL value is changed immediately (1/fs).

[AK4649] MS1023-E-01 2010/08 - 71 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H ALC Mode Control 2 IREF7 IREF6 I REF5 IREF4 IREF3 IREF2 IREF1 IREF0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 IREF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (Table 30) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Lch Input Volume Control IVL7 IV L6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 1 1 0 0 0 0 1 IVL7-0, IVR7-0: IVR7-0: Input Digital Volume; 0.375dB step, 242 Level ( Table 41) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Lch Output Volume Control OVL7 OVL6 OVL5 OVL4 OVL3 OVL2 OVL1 OVL0 25H Rch Output Volume Control OVR7 OVR6 OVR5 OVR4 OVR3 OVR2 OVR1 OVR0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 1 0 0 1 0 0 0 1 OVL7-0, OVR7-0: Output Digital Volume ( Table 42) Default: “91H” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH ALC Mode Control 3 RGAIN1 LMTH1 OREF5 OREF4 OREF3 OREF2 OREF1 OREF0 R/W R/W R/W R/W R/ W R/W R/W R/W R/W Default 0 0 1 0 1 0 0 0 OREF5-0: Reference value at Playback ALC Recovery Operation. 0.375dB step, 50 Level (Table 31) Default: “28H” (+6.0dB) LMTH1: ALC Limiter Detection Level / Recovery Counter Reset Level (Table 25) RGAIN1: ALC Recovery GAIN Step (Table 29) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH ALC Volume VOL7 VOL6 VOL5 VOL4 VOL3 VOL2 VOL1 VOL0 R/W R R R R R R R R Default - - - - - - - - VOL7-0: Current ALC volume value; 0.375dB step, 242 Level. Read operation only ( Table 33)

[AK4649] MS1023-E-01 2010/08 - 72 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Mode Control 3 READ 0 SMUTE OVOLC DATT1 DATT0 DEM1 DEM0 R/W R/W R R/W R/W R/W R/W R/W R/W Default 0 0 0 1 0 0 0 1 DEM1-0: De-emphasis Frequency Select ( Table 47) Default: “01” (OFF) DATT1-0: Output Digital Volume2; 6dB step, 4 Level (Table 43) Default: “00H” (0.0dB) OVOLC: Output Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When OVOLC bit = “1”, OVL7-0 bits control both Lch and Rch volume level, while register values of OVL7-0 bits are not written to OVR7-0 bits. When OVOL C bit = “0”, OVL7-0 bits control Lch level and OVR7-0 bits control Rch level, respectively. SMUTE: Soft Mute Control 0: Normal Operation (default) 1: DAC outputs soft-muted READ: Read function Enable 0: Disable (default) 1 : E n a b l e Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Digital Volume Control DVOL 7 DVOL6 DVOL5 DVOL4 DVOL 3 DVOL2 DVOL1 DVOL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 DVOL7-0: Output Digital Volume Control 3; Linear step (Table 43, Table 45) Default: “FFH” (0dB)

[AK4649] MS1023-E-01 2010/08 - 73 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H Power Management 3 I VOLC 0 0 0 0 INR INL PMADR R/W R/W R R R R R/W R/W R/W Default 1 0 0 0 0 0 0 0 PMADR: MIC-Amp Rch, ADC Rch Power Management 0: Power down (default) 1: Power up INL: ADC Lch Input Source Select 0: LIN1 pin (default) 1: LIN2 pin INR: ADC Rch Input Source Select 0: RIN1 pin (default) 1: RIN2 pin IVOLC: Input Digital Volume Control Mode Select 0: Independent 1: Dependent (default) When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0 bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits control Rch level, respectively.

[AK4649] MS1023-E-01 2010/08 - 74 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H Digital Filter Select 1 GN1 GN0 LPF HPF EQ0 FIL3 0 HPFAD R/W R/W R/W R/W R/ W R/W R/W R R/W Default 0 0 0 0 0 0 0 1 HPFAD: HPF1 Control of ADC 0: OFF 1: ON (default) When HPFAD bit is “1”, the settings of HPFC1-0 bits are enabled. When HPFAD bit is “0”, HPFAD block is through (0dB). When PMADL bit = “1” or PMADR bit = “1”, set HPFAD bit to “1”. FIL3: FIL3 (Stereo Separation Emphasis Filter) Coefficient Setting Enable 0: OFF (default) 1: ON When FIL3 bit is “1”, the settings of F3A13-0 and F3B13-0 bits are enabled. EQ0: EQ0 (Gain Compensation Filter) Coefficient Setting Enable 0: OFF (default) 1: ON When EQ0 bit is “1”, the settings of E0A15-0, E0B13-0 and E-C15-0 bits are enabled. When EQ0 bit is “0”, EQ block is through (0dB). HPF: HPF2 Coefficient Setting Enable 0: OFF (default) 1: ON When HPF bit is “1”, the settings of F1A13-0 and F1B13-0 bits are enabled. When HPF bit is “0”, HPF block is through (0dB). LPF: LPF Coefficient Setting Enable 0: OFF (default) 1: ON When LPF bit is “1”, the settings of F2A13-0 and F2B13-0 bits are enabled. When LPF bit is “0”, LPF block is through (0dB). GN1-0: Gain Select at GAIN block ( Table 24) Default: “00” (0dB)

[AK4649] MS1023-E-01 2010/08 - 75 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ0-efficient 0 E0A7 E0A6 E0A5 E0A4 E0A3 E0A2 E0A1 E0A0 17H EQ0-efficient 1 E0A15 E0A14 E0A13 E0A12 E0A11 E0A10 E0A9 E0A8 18H EQ0-efficient 2 E0B7 E0B6 E0B5 E0B4 E0B3 E0B2 E0B1 E0B0 19H EQ0-efficient 3 0 0 E0B13 E0B12 E0B11 E0B10 E0B9 E0B8 1AH EQ0-efficient 4 E0C7 E0C6 E0C5 E0C4 E0C3 E0C2 E0C1 E0C0 1BH EQ0-efficient 5 E0C15 E0C14 E0C13 E0C12 E0C11 E0C10 E0C9 E0C8 R/W W W W W W W W W Default 0 0 0 0 0 0 0 0 F3A13-0, F3B13-0: FIL3 (Stereo Separation Emphasis Filter) Coefficient (14bit x 2) Default: “0000H” F3AS: FIL3 (Stereo Separation Emphasis Filter) Select 0: HPF (default) 1: LPF E0A15-0, E0B13-0, E0C15-C0: EQ (Gain Compensation Filter) Coefficient (16bit x 2 + 14bit x 1) Default: “0000H” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1CH HPF Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH HPF Co-efficient 1 0 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH HPF Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH HPF Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 R/W W W W W W W W W Default F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD F1A13-0, F1B13-0: HPF2 Coefficient (14bit x 2) Default: F1A13-0 bits = 0x1FA9, F1B13-0 bits = 0x20AD fc = 150Hz@fs=44.1kHz Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 24H BEEP Volume Control 0 0 0 0 0 BPLVL2 BPLVL1 BPLVL0 R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 0 0 BPLVL2-0 : BEEP Sound Output Level (Table 51) Default: “0H”: 0dB

[AK4649] MS1023-E-01 2010/08 - 76 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 26H Digital Filter Mode 0 0 0 0 0 PFDAC ADCPF PFSDO R/W R R R R R R/W R/W R/W Default 0 0 0 0 0 0 1 1 PFSDO: SDTO Output Signal Select 0: ADC (+ 1st HPF) Output 1: Programmable Filter / ALC Output (default) ADCPF: Programmable Filter / ALC Input Signal Select 0: SDTI 1: ADC Output (default) PFDAC: DAC Input Signal Select 0: SDTI (default) 1: Programmable Filter / ALC Output Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 27H Digital MIC 0 MPDMP PMDMR PMDML DCLKE DMPE DCLKP DMIC R/W R R/W R/W R/W R/ W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DMIC: Digital Microphone Connection Select 0: Analog Microphone (default) 1: Digital Microphone DCLKP: Data Latching Edge Select 0: Lch data is latched on the DMCLK rising edge (“ ↑”). (default) 1: Lch data is latched on the DMCLK falling edge (“ ↓”). DMPE: Digital Microphone Power Supply 0: Externally (the same supply as AVDD) (default) 1: DMP pin DCLKE: DMCLK pin Output Clock Control 0: “L” Output (default) 1: 64fs Output PMDML/R: Input Signal Select with Digital Microphone ( Table 20) Default: “00” ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input (DMIC bit = “1”, INL/R bits = “00”, “01” or “10”). MPDMP: Analog / Digital Microphone Power Supply Pin Select 0: Power Supply for Analog Microphone: MPWR pin (default) 1: Power Supply for Digital Microphone: DMP pin

[AK4649] MS1023-E-01 2010/08 - 77 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 28H BEEP/HPF Mode HPFC1 HPFC0 0 0 0 0 0 BPM R/W R/W R\\/W R R R R R R/W Default 0 0 0 0 0 0 0 0 BPM: BEEP Mode Setting (Table 48) Default: “0”: External Resistance Mode HPFC1-0: Cut-off Frequency Setting of HPF1 (ADC) (Table 46) Default: “00” (3.4Hz @ fs = 44.1kHz) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 29H Noise Suppression 1 0 NSCE NSTHH1 NSTHH0 NSTHL3 NSTHL2 NSTHL1 NSTHL0 R/W R R/W R/W R/W R/ W R/W R/W R/W Default 0 0 0 1 0 0 0 0 NSTHL3-0: Noise Suppression Threshold Low Level Setting (Table 36) Default: “0000” (-81dBFS) NSTHH1-0: Noise Suppression Threshold High Level Setting (Table 38) Default: “01” (NSTHL3-0 bits + 6dB) NSCE: Noise Suppression Enable 0: Disable (default) 1 : E n a b l e Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 2AH Noise Suppression 2 0 0 NATT1 NATT0 0 0 NSGAIN1 NSGAIN0 R/W R R R/W R/W R R R/W R/W Default 0 0 0 1 0 0 0 1 NSGAIN1-0: ALC First Recovery Speed Setting after Noise Suppression (Table 39) Default: “01” (8 step) NATT1-0: Noise Attenuate Step Setting (Table 37) Default: “01” (1/2 step) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 2BH Noise Suppression 3 NSREF7 NSREF6 NS REF5 NSREF4 NSREF3 NS REF2 NSREF1 NSREF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 1 0 0 0 1 NSREF7-0: Reference Level Setting at Noise Suppression 0.375dB step, 242 Level (Table 40) Default: “91H” (0dB)

[AK4649] MS1023-E-01 2010/08 - 78 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 2CH LPF Co-efficient 0 F2A7 F2A6 F2A5 F2A4 F2A3 F2A2 F2A1 F2A0 2DH LPF Co-efficient 1 0 0 F2A13 F2A12 F2A11 F2A10 F2A9 F2A8 2EH LPF Co-efficient 2 F2B7 F2B6 F2B5 F2B4 F2B3 F2B2 F2B1 F2B0 2FH LPF Co-efficient 3 0 0 F2B13 F2B12 F2B11 F2B10 F2B9 F2B8 R/W W W W W W W W W Default 0 0 0 0 0 0 0 0 F2A13-0, F2B13-0: LPF Coefficient (14bit x 2) Default: “0000H” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 30H Digital Filter Select 2 0 0 0 EQ5 EQ4 EQ3 EQ2 EQ1 R/W R R R R/W R/ W R/W R/W R/W Default 0 0 0 0 0 0 0 0 EQ1: Equalizer 1 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ1 bit is “1”, the settings of E1A15-0, E1B15-0 and E1C15-0 bits are enabled. When EQ1 bit is “0”, EQ1 block is through (0dB). EQ2: Equalizer 2 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ2 bit is “1”, the settings of E2A15-0, E2B15-0 and E2C15-0 bits are enabled. When EQ2 bit is “0”, EQ2 block is through (0dB). EQ3: Equalizer 3 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ3 bit is “1”, the settings of E3A15-0, E3B15-0 and E3C15-0 bits are enabled. When EQ3 bit is “0”, EQ3 block is through (0dB). EQ4: Equalizer 4 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ4 bit is “1”, the settings of E4A15-0, E4B15-0 and E4C15-0 bits are enabled. When EQ4 bit is “0”, EQ4 block is through (0dB). EQ5: Equalizer 5 Coefficient Setting Enable 0: Disable (default) 1: Enable When EQ5 bit is “1”, the settings of E5A15-0, E5B15-0 and E5C15-0 bits are enabled. When EQ5 bit is “0”, EQ5 block is through (0dB).

[AK4649] MS1023-E-01 2010/08 - 79 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 32H E1 Co-efficient 0 E1A7 E1A6 E1A5 E1A4 E1A3 E1A2 E1A1 E1A0 33H E1 Co-efficient 1 E1A15 E1A14 E1A13 E1A12 E1A11 E1A10 E1A9 E1A8 34H E1 Co-efficient 2 E1B7 E1B6 E1B5 E1B4 E1B3 E1B2 E1B1 E1B0 35H E1 Co-efficient 3 E1B15 E1B14 E1B13 E1B12 E1B11 E1B10 E1B9 E1B8 36H E1 Co-efficient 4 E1C7 E1C6 E1C5 E1C4 E1C3 E1C2 E1C1 E1C0 37H E1 Co-efficient 5 E1C15 E1C14 E1C13 E1C12 E1C11 E1C10 E1C9 E1C8 38H E2 Co-efficient 0 E2A7 E2A6 E2A5 E2A4 E2A3 E2A2 E2A1 E2A0 39H E2 Co-efficient 1 E2A15 E2A14 E2A13 E2A12 E2A11 E2A10 E2A9 E2A8 3AH E2 Co-efficient 2 E2B7 E2B6 E2B5 E2B4 E2B3 E2B2 E2B1 E2B0 3BH E2 Co-efficient 3 E2B15 E2B14 E2B13 E2B12 E2B11 E2B10 E2B9 E2B8 3CH E2 Co-efficient 4 E2C7 E2C6 E2C5 E2C4 E2C3 E2C2 E2C1 E2C0 3DH E2 Co-efficient 5 E2C15 E2C14 E2C13 E2C12 E2C11 E2C10 E2C9 E2C8 3EH E3 Co-efficient 0 E3A7 E3A6 E3A5 E3A4 E3A3 E3A2 E3A1 E3A0 3FH E3 Co-efficient 1 E3A15 E3A14 E3A13 E3A12 E3A11 E3A10 E3A9 E3A8 40H E3 Co-efficient 2 E3B7 E3B6 E3B5 E3B4 E3B3 E3B2 E3B1 E3B0 41H E3 Co-efficient 3 E3B15 E3B14 E3B13 E3B12 E3B11 E3B10 E3B9 E3B8 42H E3 Co-efficient 4 E3C7 E3C6 E3C5 E3C4 E3C3 E3C2 E3C1 E3C0 43H E3 Co-efficient 5 E3C15 E3C14 E3C13 E3C12 E3C11 E3C10 E3C9 E3C8 44H E4 Co-efficient 0 E4A7 E4A6 E4A5 E4A4 E4A3 E4A2 E4A1 E4A0 45H E4 Co-efficient 1 E4A15 E4A14 E4A13 E4A12 E4A11 E4A10 E4A9 E4A8 46H E4 Co-efficient 2 E4B7 E4B6 E4B5 E4B4 E4B3 E4B2 E4B1 E4B0 47H E4 Co-efficient 3 E4B15 E4B14 E4B13 E4B12 E4B11 E4B10 E4B9 E4B8 48H E4 Co-efficient 4 E4C7 E4C6 E4C5 E4C4 E4C3 E4C2 E4C1 E4C0 49H E4 Co-efficient 5 E4C15 E4C14 E4C13 E4C12 E4C11 E4C10 E4C9 E4C8 4AH E5 Co-efficient 0 E5A7 E5A6 E5A5 E5A4 E5A3 E5A2 E5A1 E5A0 4BH E5 Co-efficient 1 E5A15 E5A14 E5A13 E5A12 E5A11 E5A10 E5A9 E5A8 4CH E5 Co-efficient 2 E5B7 E5B6 E5B5 E5B4 E5B3 E5B2 E5B1 E5B0 4DH E5 Co-efficient 3 E5B15 E5B14 E5B13 E5B12 E5B11 E5B10 E5B9 E5B8 4EH E5 Co-efficient 4 E5C7 E5C6 E5C5 E5C4 E5C3 E5C2 E5C1 E5C0 4FH E5 Co-efficient 5 E5C15 E5C14 E5C13 E5C12 E5C11 E5C10 E5C9 E5C8 R/W W W W W W W W W Default 0 0 0 0 0 0 0 0 E1A15-0, E1B15-0, E1C15-0: Equalizer 1 Coefficient (16bit x3) Default: “0000H” E2A15-0, E2B15-0, E2C15-0: Equalizer 2 Coefficient (16bit x3) Default: “0000H” E3A15-0, E3B15-0, E3C15-0: Equalizer 3 Coefficient (16bit x3) Default: “0000H” E4A15-0, E4B15-0, E4C15-0: Equalizer 4 Coefficient (16bit x3) Default: “0000H” E5A15-0, E5B15-0, E5C15-0: Equalizer 5 Coefficient (16bit x3) Default: “0000H”

[AK4649] MS1023-E-01 2010/08 - 81 - 1. Grounding and Power Supply Decoupling The AK4649 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the power-up sequence is not critical. VSS1, VSS2 and VSS3 of the AK4649 must be connected to the analog ground plane. System analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors must be as near to the AK4649 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2μF electrolytic capacitor in parallel with a 0.1μF ceramic capacitor nust be attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, must be kept away from the VCOM pin in order to avoid unwanted coupling into the AK4649. 3. Analog Inputs The MIC and Line inputs are single-ended. The inputs signal range scales with nominally at typ. 0.07 x AVDD Vpp (@ MGAIN = +20dB) and typ. 0.7 x AVDD Vpp (@ MGAIN = 0dB), centered around the internal common voltage (typ. 0.5 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = 1/ (2πRC). The AK4649 can accept input voltages from VSS1 to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit). Stereo Line

When ADC, DAC, Digital MIC or Programmable Filter is powered-up, the clocks must be supplied. Figure 55. Clock Set Up Sequence (1) “L” time of 150ns or more is needed to reset the AK4649. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits must be set during this period. VCOM must first be powered-up before the other block operates. (7) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”. (8) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.

1. PLL Slave Mode (LRCK or BICK pin)

Figure 56. Clock Set Up Sequence (2) “L” time of 150ns or more is needed to reset the AK4649. (2) DIF1-0, FS3-0 and PLL3-0 bits must be set during this period. VCOM must first be powered up before the other block operates. when BICK is a PLL reference clock. (5) Normal operation stats after that the PLL is locked.

1. PLL Slave Mode (MCKI pin)

Figure 57. Clock Set Up Sequence (3) “L” time of 150ns or more is needed to reset the AK4649. (2) DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits must be set during this period. VCOM must first be powered up before the other block operates. (5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied. PLL lock time is 10ms (max). (6) The normal clock is output from MCKO after PLL is locked. (7) The invalid frequency is output from MCKO during this period. (8) BICK and LRCK clocks must be synchronized with MCKO clock.

Figure 58. Clock Set Up Sequence (4) “L” time of 150ns or more is needed to reset the AK4649. (2) DIF1-0 and FS1-0 bits must be set during this period. VCOM must first be powered up before the other block operates. (4) Normal operation starts after the MCKI, LRCK and BICK are supplied.

Figure 59. MIC Input Recording Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. must be powered-up in consideration of PLL lock time after a sampling frequency is changed.

0 X 11 XXXX0 X 00 XXXX 0 X 00 XXXX

Figure 60. Digital MIC Input Recording Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. Filter must be powered-up in consideration of PLL lock time after a sampling frequency is changed. during initialization cycle. After the ALC1 bit is set to “1”, the ALC1 operation starts from IVOL value of (4).

Figure 61. Speaker-Amp Output Sequence At first, clocks must be supplied according to “Clock Set Up” sequence. powered-up in consideration of PLL lock time after a sampling frequency is changed. (7) Set up the output digital volume (Addr = 0AH, 0DH). bit = “0”, it could be digital volume control.

[AK4649] MS1023-E-01 2010/08 - 89 - (10) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1” “(9)” time depends on the time constant of external resistor and capacitor connected to the MIN pin. If Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur. (11) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0” (12) Disable the path of “DAC → SPK-Amp”: DACS bit = “1” → “0” (13) Power down DAC, MIN-Amp Programmable Filter and Speaker: PMDAC = PMPFIL = PMBP = PMSPK bits = “1” → “0”

Figure 62. “MIN-Amp Æ Speaker-Amp” Output Sequence The clocks can be stopped when only MIN-Amp and Speaker-Amp are operating. Speaker-Amp output is enabled before input of MIN-Amp becomes stable, pop noise may occur.

Figure 63. Stereo Lineout Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. be powered-up in consideration of PLL lock time after the sampling frequency is changed. voltage is 300ms (max) at C=1μF and RL=10kΩ. LOUT and ROUT pins fall down to 1% VCOM voltage. Fall time is 300ms (max) at C=1μF and RL=10kΩ. LOPS bit must be set to “0” after LOUT and ROUT pins fall down.

[AK4649] MS1023-E-01 2010/08 - 94 - PACKAGE 0.5 φ 0.30 ± 0.05 0.08 S S φ 0.05 ABS A M B 0.625 ± 0.02 0.25 ± 0.0 5 E DC B A A B C D E Top View Bottom View 4649 XXXX 3.01 ± 0.05 (0.38) (0.505) 3.26 ± 0.05 ■ Material & Lead finish Package molding compound: Epoxy resin, Halogen (bromine, chlorine) free Solder ball material: SnAgCu

[AK4649] MS1023-E-01 2010/08 - 95 - MARKING 4649 XXXX A “4649”: Market Number XXXX: Date code (4 digit)

• : Pin #1 indication

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents 08/10/24 00 First Edition 10/08/19 01 Specification Addition

07 RECOMMENDED OPERATING CONDITIONS

AVDD – SVDD was added: 1.0V (max) Error Correction 43 Transfer function was changed.

[AK4649] MS1023-E-01 2010/08 - 96 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.