AK4645EN AKM | Alldatasheet
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ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 1 - ཁ AK4645ϚΠΫΞϯϓ͓ΑͼϔουϑΥϯΞϯϓΛଂͨ͠εςϨΦCODECͰ͢ɻAK4645Ξφϩ ͷ32pin QFN༻ɺैདྷ ͠·͢ɻ ಛ 1. ೳ
- 4εςϨΦೖྗηϨΫλ
- εςϨΦϚΠΫೖྗ(ಈ or γϯάϧΤϯυೖྗ)
- εςϨΦϥΠϯೖྗ
- ϚΠΫ༻ήΠϯΞϯϓଂ (+32dB/+26dB/+20dB or 0dB)
- Digital ALC (Automatic Level Control) ճ࿏ଂ (+36dB ∼ −54dB, 0.375dB Step, Mute)
- ADCಛੑ: S/(N+D): 83dB, DR, S/N: 86dB (MIC-Amp=+20dB) S/(N+D): 88dB, DR, S/N: 95dB (MIC-Amp=0dB)
- ෩ΓԻϑΟϧλ
- ௐճ࿏
- Programmable EQ 2. ೳ
- σΟδλϧσΟΤϯϑΝγεϑΟϧλ (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
- όεϒʔετ
- ιϑτϛϡʔτ
- σΟδλϧϘϦϡʔϜଂ (+12dB ∼ −115.0dB, 0.5dB Step, Mute)
- Digital ALC (Automatic Level Control) ճ࿏ଂ (+36dB ∼ −54dB, 0.375dB Step, Mute)
- ௐճ࿏
- Programmable EQ
- εςϨΦϥΠϯग़ྗ - ಛੑ: S/(N+D): 88dB, S/N: 92dB
- εςϨΦϔουϑΥϯΞϯϓଂ - HP-AMPಛੑ: S/(N+D): 70dB@7.5mW, S/N: 90dB - ग़ྗ: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V) - ݯON/OFFΫϦοΫϊΠζϑϦʔ
- ΞφϩάϛΩγϯά: 4εςϨΦೖྗ 3. ೳ 4. ϚελΫϩοΫ: (1) PLLϞʔυ
- प: 11.2896MHz, 12MHz, 12.288MHz, 13M Hz, 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz (MCKI pin) 1fs (LRCK pin) 32fs or 64fs (BICK pin) (2) ֎෦ΫϩοΫϞʔυ
- प: 256fs, 512fs or 1024fs (MCKI pin) 5. ϚελΫϩοΫग़ྗप: 32fs/64fs/128fs/256fs 6. αϯϓϦϯάप:
- PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (BICK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz Stereo CODEC with MIC/HP-AMP AK4645
- PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
- EXT Master/Slave Mode: 7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs) 7. γϦΞϧµPΠϯλϑΣʔε: 3ઢγϦΞϧ, I2Cόε (Ver 1.0, 400kHzϞʔυ) 8. ϚελʗεϨʔϒϞʔυ 9. ΦʔσΟΦΠϯλϑΣʔεϑΥʔϚοτ: MSB First, 2’s complement
- ADC : 16bitΊ, I2S, DSP Mode
- DAC : 16bitΊ, 16bitΊ, 16-24bit I2S, DSP Mode 11. ిѹ:
- AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
- TVDD (Digital I/O): 1.6 ∼ 3.6V (typ. 3.3V) 12. ύοέʔδ : 32pin QFN (5mm x 5mm, 0.5mm pitch) 13. AK4644ޓ ϒϩοΫਤ MIC Power Supply MIC-Amp A/D Wind-Noise Reduction Stereo SeparationHPF PMADL or PMMICL PMADR or PMMICR PMADL or PMADR Audio I/F D/A DATT SMUTE PMDAC PMHPL PMHPR Internal MIC External MIC Line In Stereo Line Out Headphone ALC Bass Boost PLL PMMIN PMPLL MPWR LIN1 RIN1 LIN2 RIN2 HPL HPR MUTET HVDD HVSS AVDD AVSS VCOM DVDD PDN BICK LRCK SDTO SDTI MCKO MCKI VCOC PMLO LOUT ROUT ALC TVDD Stereo Separation HPF LIN3/MIN RIN3/VCOC PMMP PMAINR2 PMAINL2 PMAINR4 Line In LIN4 RIN4 PMAINL3 PMAINR3 PMAINL4 Control Register CSN CCLK CDTI I2C
Figure 1. ϒϩοΫਤ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 3 - ΦʔμϦϯάΨΠυ AK4645EN −30 ∼ +85°C 32pin QFN (0.5mm pitch) AKD4645 AK4645 ༻ධՁϘʔυ ϐϯஔ LIN4 / IN4+ ROUT / LON LOUT / LOP MIN / LIN3 RIN2 / IN2− LIN2 / IN2+ LIN1 / IN1− RIN1 / IN1+ RIN4 / IN4− MUTET HPL HPR HVDD HVSS MCKO MCKI MPWR VCOM AVSS AVDD VCOC / RIN3 I2C PDN CSN / CAD0 TVDD DVDD BICK LRCK SDTO SDTI CDTI / SDA CCLK / SCL AK4645EN Top View AK4643/44ੑ 1. Function Function AK4643 AK4644 AK4645 Digital I/O of µP I/F 2.6 to 3.6V Å 1.6 to 3.6V Analog Mixing for Playback 3 Stereo Å 4 Stereo Input Selector for Recording 3 Stereo Å 4 Stereo HP-Amp Hi-Z Setting for wired OR No Å Yes PLL 11.2896/12/12.288/ 13.5/24/27MHz Å 11.2896/12/12.288/13/ Speaker-Amp Yes No Å Receiver-Amp Yes Å No
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 4 - 2. Pin Pin# AK4643 AK4644 AK4645
16 DVSS Å TVDD
19 SPN TEST1 HVSS
20 SPP TEST2 HVDD
21 HVDD Å HPR
22 HVSS Å HPL
23 HPR Å MUTET
24 HPL Å RIN4 / IN4−
25 MUTET Å LIN4 / IN4+
26 ROUT/RCN Å ROUT/LON
27 LOUT/RCP Å LOUT/LOP
- Ϩδελ(AK4644) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 PMVCM PMMIN 0 PMLO PMDAC 0 PMADL 01H Power Management 2 HPZ HPMTN PMHPL PMHPR M/S 0 MCKO PMPLL 02H Signal Select 1 0 0 0 DACL 0 PMMP 0 MGAIN0 03H Signal Select 2 LOVL LOPS MGAIN1 0 0 MINL 0 0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 05H Mode Control 2 PS1 PS0 FS3 MSBS BCKP FS2 FS1 FS0 06H Timer Select DVTM WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0 07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 VBAT 0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 0DH Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 0EH Mode Control 3 0 LOOP SM UTE DVOLC BST1 BST0 DEM1 DEM0 0FH Mode Control 4 0 0 0 0 IVOLC HPM MINH DACH 10H Power Management 3 INR1 INL1 HPG MDIF2 MDIF1 INR0 INL0 PMADR 11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ Co-efficient 0 EQA7 EQA6 E QA5 EQA4 EQA3 EQA2 EQA1 EQA0 17H EQ Co-efficient 1 EQA15 EQA1 4 EQA13 EQA12 EQA11 EQA10 EQA9 EQA8 18H EQ Co-efficient 2 EQB7 EQB6 EQ B5 EQB4 EQB3 EQB2 EQB1 EQB0 19H EQ Co-efficient 3 0 0 EQB13 EQB12 EQB11 EQB10 EQB9 EQB8 1AH EQ Co-efficient 4 EQC7 EQC6 EQ C5 EQC4 EQC3 EQC2 EQC1 EQC0 1BH EQ Co-efficient 5 EQC15 EQC14 E QC13 EQC12 EQC11 EQC10 EQC9 EQC8 1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 20H Power Management 4 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 21H Mode Control 5 0 0 MICR3 MICL3 L4DIF MIX AIN3 LODIF 22H Lineout Mixing Select LOM LOM3 RINR4 LINL4 RINR3 LINL3 RINR2 LINL2 23H HP Mixing Select 0 HPM3 RINH4 LINH4 RINH3 LINH3 RINH2 LINH2 24H Reserved 0 0 0 0 0 0 0 0 AK4645ͰՃ͞ΕͨϏοτ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 5 - No. Pin Name I/O Function
1 MPWR O ϐϯ
2 VCOM O ίϞϯిѹग़ྗϐϯ, 0.45 x AVDD
3 AVSS - Ξφϩάάϥϯυϐϯ
4 AVDD - ϐϯ
VCOC O PLLͷϧʔϓϑΟϧλ༻ग़ྗϐϯ(AIN3 bit = “0”: PLL༻Մೳ) AVSSͱίϯσϯαΛγϦʔζଓͯ͠Լ͍͞ɻ 5 RIN3 I Rch Ξφϩάೖྗ3ϐϯ(AIN3 bit = “1”: PLL༻ෆՄ)
6 I2C I ίϯτϩʔϧϞʔυબϐϯ
“H”: I2Cόε, “L”: 3γϦΞϧ
7 PDN I
ύϫʔμϯϞʔυϐϯ “H”: ύϫʔΞοϓ “L”: Խ CSN I νοϓηϨΫτϐϯ (I2C pin = “L”: 3ઢγϦΞϧϞʔυ) 8 CAD0 I νοϓΞυϨε0ϐϯ (I2C pin = “H” : I2CόεϞʔυ) CCLK I ίϯτϩʔϧΫϩοΫೖྗϐϯ (I2C pin = “L”: 3ઢγϦΞϧϞʔυ) 9 SCL I ίϯτϩʔϧΫϩοΫೖྗϐϯ (I2C pin = “H”: I2CόεϞʔυ) CDTI I ίϯτϩʔϧσʔλೖྗϐϯ (I2C pin = “L”: 3ઢγϦΞϧϞʔυ) 10 SDA I/O ίϯτϩʔϧσʔλೖग़ྗϐϯ (I2C pin = “H”: I2CόεϞʔυ)
11 SDTI I ΦʔσΟΦγϦΞϧσʔλೖྗϐϯ
12 SDTO O ΦʔσΟΦγϦΞϧσʔλग़ྗϐϯ
13 LRCK I/O ೖग़ྗνϟωϧΫϩοΫϐϯ
14 BICK I/O ΦʔσΟΦγϦΞϧΫϩοΫϐϯ
15 DVDD - ϐϯ
16 TVDD - σΟδλϧI/Oϐϯ
17 MCKI I ֎෦ϚελΫϩοΫೖྗϐϯ
18 MCKO O ϚελΫϩοΫग़ྗϐϯ
19 HVSS - ϔουϑΥϯΞϯϓάϥϯυϐϯ
20 HVDD - ϐϯ
21 HPR O Rch ϔουϑΥϯΞϯϓग़ྗϐϯ
22 HPL O Lch ϔουϑΥϯΞϯϓग़ྗϐϯ
23 MUTET O ఆίϯτϩʔϧϐϯ
RIN4 I Rch Ξφϩάೖྗ4ϐϯ(L4DIF bit = “0”: γϯάϧΤϯυೖྗ) 24 IN4− I సϥΠϯೖྗ4ϐϯ(L4DIF bit = “1”: ಈೖྗ) LIN4 I Lch Ξφϩάೖྗ2ϐϯ(L4DIF bit = “0”: γϯάϧΤϯυೖྗ) 25 IN4+ I ඇసϥΠϯೖྗ4ϐϯ(L4DIF bit = “1”: ಈೖྗ) ROUT O Rch ϥΠϯग़ྗϐϯ(LODIF bit = “0”: γϯάϧΤϯυεςϨΦग़ྗ) 26 LON O సϥΠϯग़ྗϐϯ(LODIF bit = “1”: ಈϞϊϥϧग़ྗ) LOUT O Lch ϥΠϯग़ྗϐϯ(LODIF bit = “0”: γϯάϧΤϯυεςϨΦग़ྗ) 27 LOP O ඇసϥΠϯग़ྗϐϯ(LODIF bit = “1”: ಈϞϊϥϧग़ྗ) MIN I ϞϊϥϧΞφϩάೖྗϐϯ(AIN3 bit = “0”: PLL༻Մೳ) 28 LIN3 I Lch Ξφϩάೖྗ3ϐϯ (AIN3 bit = “1”: PLL༻ෆՄ) RIN2 I Rch Ξφϩάೖྗ2ϐϯ(MDIF2 bit = “0”: γϯάϧΤϯυೖྗ) 29 IN2− I ϚΠΫసೖྗ2ϐϯ(MDIF2 bit = “1”: ಈೖྗ) LIN2 I Lch Ξφϩάೖྗ2ϐϯ(MDIF2 bit = “0”: γϯάϧΤϯυೖྗ) 30 IN2+ I ϚΠΫඇసೖྗ2ϐϯ(MDIF2 bit = “1”: ಈೖྗ) LIN1 I Lch Ξφϩάೖྗ1ϐϯ(MDIF1 bit = “0”: γϯάϧΤϯυೖྗ) 31 IN1− I ϚΠΫసೖྗ1ϐϯ(MDIF1 bit = “1”: ಈೖྗ) RIN1 I Rch Ξφϩάೖྗ1ϐϯ(MDIF1 bit = “0”: γϯάϧΤϯυೖྗ) 32 IN1+ I ϚΠΫඇసೖྗ1ϐϯ(MDIF1 bit = “1”: ಈೖྗ) Note 1. Ξφϩάೖྗϐϯ (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3, LIN4, RIN4)Ҏ֎ͷͯ͢ͷೖྗϐϯϑ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 6 - ϐϯ໊ ઃఆ Analog MPWR, VCOC/RIN3, HPR, HPL, MUTET, RIN4/IN4−, LIN4/IN4+, ROUT/LON, LOUT/LOP, MIN/LIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ Φʔϓϯ MCKO Φʔϓϯ Digital MCKI HVSSʹଓ AVSS, HVSS=0V; Note 3) Parameter Symbol Min max Units Power Supplies: Analog AVDD −0.3 6.0 V Digital DVDD −0.3 6.0 V Digital I/O TVDD −0.3 6.0 V Headphone-Amp HVDD −0.3 6.0 V |AVSS – HVSS| (Note 4) ∆GND2 - 0.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 5) VINA −0.3 AVDD+0.3 V Digital Input Voltage (Note 6) VIND −0.3 TVDD+0.3 V Ambient Temperature (powered applied) Ta −30 85 °C Storage Temperature Tstg −65 150 °C Note 4. AVSSͱHVSSಉ͡Ξφϩάάϥϯυʹଓͯ͠Լ͍͞ɻ Note 5. I2C, RIN4/IN4−, LIN4/IN4+, MIN/LIN3, RIN3, RIN2/IN2−, LIN2/IN2+, LIN1/IN1−, RIN1/IN1+ pins Note 6. PDN, CSN/CAD0, CCLK/SCL, CDTI/SDA, SDTI, LRCK, BICK, MCKI pins SDA, SCL pinsͷଓઌ(TVDD+0.3)VҎԼʹͯ͠Լ͍͞ɻ ҙ: อূ ͞Ε·ͤΜɻ AVSS, HVSS=0V; Note 3) Parameter Symbol min typ max Units Power Supplies Analog AVDD 2.6 3.3 3.6 V (Note 7) Digital DVDD 2.6 3.3 3.6 V Digital I/O TVDD 1.6 3.3 DVDD V HP-Amp HVDD 2.6 3.3 / 5.0 5.25 V Difference AVDD−DVDD −0.3 0 +0.3 V Note 7. AVDD, DVDD, TVDD, HVDDྀ͢Δඞཁ͋Γ·ͤΜɻAVDD, HVDD, ͝ҙԼ͍͞ɻ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 7 - Ξφϩάಛੑ (Ta=25°C; AVDD, DVDD, TVDD, HVDD=3.3V; AVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Units MIC Amplifier: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”); MDIF1=MDIF2 bits = “0” (Single-ended inputs) MGAIN1-0 bits = “00” 40 60 80 kΩ Input Resistance MGAIN1-0 bits = “01”, “10”or “11” 20 30 40 kΩ MGAIN1-0 bits = “00” - 0 - dB MGAIN1-0 bits = “01” - +20 - dB MGAIN1-0 bits = “10” - +26 - dB Gain MGAIN1-0 bits = “11” - +32 - dB MIC Amplifier: IN1+/IN1−/IN2+/IN2− pins; MDIF1 = MDIF2 bits = “1” (Full-differential input) Input Voltage (Note 8) MGAIN1-0 bits = “01” - - 0.228 Vpp MGAIN1-0 bits = “10” - - 0.114 Vpp MGAIN1-0 bits = “11” - - 0.057 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 9) 2.22 2.47 2.72 V Load Resistance 0.5 - - kΩ Load Capacitance - - 30 pF ADC Analog Input Characteristics: LIN1/RIN1/LIN2/RIN2/LIN4/RIN4 pins & LIN3/RIN3 pins (AIN3 bit = “1”) → ADC → IVOL, IVOL=0dB, ALC=OFF Resolution - - 16 Bits (Note 11, LIN1/RIN1/LIN2/RIN2) 71 83 - dBFS (Note 11, LIN3/RIN3/LIN4/RIN4) - 83 - dBFS (Note 12, except for LIN3/RIN3) - 88 - dBFS S/(N+D) (−1dBFS) (Note 12, LIN3/RIN3) - 72 - dBFS (Note 11) 76 86 - dB D-Range (−60dBFS, A-weighted) (Note 12) - 95 - dB (Note 11) 76 86 - dB S/N (A-weighted) (Note 12) - 95 - dB (Note 11) 75 90 - dB Interchannel Isolation (Note 12) - 100 - dB (Note 11) - 0.1 0.8 dB Interchannel Gain Mismatch (Note 12) - 0.1 0.8 dB Note 8. Ͱ͢ɻACೖྗϐϯʹγϦʔ ζʹଓͯ͠Լ͍͞ɻMGAIN1-0 bits = “00”Ͱ͢ɻIN1+, IN1−, IN2+, IN2− pin (max)@MGAIN1-0 bits = “01”, 0.035 x AVDD (max)@MGAIN1-0 bits = “10”, 0.017 x AVDD (max)@MGAIN1-0 bits = “11”. Note 9. ग़ྗిѹAVDDʹൺྫ͠·͢ɻVout = 0.75 x AVDD (typ)ɻ Note 10. ೖྗిѹAVDDʹൺྫ͠·͢ɻVin = 0.06 x AVDD (typ)@MGAIN1-0 bits = “01” (+20dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = “00” (0dB) Note 11. MGAIN1-0 bits = “01” (+20dB) Note 12. MGAIN1-0 bits = “00” (0dB)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 8 - Parameter min typ max Units DAC Characteristics: Resolution - - 16 Bits Stereo Line Output Characteristics: DAC → LOUT/ROUT pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “0”, RL=10kΩ; unless otherwise specified. Output Voltage (Note 13) LOVL bit = “0” 1.78 1.98 2.18 Vpp LOVL bit = “1” 2.25 2.50 2.75 Vpp S/(N+D) (−3dBFS) 78 88 - dBFS S/N (A-weighted) 82 92 - dB Interchannel Isolation 80 100 - dB Interchannel Gain Mismatch - 0.1 0.5 dB Load Resistance 10 - - kΩ Load Capacitance - - 30 pF Mono Line Output Characteristics: DAC → LOP/LON pins, ALC=OFF, IVOL=0dB, DVOL=0dB, LOVL bit = “0”, LODIF bit = “1”, RL=10kΩ for each pin (Full-differential) Output Voltage (Note 14) LOVL bit = “0” 3.52 3.96 4.36 Vpp LOVL bit = “1” - 5.00 - Vpp S/(N+D) (−3dBFS) 78 88 - dBFS S/N (A-weighted) 85 95 - dB Load Resistance (LOP/LON pins, respectively) 10 - - kΩ Load Capacitance (LOP/LON pins, respectively) - - 30 pF Note 13. ग़ྗిѹAVDDʹൺྫ͠·͢ɻVout = 0.6 x AVDD (typ)@LOVL bit = “0”. Note 14. ग़ྗిѹAVDDʹൺྫ͠·͢ɻVout = (LOP) − (LON) = 1.2 x AVDD (typ)@LOVL bit = “0”.
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 10 - Parameter min typ max Units Mono Input: MIN pin (AIN3 bit = “0”; External Input Resistance=20kΩ) Maximum Input Voltage (Note 18) - 1.98 - Vpp Gain (Note 19) MIN Æ LOUT/ROUT LOVL bit = “0” −4.5 0 +4.5 dB LOVL bit = “1” - +2 - dB MIN Æ HPL/HPR HPG bit = “0” −24.5 −20 −15.5 dB HPG bit = “1” - −16.4 - dB Stereo Input: LIN2/RIN2/LIN4/RIN4 pins; LIN3/RIN3 pins (AIN3 bit = “1”) Maximum Input Voltage (Note 20) - 1.98 - Vpp Gain LIN/RIN Æ LOUT/ROUT LOVL bit = “0” −4.5 0 +4.5 dB LOVL bit = “1” - +2 - dB LIN/RIN Æ HPL/HPR HPG bit = “0” −4.5 0 +4.5 dB HPG bit = “1” - +3.6 - dB Full-differential Mono Input: IN4+/− pins (L4DIF bit = “1”) Maximum Input Voltage (Note 21) - 3.96 - Vpp Gain IN4+/− Æ LOUT/ROUT LOVL bit = “0” −10.5 −6 −1.5 dB (LODIF bit = “0”) LOVL bit = “1” - −4 - dB IN4+/− Æ LOP/LON LOVL bit = “0” −4.5 0 +4.5 dB (LODIF bit = “1”, Note 22) LOVL bit = “1” - +2 - dB IN4+/− Æ HPL/HPR HPG bit = “0” −10.5 −6 −1.5 dB HPG bit = “1” - −2.4 - dB Power Supplies: Power Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD+TVDD (Note 23) - 16 24 mA HVDD: HP-Amp Normal Operation No Output (Note 24) - 5 8 mA Power Down (PDN pin = “L”) (Note 25) AVDD+DVDD+TVDD+HVDD - 1 100 µA Note 18. େೖྗిѹAVDD߅Rin)ʹൺྫ͠·͢ɻVin = 0.6 x AVDD x Rin / 20kΩ (typ). Note 20. େೖྗిѹAVDDʹൺྫ͠·͢ɻVin = 0.6 x AVDD (typ). Note 21. େೖྗిѹAVDDʹൺྫ͠·͢ɻVin = (IN4+) − (IN4−) = 1.2 x AVDD (typ). Note 22. Vout = (LOP) − (LON) at LODIF bit = “1”. Note 23. PLL Master Mode (MCKI=12.288MHz)ͰɺPMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = MCKO = PMMIN = PMMP = M/S bits = “1”Ͱ͢ɻ͜ͷͱ͖ɺMPWR pinͷग़ AVDD=11mA(typ), DVDD=3mA(typ), TVDD=2mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = “0”)߹AVDD=10mA(typ), DVDD=3mA(typ), TVDD=0.03mA(typ). Note 24. PMADL = PMADR = PMDAC = PMLO = PMHPL = PMHPR = PMVCM = PMPLL = PMMIN bits = “1”ͷ Ͱ͢ɻ
BICK=64fs; 1kHz, 0dBFS input; Headphone = No output. Table 1. Power Consumption for each operation mode (typ)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 12 - ϑΟϧλಛੑ FIL1=FIL3=EQ=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 26) ±0.16dB PB 0 - 17.3 kHz −0.66dB - 19.4 - kHz −1.1dB - 19.9 - kHz −6.9dB - 22.1 - kHz Stopband SB 26.1 - - kHz Passband Ripple PR - - ±0.1 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 27) GD - 19 - 1/fs Group Delay Distortion ∆GD - 0 - µs ADC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR - 0.9 - Hz −0.5dB - 2.7 - Hz −0.1dB - 6.0 - Hz DAC Digital Filter (LPF): Passband (Note 26) ±0.1dB PB 0 - 19.6 kHz −0.7dB - 20.0 - kHz −6.0dB - 22.05 - kHz Stopband SB 25.2 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 59 - - dB Group Delay (Note 27) GD - 25 - 1/fs DAC Digital Filter (LPF) + SCF: Frequency Response: 0 ∼ 20.0kHz FR - ±1.0 - dB DAC Digital Filter (HPF): (Note 28) Frequency Response (Note 26) −3.0dB FR - 0.9 - Hz −0.5dB - 2.7 - Hz −0.1dB - 6.0 - Hz BOOST Filter: (Note 29) MIN 20Hz FR - 5.76 - dB 100Hz - 2.92 - dB 1kHz - 0.02 - dB MID 20Hz FR - 10.80 - dB 100Hz - 6.84 - dB 1kHz - 0.13 - dB MAX 20Hz FR - 16.06 - dB 100Hz - 10.54 - dB Frequency Response 1kHz - 0.37 - dB Note 26. ৼ෯ಛੑͷप fs (γεςϜαϯϓϦϯάϨʔτ)ʹൺྫ͠·͢ɻ Ͱ͢ɻ DAC෦16ؒ࣌ Ͱ͢ɻPMADL=PMADR bits = “0”ͷͱ͖DAC෦ͷGroup Delay25/fs(typ)Ͱ͢ɻ Note 28. PMADL bit = “1” or PMADR bit = “1”ͷͱ͖ɺADCͷHPFONɺDACͷHPFOFFͰ͢ɻ PMADL=PMADR bits = “0”, PMDAC bit = “1”ͷͱ͖ɺDACͷHPFONɺADCͷHPFOFFͰ͢ɻ Note 29. ɺҬͰΫ Ϧοϓ͠·͢ɻ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 13 - DCಛੑ Parameter Symbol min typ max Units High-Level Input Voltage 2.2V ≤TVDD≤3.6V VIH 70 %TVDD - - V 1.6V ≤TVDD<2.2V VIH 75 %TVDD - - V Low-Level Input Voltage 2.2V ≤TVDD≤3.6V VIL - - 30 %TVDD V 1.6V ≤TVDD<2.2V VIL - - 25 %TVDD V High-Level Output Voltage (Iout=−200µA) VOH TVDD−0.2 - - V Low-Level Output Voltage (Except SDA pin: Iout=200µA) VOL - - 0.2 V (SDA pin: Iout=3mA) VOL - - 0.4 V Input Leakage Current Iin - - ±10 µA εΠονϯάಛੑ Parameter Symbol min typ max Units PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Output Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH - tBCK - ns Except DSP Mode: Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - % PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 - 27 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns MCKO Output Timing Frequency fMCK 0.2352 - 12.288 MHz Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 60 % 256fs at fs=32kHz, 29.4kHz dMCK - 33 - % LRCK Input Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK −60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 14 - Parameter Symbol min typ max Units PLL Slave Mode (PLL Reference Clock = LRCK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK −60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period tBCK 1/(64fs) - 1/(32fs) ns Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns PLL Slave Mode (PLL Reference Clock = BICK pin) LRCK Input Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH tBCK−60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period PLL3-0 bits = “0010” tBCK - 1/(32fs) - ns PLL3-0 bits = “0011” tBCK - 1/(64fs) - ns Pulse Width Low tBCKL 0.4 x tBCK - - ns Pulse Width High tBCKH 0.4 x tBCK - - ns External Slave Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 - 12.288 MHz 512fs fCLK 3.7632 - 13.312 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Input Timing Frequency 256fs fs 7.35 - 48 kHz 512fs fs 7.35 - 26 kHz 1024fs fs 7.35 - 13 kHz DSP Mode: Pulse Width High tLRCKH tBCK−60 - 1/fs − tBCK ns Except DSP Mode: Duty Cycle Duty 45 - 55 % BICK Input Timing Period tBCK 312.5 - - ns Pulse Width Low tBCKL 130 - - ns Pulse Width High tBCKH 130 - - ns External Master Mode MCKI Input Timing Frequency 256fs fCLK 1.8816 - 12.288 MHz 512fs fCLK 3.7632 - 13.312 MHz 1024fs fCLK 7.5264 - 13.312 MHz Pulse Width Low tCLKL 0.4/fCLK - - ns Pulse Width High tCLKH 0.4/fCLK - - ns LRCK Output Timing Frequency fs 7.35 - 48 kHz DSP Mode: Pulse Width High tLRCKH - tBCK - ns Except DSP Mode: Duty Cycle Duty - 50 - % BICK Output Timing Period BCKO bit = “0” tBCK - 1/(32fs) - ns BCKO bit = “1” tBCK - 1/(64fs) - ns Duty Cycle dBCK - 50 - %
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 15 - Parameter Symbol min typ max Units Audio Interface Timing (DSP Mode) Master Mode LRCK “↑” to BICK “↑” (Note 30) tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns LRCK “↑” to BICK “↓” (Note 31) tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns BICK “↑” to SDTO (BCKP bit = “0”) tBSD −70 - 70 ns BICK “↓” to SDTO (BCKP bit = “1”) tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK “↑” to BICK “↑” (Note 30) tLRB 0.4 x tBCK - - ns LRCK “↑” to BICK “↓” (Note 31) tLRB 0.4 x tBCK - - ns BICK “↑” to LRCK “↑” (Note 30) tBLR 0.4 x tBCK - - ns BICK “↓” to LRCK “↑” (Note 31) tBLR 0.4 x tBCK - - ns BICK “↑” to SDTO (BCKP bit = “0”) tBSD - - 80 ns BICK “↓” to SDTO (BCKP bit = “1”) tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Audio Interface Timing (Right/Left justified & I2S) Master Mode BICK “↓” to LRCK Edge (Note 32) tMBLR −40 - 40 ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD −70 ns BICK “↓” to SDTO tBSD −70 - 70 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Slave Mode LRCK Edge to BICK “↑” (Note 32) tLRB 50 - - ns BICK “↑” to LRCK Edge (Note 32) tBLR 50 - - ns LRCK Edge to SDTO (MSB) (Except I2S mode) tLRD ns BICK “↓” to SDTO tBSD - - 80 ns SDTI Hold Time tSDH 50 - - ns SDTI Setup Time tSDS 50 - - ns Note 30. MSBS, BCKP bits = “00” or “11”. Note 31. MSBS, BCKP bits = “01” or “10”.
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 16 - Parameter Symbol min typ max Units Control Interface Timing (3-wire Serial mode) CCLK Period tCCK 200 - - ns CCLK Pulse Width Low tCCKL 80 - - ns Pulse Width High tCCKH 80 - - ns CDTI Setup Time tCDS 40 - - ns CDTI Hold Time tCDH 40 - - ns CSN “H” Time tCSW 150 - - ns CSN “↓” to CCLK “↑” tCSS 50 - - ns CCLK “↑” to CSN “↑” tCSH 50 - - ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - µs Clock Low Time tLOW 1.3 - - µs Clock High Time tHIGH 0.6 - - µs Setup Time for Repeated Start Condition tSU:STA 0.6 - - µs SDA Hold Time from SCL Fa lling (Note 34) tHD:DAT 0 - - µs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - µs Rise Time of Both SDA and SCL Lines tR - - 0.3 µs Fall Time of Both SDA and SCL Lines tF - - 0.3 µs Setup Time for Stop Condition tSU:STO 0.6 - - µs Capacitive Load on Bus Cb - - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns Power-down & Reset Timing PDN Pulse Width (Note 35) tPD 150 - - ns PMADL or PMADR “↑” to SDTO valid (Note 36) tPDV - 1059 - 1/fs Note 33. I2CPhilips SemiconductorsͷొඪͰ͢ɻ Note 35. AK4645PDN pin = “L”ͰϦηοτ͞Ε·͢ɻ
Table 2. Clock Mode Setting (x: Don’t care) Table 3. Clock pins state in Clock Mode
0 Slave Mode Default
1 Master Mode
Table 4. Select Master/Slave Mode
**Table 5. Setting of PLL Mode (*fs: Sampling Frequency)** Table 6. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = MCKI pin)
Table 7. Setting of Sampling Frequency at PMPLL bit = “1” (Reference Clock = LRCK or BICK pin) Table 8. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
Figure 19. PLL Master Mode Table 10. MCKOप (PLLϞʔυ, MCKO bit = “1”) Table 11. BICK Output Frequency at Master Mode
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
Table 12. EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) ͷMCKIपͷઃఆ Table 13. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 23. EXT Slave Mode
Table 14. EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)ͷMCKIपͷઃఆ Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins Figure 24. EXT Master Mode Table 16. BICK Output Frequency at Master Mode
Figure 29. Mode 1 Timing
14 Don't Care
Figure 30. Mode 2 Timing
15 Don't Care
Figure 31. Mode 3 Timing
0 Lch Input Signal Rch Input Signal 1 1 1 (L+R)/2 (L+R)/2
Table 19. ϞϊϥϧʗεςϨΦΓସ͑(x: Don’t care)
Table 20. MIC/Line In Path Select Table 21. Handling of MIC/Line Input Pins (“-“: N/A; “X”: Signal should not be input.)
Table 23. ϚΠΫೖྗήΠϯ
0 Hi-Z Default
1 Output
Table 24. ϚΠΫύϫʔ Figure 34. MIC Block Circuit
Table 25. Digital EQ/HPF/LPFઃఆ (x: Don’t care) Figure 35. Digital EQ/HPF/LPF Table 26. Gain෦ͷήΠϯઃఆ (x: Don’t care)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 41 - 1) FIL1, FIL3 ΛHPF߹ fs: αϯϓϦϯάप fc: ΧοτΦϑप f: प K: ήΠϯ[dB] (FIL1ͷήΠϯ0dBʹઃఆͯ͠Լ͍͞ɻ) Ϩδελઃఆ FIL1: F1AS bit = “0”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “0”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) A = 10K/20 x 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) ৼ෯ Ґ૬ H(z) = A 1 − z −1 1 + Bz −1 M(f) = A 2 − 2cos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (B+1)sin (2πf/fs) 1 - B + (B−1)cos (2πf/fs) 2) FIL1, FIL3 ΛLPF߹ fs: αϯϓϦϯάप fc: ΧοτΦϑप f: प K: ήΠϯ[dB] (FIL1ͷήΠϯ0dBʹઃఆͯ͠Լ͍͞ɻ) Ϩδελઃఆ FIL1: F1AS bit = “1”, F1A[13:0] bits =A, F1B[13:0] bits =B FIL3: F3AS bit = “1”, F3A[13:0] bits =A, F3B[13:0] bits =B (MSB=F1A13, F1B13, F3A13, F3B13; LSB=F1A0, F1B0, F3A0, F3B0) A = 10K/20 x 1 + 1 / tan (πfc/fs) B = 1 − 1 / tan (πfc/fs) 1 + 1 / tan (πfc/fs) ৼ෯ Ґ૬ H(z) = A 1 + z −1 1 + Bz −1 M(f) = A 2 + 2cos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (B−1)sin (2πf/fs) 1 + B + (B+1)cos (2πf/fs)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 42 - 3) EQ fs: αϯϓϦϯάप fc1: ͷप fc2: ྵͷप f: प Ϩδελઃఆ EQA[15:0] bits =A, EQB[13:0] bits =B, EQC[15:0] bits =C (MSB=EQA15, EQB13, EQC15; LSB=EQA0, EQB0, EQC0) A = 10K/20 x 1 + 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) B = 1 − 1 / tan (πfc1/fs) 1 + 1 / tan (πfc1/fs) , C =10 K/20 x 1 − 1 / tan (πfc2/fs) 1 + 1 / tan (πfc1/fs) ৼ෯ Ґ૬ H(z) = A + Cz −1 1 + Bz −1 M(f) = A2 + C2 + 2ACcos (2πf/fs) 1 + B2 + 2Bcos (2πf/fs) θ(f) = tan −1 (AB−C)sin (2πf/fs) A + BC + (AB+C)cos (2πf/fs) X=() x 213 ઃఆϨδελͷMSBϏοτͰ͢ɻ [ͷઃఆྫ] 1) FIL1 ϒϩοΫ ྫ: fs=44.1kHz, fc=100HzͷHPF߹ F1AS bit = “0” F1A[13:0] bits = 01 1111 1100 0110 F1B[13:0] bits = 10 0000 0111 0100 2) EQ ϒϩοΫ ྫ: fs=44.1kHz, fc 1=300Hz, fc2=3000Hz, Gain=+8dB߹ Gain[dB] +8dB fc1 fc 2 Frequency EQA[15:0] bits = 0000 1001 0110 1110 EQB[13:0] bits = 10 0001 0101 1001 EQC[15:0] bits = 1111 1001 1110 1111
Table 27. ALCઃఆ (x: Don’t care) Table 28. ALC ΧϯλϦηοτϨϕϧ Table 29. ALC ϦϛολATTεςοϓͷઃఆ (x: Don’t care) Table 30. ALCͷઃఆ
Table 31. ALCͷઃఆ Table 32. ALC ϦΧόϦήΠϯྔͷઃఆ
Table 33. ALC४ઃఆ Table 34. ϑΝʔετϦΧόϦઃఆ
Table 35. ALCઃఆྫ Figure 36. ALCઃఆखॱྫ
- ɺALC͢ΔϨδελઃఆ(ZTM1-0, LMTH1-0 bitsͳͲ)ɻ
Table 36. ೖྗσΟδλϧϘϦϡʔϜͷઃఆ
Figure 37. ALCதͷIVOLྫ
Table 37. σΟΤϯϑΝγείϯτϩʔϧ Figure 38. όεϒʔετप (fs=44.1kHz) Table 38. όεϒʔετίϯτϩʔϧ
Table 39. Digital Volume Code Table
Figure 39. ೳ
Figure 40. ΞφϩάϛΩγϯάճ࿏(εςϨΦೖྗ)
Figure 44. Full-differential Mono Analog Mixing Circuit Table 44. IN4+/IN4− Input Æ LOUT/ROUT Output Gain (typ) Table 45. IN4+/IN4− Input Æ LOP/LON Output Gain (typ) Table 46. IN4+/IN4− Input Æ Headphone-Amp Output Gain (typ)
Figure 7. Block Diagram of MIN pin Table 47. Ri = 20kΩ ɺMINೖྗ Æ LOUT/ROUTग़ྗήΠϯ(typ) Table 48. Ri = 20kΩ ɺMINೖྗ Æ LOP/LONग़ྗήΠϯ(typ) Table 49. Ri = 20kΩ ɺMINೖྗ Æ ϔουϑΥϯग़ྗήΠϯ(typ)
Figure 47. εςϨΦϥΠϯग़ྗίϯτϩʔϧγʔέϯε(࣌ )
Figure 52. Mono Line Output
1 Power-save Hi-Z VCOM 1 0 Normal Operation Normal Operation Normal Operation
Table 52. Mono Line Output Mode Setting (x: Don’t care) Table 53. Mono Line Output Volume Setting Figure 53. Power-up/Power-down Timing for Mono Line Output
Table 54. ϔουϑΥϯͷग़ྗిѹ Figure 56. ϔουϑΥϯΞϯϓͷύϫʔΞοϓʗμϯγʔέϯε
Figure 57. ϔουϑΥϯΞϯϓͷ֎͚ճ࿏ྫ Table 56. ϔουϑΥϯΞϯϓͷίϞϯిѹ Table 57. HP-Amp Mode Setting (x: Don’t care)
Figure 63. γϦΞϧίϯτϩʔϧΠϯλϑΣʔελΠϛϯά
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 70 - ϨδελϚοϓ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 PMVCM PMMIN 0 PMLO PMDAC 0 PMADL 01H Power Management 2 HPZ HP MTN PMHPL PMHPR M/S 0 MCKO PMPLL 02H Signal Select 1 0 0 0 DACL 0 PMMP 0 MGAIN0 03H Signal Select 2 LOVL LOPS MGAIN1 0 0 MINL 0 0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 05H Mode Control 2 PS1 PS0 FS3 MSBS BCKP FS2 FS1 FS0 06H Timer Select DVTM WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0 07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 VBAT 0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 0DH Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 0EH Mode Control 3 0 LOOP SM UTE DVOLC BST1 BST0 DEM1 DEM0 0FH Mode Control 4 0 0 0 0 IVOLC HPM MINH DACH 10H Power Management 3 INR1 INL1 HPG MDIF2 MDIF1 INR0 INL0 PMADR 11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ Co-efficient 0 EQA7 EQA6 E QA5 EQA4 EQA3 EQA2 EQA1 EQA0 17H EQ Co-efficient 1 EQA15 EQA1 4 EQA13 EQA12 EQA11 EQA10 EQA9 EQA8 18H EQ Co-efficient 2 EQB7 EQB6 EQ B5 EQB4 EQB3 EQB2 EQB1 EQB0 19H EQ Co-efficient 3 0 0 EQB13 EQB12 EQB11 EQB10 EQB9 EQB8 1AH EQ Co-efficient 4 EQC7 EQC6 EQ C5 EQC4 EQC3 EQC2 EQC1 EQC0 1BH EQ Co-efficient 5 EQC15 EQC14 E QC13 EQC12 EQC11 EQC10 EQC9 EQC8 1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 20H Power Management 4 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL 21H Mode Control 5 0 0 MICR3 MICL3 L4DIF MIX AIN3 LODIF 22H Lineout Mixing Select LOM LOM3 RINR4 LINL4 RINR3 LINL3 RINR2 LINL2 23H HP Mixing Select 0 HPM3 RINH4 LINH4 RINH3 LINH3 RINH2 LINH2 24H Reserved 0 0 0 0 0 0 0 0 Note 42. PDN pinΛ “L” Խ͞Ε·͢ɻ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 71 - આ໌ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 1 0 PMVCM PMMIN 0 PMLO PMDAC 0 PMADL Default 0 0 0 0 0 0 0 0 PMADL: MIC-Amp Lch, ADC LchͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMADL·ͨPMADR bitΛ “0”͔Β “1”ԽαΠΫϧ(1059/fs=24ms@44.1kHz)͕ PMDAC: DACͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMLO: εςϨΦϥΠϯग़ྗͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMMIN: ϞϊϥϧೖྗͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMVCM: VCOM ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up ͯ͠“0”Ή͜ͱ͕Ͱ͖ΔͷɺΞυϨε00H, 01H, 02H, 10H, 20H ͷશͯͷύϫʔϚωδϝ Խ͞Ε·͢ɻ ·ͨɺΞυϨε00H, 01H, 02H, 10H, 20H ͷશͯͷύϫʔϚωδϝϯτϏοτͱMCKO bitΛ“0”ʹ͢Δ͜ͱ ͯ͠Լ͍͞ɻ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 72 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 2 HPZ HP MTN PMHPL PMHPR M/S 0 MCKO PMPLL Default 0 0 0 0 0 0 0 0 PMPLL: PLL ͷύϫʔϚωδϝϯτ 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up MCKO: MCKOޚ 0: Disable: MCKO pin = “L” (Default) 1: Enable: Output frequency is selected by PS1-0 bits. M/S: Master / Slave Mode ͷબ 0: Slave Mode (Default) 1: Master Mode PMHPR: Rch ϔουϑΥϯΞϯϓͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMHPL: Lch ϔουϑΥϯΞϯϓͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up HPMTN: ϔουϑΥϯΞϯϓͷϛϡʔτ 0: Mute (Default) 1: Normal operation HPZ: HP-Ampͷϓϧμϯઃఆ 0 : άϥϯυʹγϣʔτ (Default) 1: 200k Ω(typ)Ͱϓϧμϯ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Signal Select 1 0 0 0 DACL 0 PMMP 0 MGAIN0 Default 0 0 0 0 0 0 0 1 MGAIN1-0: ϚΠΫΞϯϓͷήΠϯίϯτϩʔϧ(See Table 23) MGAIN1 bit03HͷD5 bitͰ͢ɻ PMMP: MPWR pin ͷύϫʔϚωδϝϯτ 0: Power down: Hi-Z (Default) 1: Power up DACL: DACͷίϯτϩʔϧ 0: OFF (Default) 1: ON PMLO bit = “1”ʹͳΓ·͢ɻPMLO bit = “0”ɺLOUT, ROUT pinsAVSS Λग़ྗ͠·͢ɻ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 73 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Signal Select 2 LOVL LOPS MGAIN1 0 0 MINL 0 0 Default 0 0 0 0 0 0 0 0 MINL: εςϨΦϥΠϯग़ྗʹೖྗ͞ΕΔMINͷίϯτϩʔϧ 0: OFF (Default) 1: ON PMLO bit = “1”ʹͳΓ·͢ɻPMLO bit = “0”ɺLOUT, ROUT pinsAVSS Λग़ྗ͠·͢ɻ MGAIN1: ϚΠΫΞϯϓͷήΠϯίϯτϩʔϧ(See Table 23) LOPS: εςϨΦϥΠϯग़ྗͷύϫʔηʔϒϞʔυ 0: Normal Operation (Default) 1: Power Save Mode LOVL: εςϨΦϥΠϯग़ྗ/ಈϞϊϥϧϥΠϯग़ྗήΠϯઃఆ(See Table 51, Table 53) 0: 0dB/+6dB (Default) 1: +2dB/+8dB Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0 Default 0 0 0 0 0 0 1 0 DIF1-0: ΦʔσΟΦΠϯλϑΣʔεϑΥʔϚοτ (See Table 17) Default: “10” (Ί) BCKO: ͷBICKग़ྗपͷઃఆ (See Table 11) PLL3-0: PLL४ΫϩοΫͷબ(See Table 5) Default: “0000”(LRCK pin) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Mode Control 2 PS1 PS0 FS3 MSBS BCKP FS2 FS1 FS0 Default 0 0 0 0 0 0 0 0 FS3-0: αϯϓϦϯάप(See Table 6 and Table 7)ͼMCKIपͷઃఆ(See Table 12) BCKP: DSP ModeͷBICKੑઃఆ (See Table 18) MSBS: DSP ModeͷLRCKҐ૬ઃఆ (See Table 18) “0”: LRCKͷ “↑”͕νϟωϧସͷBICK લ(Default) PS1-0: MCKO पͷઃఆ(See Table 10) Default: “00”(256fs)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 74 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Timer Select DVTM WTM2 ZTM 1 ZTM0 WTM1 WTM0 RFST1 RFST0 Default 0 0 0 0 0 0 0 0 RFST1-0: ALCϑΝʔετϦΧόϦͷ(See Table 34) Default: “00”(4ഒ)ɻ WTM2-0: ALCͷઃఆ(See Table 31) ALC “000” (128/fs)Ͱ͢ɻ ZTM1-0: ALCͷઃఆ(See Table 30) ɺALC͞ΕΔͷɺθϩΫϩε͢Δ͔ DVTM: Digital VolumeΛઃఆ͠·͢ɻ 0: 1061/fs (Default) 1: 256/fs DVL7-0, DVR7-0 bits Λ00H͔ΒFFHͰ͢ɻ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0 Default 0 0 0 0 0 0 0 0 LMTH1-0: ALCग़ઃఆϨϕϧ/ΧϯλϦηοτϨϕϧ(See Table 28) Default: “00” LMTH1 bit0BHͷD6 bitͰ͢ɻ RGAIN1-0: ALCϦΧόϦήΠϯεςοϓ(See Table 32) Default: “00” RGAIN1 bit0BHͷD7 bitͰ͢ɻ LMAT1-0: ALCϦϛολATTεςοϓ(See Table 29) Default: “00” ZELMN: ALCग़Πωʔϒϧ 0: Enable (Default) 1: Disable ALC: ALC Πωʔϒϧ 0: ALC Disable (Default) 1 : A L C E n a b l e Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0 Default 1 1 1 0 0 0 0 1 REF7-0: ALC४ͷઃఆɻ0.375dB step, 242 Level (See Table 33) Default: “E1H” (+30.0dB)
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 75 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Lch Input Volume Control IVL7 IVL6 IVL5 IVL4 IVL3 IVL2 IVL1 IVL0 0CH Rch Input Volume Control IVR7 IVR6 IVR5 IVR4 IVR3 IVR2 IVR1 IVR0 Default 1 1 1 0 0 0 0 1 IVL7-0, IVR7-0: ೖྗσΟδλϧϘϦϡʔϜ; 0.375dB step, 242 Level (See Table 36) Default: “E1H” (+30.0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0 0DH Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0 Default 0 0 0 1 1 0 0 0 DVL7-0, DVR7-0: ग़ྗσΟδλϧϘϦϡʔϜ(See Table 39) Default: “18H” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 VBAT 0 Default 0 0 0 0 0 0 0 0 VBAT: ϔουϑΥϯΞϯϓͷίϞϯిѹ(See Table 56) 0: 0.5 x HVDD (Default) 1: 0.64 x AVDD LMTH1: ALCग़ઃఆϨϕϧ/ΧϯλϦηοτϨϕϧ(See Table 28) RGAIN1: ALCϦΧόϦήΠϯεςοϓ(See Table 32) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Mode Control 3 0 LOOP SM UTE DVOLC BST1 BST0 DEM1 DEM0 Default 0 0 0 1 0 0 0 1 DEM1-0: σΟΤϯϑΝγείϯτϩʔϧ(See Table 37) Default: “01” (OFF) BST1-0: Ҭิਖ਼ճ࿏ͷίϯτϩʔϧ(See Table 38) Default: “00” (OFF) DVOLC: σΟδλϧϘϦϡʔϜͷίϯτϩʔϧ 0: Independent 1: Dependent (Default) DVOLC bit = “1” ͷͱ͖ɺDVL7-0 bit Ͱ྆νϟωϧͷσΟδλϧϘϦϡʔϜ͕มԽ͠·͢ɻୠ͠ɺ DVR7-0 bitʹDVL7-0 bit·Ε·ͤΜɻ SMUTE: ιϑτϛϡʔτίϯτϩʔϧ 0: Normal Operation (Default) 1: DAC outputs soft-muted LOOP: σόΠε෦ϧʔϓόοΫ 0 : S D T I → DAC (Default) 1 : S D T O → DAC
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 76 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Mode Control 4 0 0 0 0 IVOLC HPM MINH DACH Default 0 0 0 0 1 0 0 0 DACH: DACͷίϯτϩʔϧ 0: OFF (Default) 1: ON MINH: MIN pinͷίϯτϩʔϧ 0: OFF (Default) 1: ON HPM: ϔουϑΥϯͷϞϊϥϧग़ྗ 0 : εςϨΦ (Default) 1 : Ϟϊϥϧ IVOLC: IVOL ͷίϯτϩʔϧ 0: Independent 1: Dependent (Default) IVOLC bit = “1”ͷͱ͖ɺIVL7-0 bitͰ྆νϟωϧͷIVOL͕มԽ͠·͢ɻୠ͠ɺIVR7-0 bitʹIVL7-0 bit ·Ε·ͤΜɻ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H Power Management 3 INR1 INL1 HPG MDIF2 MDIF1 INR0 INL0 PMADR Default 0 0 0 0 0 0 0 0 PMADR: MIC-Amp Rch, ADC Rch ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up INL1-0: ADC Lch ೖྗιʔεબ(See Table 20) Default: 00 (LIN1 pin) INR1-0: ADC Rch ೖྗιʔεબ(See Table 20) Default: 00 (RIN1 pin) MDIF1: γϯάϧΤϯυ/ಈೖྗସ1 0 : γϯάϧΤϯυೖྗ (LIN1/RIN1 pin: Default) 1 : ಈೖྗ (IN1+/IN1− pin) MDIF2: γϯάϧΤϯυ/ಈೖྗସ2 0 : γϯάϧΤϯυೖྗ (LIN2/RIN2 pin: Default) 1 : ಈೖྗ (IN2+/IN2− pin) HPG: ϔουϑΥϯΞϯϓήΠϯઃఆ (See Table 54) 0: 0dB (Default) 1: +3.6dB
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 77 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0 Default 0 0 0 0 0 0 0 0 GN1-0: Gain෦ͷήΠϯઃఆ(See Table 26) Default: “00” (0dB) FIL3: ௐ༻FIL3ޮ 0: ޮDefault) 1: ޮ FIL3 bit = “1”ͷͱ͖ɺF3A13-0, F3B13-0 bitʹͳΓ·͢ɻFIL3 bit = “0”ͷͱ͖ɺFIL3ϒ ϩοΫOFF(MUTE)Ͱ͢ɻ EQ: ޮ 0: ޮDefault) 1: ޮ EQ bit = “1”ͷͱ͖ɺEQA15-0, EQB13-0, EQC15-0 bitʹͳΓ·͢ɻEQ bit = “0”ͷͱ͖ɺ EQϒϩοΫεϧʔ(0dB)Ͱ͢ɻ FIL1: ෩ΓԻϑΟϧλ༻FIL1ޮ 0: ޮDefault) 1: ޮ FIL1 bit = “1”ͷͱ͖ɺF1A13-0, F1B13-0 bitʹͳΓ·͢ɻFIL1 bit = “0”ͷͱ͖ɺFIL1ϒ ϩοΫεϧʔ(0dB)Ͱ͢ɻ Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0 13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8 14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0 15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8 16H EQ Co-efficient 0 EQA7 EQA6 E QA5 EQA4 EQA3 EQA2 EQA1 EQA0 17H EQ Co-efficient 1 EQA15 EQA1 4 EQA13 EQA12 EQA11 EQA10 EQA9 EQA8 18H EQ Co-efficient 2 EQB7 EQB6 EQ B5 EQB4 EQB3 EQB2 EQB1 EQB0 19H EQ Co-efficient 3 0 0 EQB13 EQB12 EQB11 EQB10 EQB9 EQB8 1AH EQ Co-efficient 4 EQC7 EQC6 EQ C5 EQC4 EQC3 EQC2 EQC1 EQC0 1BH EQ Co-efficient 5 EQC15 EQC14 E QC13 EQC12 EQC11 EQC10 EQC9 EQC8 1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0 1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8 1EH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0 1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8 Default 0 0 0 0 0 0 0 0 F3A13-0, F3B13-0: ௐ༻FIL3(14bit x 2) Default: “0000H” F3AS: ௐ༻FIL3ͷબ 0: HPF (Default) 1: LPF EQA15-0, EQB13-0, EQC15-C0: (14bit x 2 + 16bit x 1) Default: “0000H” F1A13-0, F1B13-B0: ෩ΓԻϑΟϧλ༻FIL1(14bit x 2) Default: “0000H” F1AS: ෩ΓԻϑΟϧλ༻FIL1ͷબ 0: HPF (Default) 1: LPF
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 78 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 20H Power Management 4 PMAINR4 PMAINL4 PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL Default 0 0 0 0 0 0 0 0 PMMICL: MIC-Amp LchͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMMICR: MIC-Amp RchͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINL2: LIN2ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINR2: RIN2ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINL3: LIN3ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINR3: RIN3ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINL4: LIN4ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up PMAINR4: RIN4ϛΩγϯάճ࿏ͷύϫʔϚωδϝϯτ 0: Power down (Default) 1: Power up
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 79 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 21H Mode Control 5 0 0 MICR3 MICL3 L4DIF MIX AIN3 LODIF Default 0 0 0 0 0 0 0 0 LODIF: ϥΠϯग़ྗઃఆ 0: εςϨΦϥΠϯग़ྗ (LOUT/ROUT pins) (Default) 1: ಈϞϊϥϧϥΠϯग़ྗ (LOP/LON pins) AIN3: ΞφϩάϛΩγϯάઃఆ 0: Ϟϊϥϧೖྗ (MIN pin) (Default) 1: εςϨΦೖྗ (LIN3/RIN3 pins): PLL༻Ͱ͖·ͤΜɻ MIX: ϞϊϥϧԻઃఆ 0: εςϨΦ (Default) 1: Ϟϊϥϧ: (L+R)/2 L4DIF: બ 0: εςϨΦೖྗ: LIN4/RIN4 pins (Default) 1: ಈϞϊϥϧೖྗ: IN4+/− pins MICL3:ϛΩγϯάύεઃఆ 0: LIN3 pin ೖྗ (Default) 1: MIC-Amp Lch ग़ྗ MICR3:ϛΩγϯάύεઃఆ 0: RIN3 pin ೖྗ (Default) 1: MIC-Amp Rch ग़ྗ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 80 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 22H Lineout Mixing Select LOM LOM3 RINR4 LINL4 RINR3 LINL3 RINR2 LINL2 Default 0 0 0 0 0 0 0 0 LINL2: LIN2ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON RINR2: RIN2ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON LINL3: LIN3 (or MIC-Amp Lch)ͷίϯτϩʔϧ 0: OFF (Default) 1: ON RINR3: RIN3 (or MIC-Amp Rch)ͷίϯτϩʔϧ 0: OFF (Default) 1: ON LINL4: LIN4ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON RINR4: RIN4ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON LOM3: MIC-Amp (or LIN3/RIN3)ͷϞϊϥϧઃఆ 0: Stereo Mixing (Default) 1: Mono Mixing LOM: DACͷϞϊϥϧઃఆ 0: Stereo Mixing (Default) 1: Mono Mixing
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 81 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 23H HP Mixing Select 0 HPM3 RI NH4 LINH4 RINH3 LINH3 RINH2 LINH2 Default 0 0 0 0 0 0 0 0 LINH2: LIN2ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON RINH2: RIN2ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON LINH3: LIN3 (or MIC-Amp Lch)ͷίϯτϩʔϧ 0: OFF (Default) 1: ON RINH3: RIN3 (or MIC-Amp Rch)ͷίϯτϩʔϧ 0: OFF (Default) 1: ON LINH4: LIN4ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON RINH4: RIN4ͷίϯτϩʔϧ(MIC-AmpόΠύε) 0: OFF (Default) 1: ON HPM3: MIC-Amp (or LIN3/RIN3)ͷϞϊϥϧઃఆ 0: Stereo Mixing (Default) 1: Mono Mixing
Figure 74. γεςϜଓਤ(AIN3 bit = “1”: PLL༻ෆՄ, ࣌ )
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 84 - 1. ͷσΧοϓϦϯά ͱάϥϯυͷऔΓํʹेҙͯ͠Լ͍͞ɻ௨ৗɺAVDD, DVDD, TVDD, HVDDʹγεςϜͷΞφ 2. ४ిѹ VCOM͢ΔͨΊʹ 2.2µF ఔͷిղίϯσϯαͱฒྻʹ0.1µFͷηϥϛοΫίϯσϯαΛAVSSʹଓͯ͠Լ͍͞ɻಛʹɺηϥ Լ͍͞ɻ 3. Ξφϩάೖྗ Ϩϯδ෦ͷίϞϯిѹ(0.45 x AVDD)Λத৺ʹ0.06 x AVDD Vpp(typ)@MGAIN1-0 bits = “01”, 0.03 x AVDD Vpp(typ)@MGAIN1-0 bits = “10”, 0.015 x AVDD Vpp(typ)@MGAIN1-0 bits = “11”·ͨɺ0.6 x AVDD Vpp(typ)@MGAIN1-0 bits = “00”ʹͳΓ·͢ɻMINೖྗͷೖྗϨϯδ෦ͷίϞϯిѹ(0.45 x AVDD)Λத৺ ʹ0.6 x AVDD Vpp(typ)ίϯσϯαͰDCΧοτΦϑप 4. Ξφϩάग़ྗ DACʹର͢ΔೖྗσʔλͷϑΥʔϚοτ2’sίϯϓϦϝϯτͰɺ7FFFH(@16bit)ʹରͯ͠ਖ਼ͷϑϧεέʔ ϧɺ8000H(@16bit)ʹରͯ͠ෛͷϑϧεέʔϧɺ0000H(@16bit)ͰͷཧVCOMిѹͰ͢ɻVCOMిѹ ɺεςϨΦϥΠϯग़ྗͰ0.45 x AVDD (typ)Λத৺ʹग़ྗ͞ΕɺϔουϑΥϯग़ྗͰHVDD/2Λத৺ʹ ग़ྗ͞Ε·͢ɻ
Figure 75. Clock Set Up Sequence (1)
- PLLεϨʔϒϞʔυͰ֎෦ΫϩοΫ(LRCK or BICK pin)߹
Figure 76. Clock Set Up Sequence (2)
- PLLεϨʔϒϞʔυͰ֎෦ΫϩοΫ(MCKI pin)߹
Figure 77. Clock Set Up Sequence (3)
Figure 78. Clock Set Up Sequence (4)
Figure 79. Clock Set Up Sequence (5)
Figure 80. MIC Input Recording Sequence
Figure 81. Headphone-Amp Output Sequence
Figure 82. Stereo Lineout Sequence
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 95 - ύοέʔδ 32pin QFN (Unit: mm) 4.75 ± 0.10 5.00 ± 0.10 4.75 ± 0.10 0.500.23 24 17 0.01 0.08 C0.42 +0.07 -0.05 0.40 ± 0.10 0.20 + 0.04 - 0.01C Exposed Pad 3.5 5.00 ± 0.10 0.85 ± 0.05 C B A
0.10 M AB
3.5 ༷ ࣭ࡐ :ࢷ ࣭ࡐ :ಔ ϦʔυϑϨʔϜॲཧ: ాʢແԖʣϝοΩ
ASAHI KASEI [AK4645] MS0543-J-00 2006/09 - 96 - ϚʔΩϯά AK4645 XXXXX AKM XXXXX : Date code identifier (5ܻ ) վగཤྺ Date (YY/MM/DD) Revision Reason Page Contents 06/09/14 00 ॳ൛
- ͢Δ͜ͱ ৽ͷͷͰ͋Δ͜ͱΛฐ ೝԼ͍͞ɻ
- ɺ༌ Մ͕ඞཁͰ͢ɻ
- ෆྑ͕ɺ ۃ දऔకͷॻ໘ ʹΑΔಉҙΛ͓औΓԼ͍͞ɻ
- ༻͔Β