AK4640 AKM | Alldatasheet

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[AK4640] MS0273-E-00 - 1 - GENERAL DESCRIPTION The AK4640 targeted at PDA and other low-power, small size applications. It features a 16bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4640 is available in a smaller 57pin BGA in addition to a 52pin QFN that has compatibility with the AK4534/8, utilizing less board space than competitive offerings.

FEATURES

  1. Resolution : 16bits 2. Recording Function
  • Mono Input
  • 2 to 1 Selector (Internal and External MIC)
  • 1st MIC Amplifier : +20dB or 0dB
  • 2nd Amplifier with ALC : +27.5dB ∼ −8dB, 0.5dB Step
  • ADC Performance : S/(N+D) : 79dB, DR, S/N : 83dB 3. Playback Function
  • Digital De-emphasis Filter (tc=50/15µs, fs=32kHz, 44.1kHz, 48kHz)
  • Digital Volume (0dB ∼ −127dB, 0.5dB Step, Mute)
  • Headphone-Amp - S/(N+D) : 70dB, S/N : 90dB - Output Power : 15mW@16Ω (HVDD=3.3V) - Click Noise Free at Power ON/OFF
  • Mono Speaker-Amp with ALC - S/(N+D) : 64dB@150mW, S/N : 90dB - BTL Output - ALC circuit - Output Power : 300mW@8Ω, THD+N=10% (HVDD=3.3V)
  • Mono and Stereo Beep Inputs 4. Phone I/F
  • Full-differential AUX Input
  • Full-differential Mono Output 5. Power Management 6. Master Clock (1) PLL Mode
  • Frequencies : 11.2896MHz, 12MHz and 12.288MHz
  • Input Level : CMOS (2) External Clock Mode
  • Frequencies : 1.792MHz ∼ 12.288MHz 7. Output Master Clock Frequencies : 32fs/64fs/128fs/256fs 8. Sampling Rate (1) PLL Mode
  • 8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz (2) External Clock Mode
  • 8kHz ∼ 48kHz 9. Control mode: 4-wire Serial / I2C Bus 10. Master/Slave mode 16-Bit ∆Σ CODEC with MIC/HP/SPK-AMP AK4640
  1. Audio Interface Format : MSB First, 2’s compliment
  • ADC : I2S, 16bit MSB justified
  • DAC : I2S, 16bit MSB justified, 16bit LSB justified 13. Power Supply: 2.4V ∼ 3.6V (typ. 3.3V) 14. Power Supply Current
  • AVDD+DVDD : 19mA
  • PVDD : 1.2mA
  • HVDD (HP-AMP=ON, SPK-AMP=OFF) : 4mA
  • HVDD (HP-AMP=OFF, SPK-AMP=ON) : 7mA 15. Package : 57pin BGA (5mm x 5mm, 0.5mm pitch) 52pin QFN (Pin Compatible with AK4534/8VN) 16. Register Compatible with AK4534/8 „ Block Diagram ALC1 (IPGA) PMMIC ATT AVDD AVSS MICOUT AIN LRCK BICK SDTO SDTI PDN DSP and uP DVDD DVSS HVDD HVSS VCOM MUTET MIN MOUT2 MOUT- AUXIN+ MIX HPL PMHPL HP-AMP HPR PMHPR HP-AMP Control Register Interface Audio PMSPK SPK- AMP SPP SPN I2C CSN/CAD1 CCLK/SCL CDTI/SDA CDTO Volume PMMO MOUT CAD0 AUXIN- MOUT+ ATT BEEPL PLL XTI/MCKI XTO MCKO VCOC PMPLL PVDD PVSS MIX MIX MIX MIX PMAUX MPE MIC Power Supply EXT INT MIC-AMP 0dB or 20dB MPI MIC Power Supply M/S PMBPS HPF ADC PMADC PMDAC DATT SMUTE DAC BEEPR MIX ATT ALC2 BEEPM PMBPM PMHPL or PMHPR or PMSPK

Figure 1. Block Diagram

[AK4640] MS0273-E-00 - 3 - „ Ordering Guide AK4640VG −10 ∼ +70°C 57pin BGA (0.5mm pitch) AK4640VN −10 ∼ +70°C 52pin QFN (0.4mm pitch) AKD4640 Evaluation board for AK4640 „ Pin Layout (AK4640VG) A Top View B C E D F G H J AK4640 NC HPR HVSS HVDD SPN SPP M/S XTI/MCKI NC HPL MUTET HVSS HVDD SPN SPP XTO DVDD DVSS MIN NC NC MCKO MOUT2 MOUT− BICK LRCK MOUT+ AUXIN− Top View SDTI SDTO BEEPM AUXIN+ CDTO I2C BEEPL BEEPR NC CCLK/SCL CDTI/SDA MICOUT AIN MPI VCOM AVDD AVDD PVSS CSN/CAD1 PDN NC EXT MPE INT AVSS PVDD VCOC CAD0 NC A B C D E F G H J

[AK4640] MS0273-E-00 - 4 - „ Pin Layout (AK4640VN) MIN MOUT2 NC NC MOUT− MOUT+ AUXIN− AUXIN+ BEEPM MUTET HPL HPR HVSS HVDD SPN SPP M/S MICOUT NC EXT MPE MPI INT VCOM AVSS AVDD NC MCKO BICK LRCK SDTO SDTI I2C CDTO CDTI/SDA Top View XTI/MCKI BEEPR BEEPL AIN CCLK/SCL CSN/CAD1 PDN XTO DVSS PVDD PVSS VCOC DVDD NC CAD0 NC NC AK4640

[AK4640] MS0273-E-00 - 5 - „ Comparison with AK4534, AK4538 1. Function Function AK4534 AK4538 AK4640 SPK-Amp Output Power at DAC path 150mW 150mW 300mW DAC Digital Filter Stopband Attenuation 43dB 43dB 59dB AUX Input Not Available Available Available MOUT Gain Select Not Available Available Available Path from IPGA to Analog Output Not Available Available Available HP-Amp Mono mode Not Available Available Available Stereo Line Out Not Available Available Not Available MIC Detect Not Available Available Not Available HP-Amp Power Supply Current (typ) 6.5mA 6.5mA 4mA SPK-Amp Power Supply Current (typ) 9mA 9mA 7mA Package 52pin QFN (7.2mm x 7.2mm) 52pin QFN (7.2mm x 7.2mm) 52pin QFN (7.2mm x 7.2mm), 57pin BGA (5mm x 5mm) 2. Pin Pin# AK4534 AK4538 AK4640VN TST1 MDT NC TST2 ROUT NC TST3 LOUT NC TST4 AUXIN− AUXIN− TST5 AUXIN+ AUXIN+ 3. Register Addr Data AK4534 AK4538 AK4640 00H PMAUX PMAUX PMLO 02H MICM MICM MOGN MOGN 03H MICL MICL AUXL AUXL PSLO 05H HPM HPM HPLM HPLM HPRM HPRM 07H AUXAD AUXAD 0EH D3-0 GN3-0 GN3-0 D6-4 ATTS2-0 ATTS2-0 ATTM ATTM 0FH DTMIC

[AK4640] MS0273-E-00 - 6 - PIN/FUNCTION (AK4640VG) No. Pin Name I/O Function NC No Connect. No internal bonding. This pin should be left floating. EXT I External Microphone Input Pin MPE O MIC Power Supply Pin for External Microphone MPI O MIC Power Supply Pin for Internal Microphone INT I Internal Microphone Input Pin VCOM O Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. AVSS Analog Ground Pin AVDD Analog Power Supply Pin AVDD Analog Power Supply Pin PVDD PLL Power Supply Pin PVSS PLL Ground Pin VCOC O Output Pin for Loop Filter of PLL Circuit This pin should be connected to PVSS with one resistor and capacitor in series. CAD0 I Chip Address 0 Select Pin NC No Connect. No internal bonding. This pin should be left floating. PDN I Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initializes the control register. CSN I Chip Select Pin (I2C pin = “L”) CAD1 I Chip Address 1 Select Pin (I2C pin = “H”) CCLK I Control Data Clock Pin (I2C pin = “L”) SCL I Control Data Clock Pin (I2C pin = “H”) CDTI I Control Data Input Pin (I2C pin = “L”) SDA I/O Control Data Input Pin (I2C pin = “H”) CDTO O Control Data Output Pin (I2C pin = “L”) I2C I Control Mode Select Pin “H”: I2C Bus, “L”: 4-wire Serial SDTI I Audio Serial Data Input Pin SDTO O Audio Serial Data Output Pin LRCK I/O Input / Output Channel Clock Pin BICK I/O Audio Serial Data Clock Pin NC No Connect. No internal bonding. This pin should be left floating. MCKO O Master Clock Output Pin DVDD Digital Power Supply Pin

[AK4640] MS0273-E-00 - 7 - No. Pin Name I/O Function NC No Connect. No internal bonding. This pin should be left floating. DVSS Digital Ground Pin XTO O X’tal Output Pin XTI I X’tal Input Pin MCKI I External Master Clock Input Pin M/S I Master / Slave Mode Pin “H” : Master Mode, “L” : Slave Mode SPP O Speaker Amp Positive Output Pin SPP O Speaker Amp Positive Output Pin SPN O Speaker Amp Negative Output Pin SPN O Speaker Amp Negative Output Pin HVDD Headphone/Speaker Amp Power Supply Pin HVDD Headphone/Speaker Amp Power Supply Pin HVSS Headphone/Speaker Amp Ground Pin HVSS Headphone/Speaker Amp Ground Pin HPR O Rch Headphone Amp Output Pin NC No Connect. No internal bonding. This pin should be left floating. HPL O Lch Headphone Amp Output Pin MUTET O Mute Time Constant Control Pin Connected to HVSS pin with a capacitor for mute time constant. NC No Connect. No internal bonding. This pin should be left floating. MIN I ALC2 Input Pin MOUT2 O Analog Mixing Output Pin MOUT− O Mono Line Negative Output Pin MOUT+ O Mono Line Positive Output Pin AUXIN− I Mono AUX Negative Input Pin AUXIN+ I Mono AUX Positive Input Pin BEEPM I Mono Beep Signal Input Pin BEEPR I Rch Stereo Beep Signal Input Pin BEEPL I Lch Stereo Beep Signal Input Pin AIN I Analog Input Pin MICOUT O Microphone Analog Output Pin NC No Connect. No internal bonding. This pin should be left floating. Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN−, BEEPM, BEEPL, and BEEPR) should not be left floating. „ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog Input EXT, INT, MIN, AUXIN−, AUXIN+, BEEPM, BEEPR, BEEPL, AIN These pins should be open and each path should be switched off. Analog Output MICOUT, MPE, MPI, VCOC, SPP, SPN, HPR, HPL, MUTET, MOUT2, MOUT−, MOUT+ These pins should be open. Digital Input CAD0, CSN, CCLK, CDTI, I2C, SDTI, LRCK (when M/S pin = “L”), BICK (when M/S pin = “L”), M/S These pins should be connected to DVSS. Digital Output CDTO, SDTO, LRCK (when M/S pin = “H”), BICK (when M/S pin = “H”), MCKO, XTO These pins should be open.

[AK4640] MS0273-E-00 - 8 - PIN/FUNCTION (AK4640VN) No. Pin Name I/O Function MICOUT O Microphone Analog Output Pin NC No Connect. No internal bonding. This pin should be left floating. EXT I External Microphone Input Pin (Mono Input) MPE O MIC Power Supply Pin for External Microphone MPI O MIC Power Supply Pin for Internal Microphone INT I Internal Microphone Input Pin (Mono Input) VCOM O Common Voltage Output Pin, 0.45 x AVDD Bias voltage of ADC inputs and DAC outputs. AVSS Analog Ground Pin AVDD Analog Power Supply Pin PVDD PLL Power Supply Pin PVSS PLL Ground Pin VCOC O Output Pin for Loop Filter of PLL Circuit This pin should be connected to PVSS with one resistor and capacitor in series. NC No Connect. No internal bonding. This pin should be left floating. CAD0 I Chip Address 0 Select Pin PDN I Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initializes the control register. CSN I Chip Select Pin (I2C pin = “L”) CAD1 I Chip Address 1 Select Pin (I2C pin = “H”) CCLK I Control Data Clock Pin (I2C pin = “L”) SCL I Control Data Clock Pin (I2C pin = “H”) CDTI I Control Data Input Pin (I2C pin = “L”) SDA I/O Control Data Input Pin (I2C pin = “H”) CDTO O Control Data Output Pin (I2C pin = “L”) I2C I Control Mode Select Pin “H”: I2C Bus, “L”: 4-wire Serial SDTI I Audio Serial Data Input Pin SDTO O Audio Serial Data Output Pin LRCK I/O Input / Output Channel Clock Pin BICK I/O Audio Serial Data Clock Pin MCKO O Master Clock Output Pin NC No Connect. No internal bonding. This pin should be left floating.

[AK4640] MS0273-E-00 - 9 - No. Pin Name I/O Function NC No Connect. No internal bonding. This pin should be left floating. DVDD Digital Power Supply Pin DVSS Digital Ground Pin XTO O X’tal Output Pin XTI I X’tal Input Pin MCKI I External Master Clock Input Pin M/S I Master / Slave Mode Pin “H” : Master Mode, “L” : Slave Mode SPP O Speaker Amp Positive Output Pin SPN O Speaker Amp Negative Output Pin HVDD Headphone Amp Power Supply Pin HVSS Headphone Amp Ground Pin HPR O Rch Headphone Amp Output Pin HPL O Lch Headphone Amp Output Pin MUTET O Mute Time Constant Control Pin Connected to HVSS pin with a capacitor for mute time constant. MIN I ALC2 Input Pin MOUT2 O Analog Mixing Output Pin NC No Connect. No internal bonding. This pin should be left floating. NC No Connect. No internal bonding. This pin should be left floating. MOUT− O Mono Line Negative Output Pin MOUT+ O Mono Line Positive Output Pin AUXIN− I Mono AUX Negative Input Pin AUXIN+ I Mono AUX Positive Input Pin BEEPM I Mono Beep Signal Input Pin BEEPR I Rch Stereo Beep Signal Input Pin BEEPL I Lch Stereo Beep Signal Input Pin AIN I Analog Input Pin NC No Connect. No internal bonding. This pin should be left floating. Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN−, BEEPM, BEEPL, and BEEPR) should not be left floating. „ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog Input EXT, INT, MIN, AUXIN−, AUXIN+, BEEPM, BEEPR, BEEPL, AIN These pins should be open and each path should be switched off. Analog Output MICOUT, MPE, MPI, VCOC, SPP, SPN, HPR, HPL, MUTET, MOUT2, MOUT−, MOUT+ These pins should be open. Digital Input CAD0, CSN, CCLK, CDTI, I2C, SDTI, LRCK (when M/S pin = “L”), BICK (when M/S pin = “L”), M/S These pins should be connected to DVSS. Digital Output CDTO, SDTO, LRCK (when M/S pin = “H”), BICK (when M/S pin = “H”), MCKO, XTO These pins should be open.

[AK4640] MS0273-E-00 - 10 - ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: Analog AVDD −0.3 4.6 V Digital DVDD −0.3 4.6 V PLL PVDD −0.3 4.6 V Headphone-Amp / Speaker-Amp HVDD −0.3 4.6 V |AVSS – PVSS| (Note 2) ∆GND1 0.3 V |AVSS – DVSS| (Note 2) ∆GND2 0.3 V |AVSS – HVSS| (Note 2) ∆GND3 0.3 V Input Current, Any Pin Except Supplies IIN ±10 mA Analog Input Voltage VINA −0.3 AVDD+0.3 V Digital Input Voltage VIND −0.3 DVDD+0.3 V Ambient Temperature (powered applied) Ta −10 Storage Temperature Tstg −65 150 Note 1. All voltages with respect to ground. Note 2. AVSS, DVSS, PVSS and HVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Symbol min typ max Units Power Supplies Analog AVDD 2.4 3.3 3.6 V (Note 3) Digital DVDD 2.4 3.3 AVDD V PLL PVDD 2.4 3.3 AVDD V HP / SPK-Amp HVDD 2.4 3.3 3.6 V Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD, DVDD, HVDD and PVDD is not critical. When the voltage difference among DVDD, PVDD and AVDD is larger than 0.3V, the power supply current at power down mode increases (see Note 19). When the power supplies are partially powered OFF, the AK4640 must be reset by bringing PDN pin “L” after these power supplies are powered ON again. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4640] MS0273-E-00 - 11 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter min typ max Units MIC Amplifier: Input Resistance kΩ (MGAIN bit = “0”) dB Gain (MGAIN bit = “1”) dB MIC Power Supply: Output Voltage (Note 4) 2.22 2.47 2.72 V Load Resistance kΩ Load Capacitance pF Input PGA Characteristics: Input Resistance (Note 5) kΩ Step Size 0.1 0.5 0.9 dB Gain Control Range +27.5 dB ADC Analog Input Characteristics: MIC Gain=20dB, IPGA=0dB, ALC1=OFF, MIC → IPGA → ADC Resolution Bits Input Voltage (Note 6) 0.168 0.198 0.228 Vpp S/(N+D) (−1dBFS) dBFS D-Range (−60dBFS, A-weighted) dB S/N (A-weighted) dB DAC Characteristics: Resolution Bits Mono Line Output Characteristics: RL=20kΩ, DAC → MOUT+/MOUT− pins Output Voltage MOGN bit = “1”, −17dB 0.31 Vpp (Note 7) MOGN bit = “0”, +6dB 3.56 3.96 4.36 Vpp S/(N+D) (-3dBFS) MOGN bit = “1”, −17dB dBFS MOGN bit = “0”, +6dB dBFS S/N (A-weighted) MOGN bit = “1”, −17dB dB MOGN bit = “0”, +6dB dB Load Resistance MOGN bit = “1”, −17dB kΩ MOGN bit = “0”, +6dB kΩ Load Capacitance pF Note 4. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD(typ). Note 5. When IPGA Gain is changed, this typical value changes between 8kΩ and 11kΩ. Note 6. Input voltage is proportional to AVDD voltage. Vin = 0.06 x AVDD(typ). Note 7. Output voltage is proportional to AVDD voltage. Vout = 1.2 x AVDD(typ)@MOGN bit = “0” at Full-differential output. Vout = 0.6 x AVDD(typ)@MOGN bit = “0” at Single-end Output.

Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.582 x AVDD(typ). Note 10. BEEP-AMP can’t output more than this maximum voltage. Figure 2. Headphone-amp output circuit

[AK4640] MS0273-E-00 - 13 - Parameter min typ max Units Mono Input: MIN pin Maximum Input Voltage (Note 11) 1.98 Vpp Input Resistance (Note 12) kΩ Mono Output: RL=10kΩ, DAC → MIX → MOUT2 pin Output Voltage (Note 13) 1.94 Vpp Load Resistance kΩ Load Capacitance (Note 14) pF AUX Input: AUXIN+, AUXIN− pins Maximum Input Voltage (Note 15) 1.98 Vpp Input Resistance kΩ Step Size dB Gain Control Range −21 +24 dB Power Supplies Power Up (PDN pin = “H”) All Circuit Power-up: AVDD+DVDD (Note 16) mA PVDD 1.2 mA HVDD: HP-AMP Normal Operation No Output (Note 17) mA HVDD: SPK-AMP Normal Operation No Output (Note 18) mA Power Down (PDN pin = “L”) (Note 19) AVDD+DVDD 100 µA PVDD 100 µA HVDD 100 µA Note 11. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ). Note 12. When ALC2 Gain is changed, this typical value changes between 22kΩ and 26kΩ. Note 13. Output Voltage is proportional to AVDD voltage. Vout = 0.588 x AVDD(typ). Note 14. When the output pin drives a capacitive load, a resistor should be added in series between the output pin and capacitive load. Note 15. Maximum Input Voltage is proportional to AVDD voltage. Vin = 0.6 x AVDD(typ). Note 16. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM= PMBPS=PMAUX= “1”, MCKO= “1” and Master Mode. AVDD=10mA (typ.), DVDD=6mA (typ.). AVDD=10mA (typ.), DVDD=4mA (typ.) at MCKO= “0” in Slave Mode. Note 17. PMMIC=PMADC=PMDAC=PMMO=PMHPL=PMHPR=PMVCM=PMPLL= PMXTL=PMBPM=PMBPS= PMAUX= “1” and PMSPK= “0”. Note 18. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMVCM=PMPLL=PMXTL= PMBPM=PMBPS=PMAUX= “1” and PMHPL=PMHPR= “0”. Note 19. All digital input pins are fixed to DVDD or DVSS. When the voltage difference among DVDD, PVDD and AVDD is larger than 0.3V, the power supply current at power down mode increases.

[AK4640] MS0273-E-00 - 14 - FILTER CHARACTERISTICS (Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; fs=44.1kHz; DEM=OFF) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 20) ±0.1dB PB 17.4 kHz −1.0dB 20.0 kHz −3.0dB 21.1 kHz Stopband SB 25.7 kHz Passband Ripple PR ±0.1 dB Stopband Attenuation SA dB Group Delay (Note 21) GD 17.0 1/fs Group Delay Distortion ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 20) −3.0dB FR 3.4 Hz −0.5dB Hz −0.1dB Hz DAC Digital Filter: Passband (Note 20) ±0.1dB PB 19.6 kHz −0.7dB 20.0 kHz −6.0dB 22.05 kHz Stopband SB 25.2 kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA dB Group Delay (Note 21) GD 16.8 1/fs DAC Digital Filter + SCF: Frequency Response: 0 ∼ 20.0kHz FR ±1.0 dB BOOST Filter: (Note 22) MIN 20Hz FR 5.74 dB 100Hz 2.92 dB 1kHz 0.0 dB MID 20Hz FR 5.94 dB 100Hz 4.71 dB 1kHz 0.14 dB MAX 20Hz FR 16.04 dB 100Hz 10.55 dB Frequency Response 1kHz 0.3 dB Note 20. The passband and stopband frequencies scale with fs (system sampling rate). Note 21. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16bit data of both channels from the input register to the output register of the ADC. This time includes the group delay of the HPF. For the DAC, this time is from setting the 16bit data of both channels from the input register to the output of analog signal. Note 22. These frequency responses scale with fs. If a high-level and low frequency signal is input, the analog output clips to the full-scale.

[AK4640] MS0273-E-00 - 15 - DC CHARACTERISTICS (Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V) Parameter Symbol min typ Max Units High-Level Input Voltage VIH 70%DVDD V Low-Level Input Voltage VIL 30%DVDD V Input Voltage at AC Coupling (Note 23) VAC 50%DVDD V High-Level Output Voltage (Iout=−200µA) VOH DVDD−0.2 V Low-Level Output Voltage (Except SDA pin: Iout=200µA) VOL 0.2 V (SDA pin: Iout=3mA) VOL 0.4 V Input Leakage Current Iin ±10 µA Note 23. The external clock is input to MCKI pin via AC coupled capacitor. SWITCHING CHARACTERISTICS (Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency 11.2896 12.288 MHz External Clock Frequency fCLK 2.048 12.288 MHz Pulse Width Low tCLKL 0.4/fCLK ns Pulse Width High tCLKH 0.4/fCLK ns AC Pulse Width (Note 24) tACW 0.4/fCLK ns MCKO Output Frequency fMCK 0.256 12.288 MHz Duty Cycle: except fs=32kHz dMCK fs=32kHz at 256fs (Note 25) dMCK LRCK Timing Frequency fs kHz Duty Cycle Slave mode Duty Master mode Duty Audio Interface Timing Slave mode BICK Period tBCK 312.5 ns BICK Pulse Width Low tBCKL 130 ns Pulse Width High tBCKH 130 ns LRCK Edge to BICK “↑” (Note 26) tLRB ns BICK “↑” to LRCK Edge (Note 26) tBLR ns LRCK to SDTO (MSB) (Except I2S mode) tLRS ns BICK “↓” to SDTO tBSD ns SDTI Hold Time tSDH ns SDTI Setup Time tSDS ns Master mode BICK Frequency (BF bit = “0”) fBCK 64fs Hz (BF bit = “1”) fBCK 32fs Hz BICK Duty dBCK BICK “↓” to LRCK tMBLR −80 ns BICK “↓” to SDTO tBSD −80 ns SDTI Hold Time tSDH ns SDTI Setup Time tSDS ns Note 24. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to ground (Refer to Figure 4). Note 25. PMPLL bit = “1”. Note 26. BICK rising edge must not occur at the same time as LRCK edge.

[AK4640] MS0273-E-00 - 16 - Parameter Symbol min typ max Units Control Interface Timing (4-wire Serial mode): CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL ns Pulse Width High tCCKH ns CDTI Setup Time tCDS ns CDTI Hold Time tCDH ns CSN “H” Time tCSW 150 ns tCSS ns tCSH ns CDTO Delay tDCD ns CSN “↑” to CDTO Hi-Z tCCZ ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency fSCL 100 kHz Bus Free Time Between Transmissions tBUF 4.7 µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 4.0 µs Clock Low Time tLOW 4.7 µs Clock High Time tHIGH 4.0 µs Setup Time for Repeated Start Condition tSU:STA 4.7 µs SDA Hold Time from SCL Falling (Note 27) tHD:DAT µs SDA Setup Time from SCL Rising tSU:DAT 0.25 µs Rise Time of Both SDA and SCL Lines tR 1.0 µs Fall Time of Both SDA and SCL Lines tF 0.3 µs Setup Time for Stop Condition tSU:STO 4.0 µs Pulse Width of Spike Noise Suppressed by Input Filter tSP ns Reset Timing PDN Pulse Width (Note 28) tPD 150 ns PMADC “↑” to SDTO valid (Note 29) tPDV 2081 1/fs Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 28. The AK4640 can be reset by the PDN pin = “L”. Note 29. This is the count of LRCK “↑” from the PMADC bit = “1”. Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.

is greater than 50% of the DVDD level to the XTI pin through a capacitor. external clock is input through a capacitor. Clock isn’t input to MCKI pin. Table 1. Master Clock Status by PMXTL bit and MCKPD bit Figure 13. X’tal mode

and the MCKO bit enables the MCKO output. speaker amps can be avoided by using the mute sequence examples (Figure 51 and Figure 52, respectively). present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”). Table 2. MCKI Input Frequency (PLL Mode) Table 3. Sampling Frequency (PLL Mode) Table 4. MCKO Frequency (PLL Mode, MCKO bit = “1”)

Table 5. Clock Operation at Master Mode (PLL Mode) Table 6. Clock Operation at Slave Mode (PLL Mode) respectively) are available to reduce the click noise of headphone and speaker amps. present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”). Table 7. Sampling Frequency Select (EXT Mode)

Table 8. MCKO Frequency (EXT Mode, MCKO bit = “1”) Table 9. Clock Operation at Master Mode (EXT Mode) Table 10. Clock Operation at Slave Mode (EXT Mode) The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise. through Headphone amp at fs=8kHz is shown in Table 11. Table 11. Relationship between MCKI and S/N of HP-AMP BICK and LRCK must be input separately. Table 12. Master mode/Slave mode

AK4640 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit (Table 14). The typical input impedance is 30kΩ. Table 14. MIC Input Gain resistance is 2kΩ(min). No capacitor must be connected directly to MPI and MPE pins. Figure 19. MIC Power

[AK4640] MS0273-E-00 - 30 - „ Manual Mode The AK4640 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and etc) 2. When the registers for the ALC1 operation (Limiter period, Recovery period and etc) are changed. For example; When the change of the sampling frequency. 3. When IPGA is used as a manual volume. When writing to the IPGA6-0 bits continually, the control register should be written by an interval more than zero crossing timeout. „ MIC-ALC Operation The ALC (Automatic Level Control) of MIC input is done by ALC1 block when ALC1 bit is “1”. (1) ALC1 Limiter Operation When the ALC1 limiter is enabled, and IPGA output exceeds the ALC1 limiter detection level (LMTH), the IPGA value is attenuated by the amount defined in the ALC1 limiter ATT step (LMAT1-0 bits) automatically. When the ZELM bit = “1”, the timeout period is set by the LTM1-0 bits. The operation for attenuation is done continuously until the input signal level becomes LMTH or less. If the ALC1 bit does not change into “0” after completing the attenuation, the attenuation operation repeats while the input signal level equals or exceeds LMTH. When the ZELM bit = “0”, the timeout period is set by the ZTM1-0 bits. This enables the zero-crossing attenuation function so that the IPGA value is attenuated at the zero-detect points of the waveform. (2) ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4640 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ALC1 Recovery Waiting Counter Reset Level”, the ALC1 recovery operation starts. The IPGA value increases automatically during this operation up to the reference level (REF6-0 bits). The ALC1 recovery operation is done at a period set by the WTM1-0 bits. Zero crossing is detected during WTM1-0 period, the ALC1 recovery operation waits WTM1-0 period and the next recovery operation starts. During the ALC1 recovery operation, when Lch or Rch input signal level exceeds the ALC1 limiter detection level (LMTH), the ALC1 recovery operation changes immediately into an ALC1 limiter operation. In the case of (Recovery waiting counter reset level) ≤ (IPGA Output Level) < (Limiter detection level) during the ALC1 recovery operation, the wait timer for the ALC1 recovery operation is reset. Therefore, in the case of (IPGA Output Level) < (Recovery waiting counter reset level), the wait timer for the ALC1 recovery operation starts. The ALC1 operation corresponds to the impulse noise. When the impulse noise is input, the ALC1 recovery operation becomes faster than a normal recovery operation.

Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Table 15. Example of the ALC1 setting operation is finished by ALC1 bit = “0” or PMMIC bit = “0”.

  • LTM1-0, LMTH, LMAT1-0, WTM1-0, ZTM1-0, RATT, REF6-0, ZELM bits IPGA gain at ALC1 operation start can be changed from the default value of IPGA6-0 bits while PMMIC bit is “1” and ALC1 bit is “0”. When ALC1 bit is changed from “1” to “0”, IPGA holds the last gain value set by ALC1 operation. Manual Mode * The value of IPGA should be the same or smaller than REF’s WR (ZTM1-0, WTM1-0, LTM1-0) WR (REF6-0) WR (IPGA6-0) ALC1 Operation WR (ALC1= “1”, LMAT1-0, RATT, LMTH, ZELM) Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms @ fs= 8kHz Limiter and Recovery Step = 1 Maximum Gain = +27.5dB Limiter Detection Level = -4dBFS ALC2 bit = “1” (default) (1) Addr=08H, Data=00H (2) Addr=0AH, Data=47H (4) Addr=09H, Data=61H (3) Addr=0BH, Data=10H Note : WR : Write

Figure 20. Registers set-up sequence at ALC1 operation

de-emphasis filter (Table 16). Table 16. De-emphasis Control output clips to the full scale. Figure 21 shows the boost frequency response at –20dB signal input. Figure 21. Boost Frequency (fs=44.1kHz) Table 17. Low Frequency Boost Control

attenuator has a soft transition function. It takes 1061/fs(24ms@fs=44.1kHz) from 00H(0dB) to FFH(MUTE). Table 18. DATT Attenuation Table is effective for changing the signal source without stopping the signal transmission (Figure 22). The soft mute function is independent of output volume and cascade connected between both functions. Figure 22. Soft Mute Function (1) The output signal is attenuated until -∞ (“0”) by the cycle set by the TM1-0 bits. (2) Analog output corresponding to digital input has the group delay (GD).

Figure 23. AUX Input Table 19. The switching noise occurs when GN3-0 bits are changed. Table 19. AUX Input Gain Setting

is powered up. And when the BPMHP bit is set to “1”, the input signal from the BEEPM pin is mixed to Headphone-amp. while the beep signal is not output. Table 20. BEEP input gain Figure 24. Block Diagram of BEEP pins

Figure 25. Power-up/Power-down Timing for Headphone-amp (1) Headphone-amp power-up (HPL, HPR bit= “0”). The outputs are still HVSS. 100k(typ) x C when the capacitor value on MUTET pin is “C”. 100k(typ) x C when the capacitor value on MUTET pin is “C”. of τ that the common voltage goes to GND.

cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance RL is 16Ω. 10Ω±20% resistor) because it has the possibility that Headphone-amp oscillates. Figure 26. External Circuit Example of Headphone Table 21. External Circuit Example

300mW@ALC2=OFF and 250mW@ALC2=ON at 8Ω load when HVDD = 3.3V. Table 22. SPK-Amp Maximum Output Power PMSPK bit is “0”, the MOUT2, SPP and SPN pins are placed in a Hi-Z state. first entering power-save-mode. Figure 27. Power-up/Power-down Timing for Speaker-amp Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state.

Figure 28. Mono Line Output bit is “0”, the mono line output enters power-down-mode and the output is placed in a Hi-Z state. output. Amp for mono line output has 6dB gain and −17dB gain that are set by the MOGN bit.

circuit, the change period of the ALC2 limiter operation is set by the ROTM bit and the attenuation level is 0.5dB/step. When the input signal is between –5.2dBV and –7.2dBV, the ALC2 limiter or recovery operations are not done. the ALC2 starts after completing the initilization cycle. Table 23. Limiter /Recovery of ALC2 at HVDD=3.3V Figure 29. Speaker-amp Output Level Diagram (HVDD=3.3V, DATT=−8.0dB, ALC2= “1”)

registers is initialized at PDN pin = “L”. Figure 30. Serial Control I/F Timing

[AK4640] MS0273-E-00 - 45 - „ Register Map Addr Register Name 00H Power Management 1 PMVCM PMBPS PMBPM PMMO PMAUX PMMIC PMADC 01H Power Management 2 MCKPD PMXTL PMPLL PMSPK PMHPL PMHPR PMDAC 02H Signal Select 1 MOGN PSMO DAMO MICM BPSSP BPMSP ALCS MOUT2 03H Signal Select 2 DAHS AUXL MICL BPSHP BPMHP HPL HPR 04H Mode Control 1 PLL1 PLL0 PS1 PS0 MCKO BF DIF1 DIF0 05H Mode Control 2 FS2 FS1 FS0 HPM LOOP SPPS 06H DAC Control TM1 TM0 SMUTE DATTC BST1 BST0 DEM1 DEM0 07H MIC Control AUXAD MPWRE MPWRI MICAD MSEL MGAIN 08H Timer Select ROTM ZTM1 ZTM0 WTM1 WTM0 LTM1 LTM0 09H ALC Mode Control 1 ALC2 ALC1 ZELM LMAT1 LMAT0 RATT LMTH 0AH ALC Mode Control 2 REF6 ERF5 REF4 REF3 REF2 REF1 REF0 0BH Input PGA Control IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0 0CH Lch Digital ATT Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 0DH Rch Digital ATT Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 0EH Volume Control ATTM ATTS2 ATTS1 ATTS0 GN3 GN2 GN1 GN0 PDN pin = “L” resets the registers to their default values. Note: Unused bits must contain a “0” value. Note: Only write to address 00H to 0FH.

[AK4640] MS0273-E-00 - 46 - „ Register Definitions Addr Register Name 00H Power Management 1 PMVCM PMBPS PMBPM PMMO PMAUX PMMIC PMADC R/W R/W R/W R/W RD R/W R/W R/W R/W Default PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from “0” to “1”, the initialization cycle (2081/fs=47.2ms@44.1kHz) starts. After initializing, digital data of the ADC is output. PMMIC: MIC In Block Power Control 0: Power down (Default) 1: Power up PMAUX: AUX In Power Control 0: Power down (Default) 1: Power up PMMO: Mono Line Out Power Control 0: Power down (Default) 1: Power up PMBPM: Mono BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBPM= “0”, the path is still connected between BEEPM and HP/SPK-Amp. BPMHP and BPMSP bits should be set to “0” to disconnect these paths, respectively. PMBPS: Stereo BEEP In Power Control 0: Power down (Default) 1: Power up Even if PMBPS= “0”, the path is still connected between BEEPL/R and HP/SPK-Amp. BPSHP and BPSSP bits should be set to “0” to disconnect these paths, respectively. PMVCM: VCOM Block Power Control 0: Power down (Default) 1: Power up Each block can be powered down respectively by writing “0” in each bit. When the PDN pin is “L”, all blocks are powered down. When all bits except MCKPD bit are “0” in the 00H and 01H addresses, all blocks are powered down. The register values remain unchanged. IPGA gain is reset when PMMIC bit is “0” (refer to the IPGA6-0 bits description). When any of the blocks are powered up, the PMVCM bit must be set to “1”. MCKI, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=ALC2 bits = “0” or PDN pin = “L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks.

[AK4640] MS0273-E-00 - 47 - Addr Register Name 01H Power Management 2 MCKPD PMXTL PMPLL PMSPK PMHPL PMHPR PMDAC R/W R/W R/W R/W RD R/W R/W R/W R/W Default PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMHPR: Rch of Headphone-Amp Common Voltage Power Control 0: Power down (Default) 1: Power up PMHPL: Lch of Headphone-Amp Common Voltage Power Control 0: Power down (Default) 1: Power up PMSPK: Speaker Block Power Control 0: Power down (Default) 1: Power up PMPLL: PLL Block Power Control Select 0: EXT Mode and Power down (Default) 1: PLL Mode and Power up PMXTL: X’tal Oscillation Block Power Control 0: Power down (Default) 1: Power up MCKPD: XTI/MCKI pin pull down control 0: Master Clock input enable 1: Pull down by 25kΩ (Default)

[AK4640] MS0273-E-00 - 48 - Addr Register Name 02H Signal Select 1 MOGN PSMO DAMO MICM BPSSP BPMSP ALCS MOUT2 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2) 0: OFF (Default) 1: ON When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs signal at the MOUT2 bit = “1”. This bit is valid at the PMSPK bit = “1”. Hi-Z is output at the PMSPK bit = “0”. ALCS: ALC2 to Speaker-amp Enable 0: OFF (Default) 1: ON ALC2 output signal is mixed to Speaker-amp at the ALCS bit = “1”. BPMSP: BEEPM to Speaker-amp Enable 0: OFF (Default) 1: ON Mono BEEP signal (BEEPM pin) is mixed to Speaker-amp at the BPMSP bit = “1”. BPSSP: BEEPL/BEEPR to Speaker-amp Enable 0: OFF (Default) 1: ON Stereo BEEP signals (BEEPL/BEEPR pins) are mixed to Speaker-amp at the BPSSP bit = “1”. MICM: Switch Control from Mic In to Mono Mixer. 0: OFF (Default) 1: ON IPGA output signal is output through Mono Line Output (MOUT+/MOUT−pins) at the MICM bit = “1”. DAMO: DAC to MOUT+/MOUT− Enable 0: OFF (Default) 1: ON DAC output signal is output through Mono Line Output (MOUT+/MOUT− pins) at the DAMO bit = “1”. PSMO: MOUT+/MOUT− Output Enable (Mixing = (L+R)/2) 0: Power Save Mode (Default) 1: Normal Operation When the PSMO bit = “0”, Mono Line Output is in power save mode and the MOUT+ and MOUT− pins output 0.45 x AVDD voltage. MOGN: Gain control for mono output 0: +6dB (Default) 1: −17dB

Figure 40. Speaker-amp switch control Mono BEEP signal (BEEPM) is mixed to Headphone-amp at the BPMHP bit = “1”. Stereo BEEP signals (BEEPL/BEEPR) is mixed to Headphone-amp at the BPSHP bit = “1”. IPGA output signal is mixed to Headphone-amp and MOUT2 at the MICL bit = “1”. AUX input signal is mixed to Headphone-amp and MOUT2 at the AUXL bit = “1”.

DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = “1”. Figure 41. Headphone-amp switch control

[AK4640] MS0273-E-00 - 51 - Addr Register Name 04H Mode Control 1 PLL1 PLL0 PS1 PS0 MCKO BF DIF1 DIF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default DIF1-0: Audio Interface Format Select (Table 13) Default: “10” (ADC: I2S, DAC: I2S) BF: BICK frequency Select at Master Mode 0: 64fs (Default) 1: 32fs This bit is invalid in slave mode. MCKO: Master Clock Output Enable 0: Disable (Default) 1: Enable PS1-0: Output Master Clock Select (Table 4, Table 8) Default: “00” (256fs) PLL1-0: Input Master Clock Select at PLL Mode (Table 2) Default: “00” (12.288MHz)

[AK4640] MS0273-E-00 - 52 - Addr Register Name 05H Mode Control 2 FS2 FS1 FS0 HPM LOOP SPPS R/W R/W R/W R/W RD RD R/W R/W R/W Default SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-Z and SPN pin is set to HVDD/2 voltage. When the PMSPK bit = “1”, this bit is valid. After the PDN pin changes from “L” to “H”, the PMSPK bit is “0”, which powers down Speaker-amp LOOP: Loopback ON/OFF 0: OFF (Default) 1: ON When this bit is “1”, the ADC output is passed to the DAC input internally. The external input data to DAC is ignored. HPM: Mono output select of Headphone 0: Stereo (Default) 1: Mono When the HPM bit = “1”, (L+R)/2 signals are output to Lch and Rch of the Headphone-amp. FS2-0: Sampling frequency modes (Table 3, Table 7) Default: “000” (fs=44.1kHz)

when the ATTL7-0 bits are written. Soft mute operation is independent of digital attenuator and is performed in the digital domain. Table 24. Soft Mute Time Setting

[AK4640] MS0273-E-00 - 54 - Addr Register Name 07H MIC/HP Control AUXAD MPWRE MPWRI MICAD MSEL MGAIN R/W RD RD R/W R/W R/W R/W R/W R/W Default MGAIN: 1st Mic-amp Gain control 0: 0dB 1: +20dB (Default) MSEL: Microphone select 0: Internal MIC (Default) 1: External MIC MICAD: Switch Control from Mic In to ADC 0: OFF (Default) 1: ON ALC1 output signal is input to ADC when MICAD bit = “1”. MPWRI: Power Supply Control for Internal Microphone 0: OFF (Default) 1: ON The setting of MPWRI is enabled when PMMICL bit = “1”. MPWRE: Power Supply for External Microphone 0: OFF (Default) 1: ON The setting of MPWRE is enabled when PMMICL bit = “1”. AUXAD: Switch Control from AUX IN to ADC. 0: OFF (Default) 1: ON AUX input signal is input to ADC when AUXAD bit = “1”.

by the period specified by the LTM1-0 bits. Default is “00” (0.5/fs). Table 25. ALC1 Limiter Operation Period at zero crossing disable (ZELM bit = “1”) A period of recovery operation when any limiter operation does not occur during the ALC1 operation. Table 26. ALC1 Recovery Operation Waiting Period ALC1 recovery operation or ALC1 limiter operation (ZELM bit = “0”). Table 27. Zero Crossing Timeout Period

The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about ±2dB. Table 28. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level exceeds the reference level (REF6-0 bits), the IPGA value does not increase. Table 29. ALC1 Recovery Gain Step Setting value exceeds IPGA = “00” (−8dB), it clips to “00”. Table 30. ALC1 Limiter ATT Step Setting recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.

Level”, the IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”. Table 31. Setting Reference Value at ALC1 Recovery Operation

When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is “0”. out regardless the actual gain. Table 32. Input Gain Setting

Table 33. Attenuation Table

[AK4640] MS0273-E-00 - 62 - 1. Grounding and Power Supply Decoupling The AK4640 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD, PVDD and HVDD are supplied separately, the correct power up sequence should be observed. AVSS, DVSS, PVSS and HVSS of the AK4640 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4640 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4640. 3. Analog Inputs The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (approx. 0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2πRC). The AK4640 can accept input voltages from AVSS to AVDD. 4. Analog Outputs The input data format for the DAC is 2’s complement. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). Mono output from the MOUT2 pin and Mono Line Output from the MOUT+ and MOUT− pins are centered at 0.45 x AVDD. The Headphone-Amp and Speaker-Amp outputs are centered at HVDD/2.

supplies are powered ON again. Set the following registers to establish the initial condition. Figure 44. Power Up Sequence “L” time of 150ns or more is needed to reset the AK4640. VCOM should first be powered up before the other block operates. Set the MOUT2 and ALCS bits to “1” when using the Speaker-amp.

  • DIF1-0 bits set the audio interface format.
  • BF bit sets BICK output frequency in master mode.
  • PLL1-0 bits set MCKI input frequency in PLL mode.

When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCKI, BICK and LRCK) must be supplied.

  1. When X'tal is used in PLL mode. (Slave mode)

Figure 45. Clock Set Up Sequence(1) the same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”. This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”. (4) MCKO is output after PLL becomes stable. (5) Input BICK and LRCK synchronized with the MCKO output.

  1. When X'tal is used in PLL mode. (Master mode)

Figure 46. Clock Set Up Sequence(2) the same time, the PLL does not start. It takes X’tal oscillator 20ms(typ) to be stable after PMXTL bit= “1”. This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0” → “1”. (4) MCKO, BICK and LRCK are output after PLL lock time.

  1. When an external clock is used in PLL mode. (Slave mode)

Figure 47. Clock Set Up Sequence(3) PLL needs 40ms lock time after the PMPLL bit = “0” → “1”. (5) MCKO is output after PLL lock time. (6) Input BICK and LRCK that synchronized in the MCKO output.

Figure 50. MIC Input Recording Sequence This sequence is an example of ALC1 setting in the case that fs=8kHz and ALC1 operation starts from IPGA=0dB. At first, clocks should be supplied according to “Clock Set Up” sequence. powered-up in consideration of PLL lock time after a sampling frequency is changed. The initialization cycle time of ADC is 2081/fs=47.2ms@fs=44.1kHz. bit is “0”, and then IPGA operation starts from the default value when PMMIC is changed to “1”.

X ’ta l a n d P L L a re u s e d . Figure 51. Headphone-Amp Output Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used. At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level. Output voltage of headphone-amp is still HVSS. pin. When this capacitor value is 1.0µF, the time constant is τr = 100ms(typ). pin. When this capacitor value is 1.0µF, the time constant is τf = 100ms(typ). GND, some click noise occurs. It takes 2times of τf that the common voltage goes to GND.

X ’ta l a n d P L L a re u s e d . Figure 52. Speaker-Amp Output Sequence At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS2-0 bits) if PLL mode is used. At DATTC bit = “1”(default), ATTL7-0 bits of Address 0CH control both Lch and Rch attenuation level. SPPS bit should be set to “1” at more than 1ms after PMSPK bit is set to “1”. The initializing time of Speaker-amp is 2048/fs=46.4ms@fs=44.1kHz.

Figure 55. Stop of Clock Sequence(3) AK4640 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized.

[AK4640] MS0273-E-00 - 73 - PACKAGE (AK4640VG) 57pin BGA (Unit: mm) 5.0 ± 0.1 5.0 ± 0.1 0.5 A B C D E F G 7 6 5 4 3 2 1 57 - φ 0.3 ± 0.05 H J 9 8 0.08 S S φ 0.05 AB S B 0.5 M A 4.0 1.0MAX 0.25 ± 0.05 „ Material & Lead finish Package molding compound: Epoxy Interposer material: BT resin Solder ball material: SnAgCu

[AK4640] MS0273-E-00 - 74 - PACKAGE (AK4640VN) 52pin QFN (Unit: mm) 7.2 ± 0.20 7.2 ± 0.20 0.30 ± 0.10 7.0 ± 0.10 7.0 ± 0.10 0.21 ± 0.05 0.60 ± 0.10 0.05 0.02 + 0.03 - 0.02 0.78 + 0.17 - 0.28 0.80 + 0.20 - 0.00 0.20 + 0.10 - 0.20 45° 45° 0.05 M 4 - C0.6 0.18 ± 0.05 0.40 Note) The part of black at four corners on reverse side must not be soldered and must be open. „ Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb free)

[AK4640] MS0273-E-00 - 75 - MARKING (AK4640VG) 4640 XXXX XXXX: Date code (4 digit) Pin #1 indication

[AK4640] MS0273-E-00 - 76 - MARKING (AK4640VN) AK4640VN XXXXXXX AKM XXXXXXX : Date code identifier (7 digits)

Revision History

Date (YY/MM/DD) Revision Reason Page

Contents

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