AK4629 AKM | Alldatasheet
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Technical content
[AK4629] GENERAL DESCRIPTION The AK4629 is a single chip audio CODEC that includes four ADC channels and eight DAC channels. The converters are designed with Enhanced Dual Bit architecture for the ADC’s, and Advanced Multi-Bit architecture for the DAC, enabling very low noise performance. The AK4629 ADC supports both single-ended and differential inputs and outputs. A wide range of applications can be realized, including home theater, pro audio and car audio. The AK4629 is available in a 48-pin LQFP package.
FEATURES
4ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-ended / Differential Input - S/(N+D): 92dB (Single-ended, Differential) - Dynamic Range, S/N: 102dB (Single-ended), 103dB (Differential) - Digital HPF for offset cancellation - I/F format: MSB justified, I2S or TDM 8ch 24bit DAC - 128x Oversampling - Sampling Rate up to 192kHz - 24bit 8 times Digital Filter - Single-ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM - Individual channel digital volume with 128 levels and 0.5dB step - Soft mute - De-emphasis for 32kHz, 44.1kHz and 48kHz - Zero Detect Function High Jitter Tolerance TTL Level Digital I/F 3-wire Serial and I2C Bus µP I/F for mode setting Master clock: 256fs, 384fs or 512fs for fs=32kHz to 48kHz 128fs, 192fs or 256fs for fs=64kHz to 96kHz 128fs for fs=120kHz to 192kHz Power Supply: 4.5 to 5.5V Power Supply for output buffer: 2.7 to 5.5V Small 48pin LQFP High Performance Multi-channel Audio CODEC AK4629 MS1277-E-02 2012/03 - 1 -
[AK4629] ■ Block Diagram Audio I/F LPF DAC DATT LPF DAC DATT LPF DAC DATT LPF DAC DATT LOUT1 ROUT1 LOUT2 ROUT2 AK4629 ADC HPF ADC HPF LIN1+/LIN1 LRCK BICK SDTI1 SDTI2 SDTI3 MCLK LRCK BICK SDIN1 SDIN2 SDIN3 MCLK LPF DAC DATT LPF DAC DATT LOUT3 ROUT3 ADC HPF ADC HPF SDTO1 SDTO1 SDTO2 SDTO2 LIN1- RIN1+/RIN1 RIN1- LIN2+/LIN2 LIN2- RIN2+/RIN2 RIN2- SDTI4 SDIN4 LPF DAC DATT LPF DAC DATT LOUT4 ROUT4 Block Diagram MS1277-E-02 2012/03 - 2 -
[AK4629] ■ Ordering Guide A K 4 6 2 9 V Q - 4 0 ∼ +105°C 48pin LQFP(0.5mm pitch) AKD4629 Evaluation Board for AK4629 ■ Pin Layout VSS2 LIN1+/LIN1
38 RIN2+/RIN2
39 LIN2-
40 LIN2+/LIN2
41 RIN1-
45 TST1
46 SGL
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[AK4629] PIN/FUNCTION No. Pin Name I/O Function
1 CAD0 I Chip Address 0 Pin
2 CAD1 I Chip Address 1 Pin
PS I Parallel/Serial Select Pin 3 “L”: Serial control mode, “H”: Parallel control mode
4 SDTO1 O ADC1 Audio Serial Data Output Pin
5 SDTO2 O ADC2 Audio Serial Data Output Pin
TVDD - 6 Output Buffer Power Supply Pin, 2.7V∼5.5V DVDD - 7 Digital Power Supply Pin, 4.5V∼5.5V
8 VSS1 - Digital Ground Pin, 0V
TDM0 I TDM I/F Format Mode Pin in parallel control mode “L”: Normal mode, “H”: TDM mode 9 SDA/CDTI I/O Control Data Input Pin in serial control mode I2C pin= “L”: CDTI (3-wire Serial), I2C pin= “H”: SDA (I2C Bus) DIF1 I Audio Data Interface Format 1 Pin in parallel control mode
10 SCL/CCLK I Control Data Clock Pin in serial control mode
I2C pin= “L”: CCLK (3-wire Serial), I2C pin= “H”: SCL (I2C Bus) DIF0 I Audio Data Interface Format 0 Pin in parallel control mode
11 CSN I Chip Select Pin in 3-wire serial control mode
This pin should be connected to DVDD at I2C bus control mode PDN I Power-Down & Reset Pin When “L”, the AK4629 is powered-down and the control registers are reset to default state. If the state of the PS pin or CAD1-0 changes, then the AK4629 must be reset by the PDN pin.
13 MCLK I Master Clock Input Pin
14 BICK I Audio Serial Data Clock Pin
15 LRCK I Input Channel Clock Pin
16 SDTI1 I DAC1 Audio Serial Data Input Pin
17 SDTI2 I DAC2 Audio Serial Data Input Pin
18 SDTI3 I DAC3 Audio Serial Data Input Pin
19 SDTI4 I DAC4 Audio Serial Data Input Pin
DFS0 I Double Speed Sampling Mode Pin (Note 1) 20 “L”: Normal Speed, “H”: Double Speed I2C I Control Mode Select Pin (PS pin = “L”) “L”: 3-wire Serial, “H”: I2C Bus 21 TST6 I Test Pin (PS pin = “H”) This pin should be connected to VSS1 TST2 Test Pin 22 This pin should be connected to VSS1.
23 LOUT4 O DAC4 Lch Analog Output Pin
24 ROUT4 O DAC4 Rch Analog Output Pin
25 LOUT3 O DAC3 Lch Analog Output Pin
26 ROUT3 O DAC3 Rch Analog Output Pin
27 LOUT2 O DAC2 Lch Analog Output Pin
28 ROUT2 O DAC2 Rch Analog Output Pin
29 LOUT1 O DAC1 Lch Analog Output Pin
30 ROUT1 O DAC1 Rch Analog Output Pin
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[AK4629] No. Pin Name I/O Function VCOM O Common Voltage Output Pin, AVDD/2 31 Large external capacitor around 2.2µF is used to reduce power-supply noise.
32 VREFH I Positive Voltage Reference Input Pin, AVDD
AVDD - 33 Analog Power Supply Pin, 4.5V∼5.5V
34 VSS2 - Analog Ground Pin, 0V
35 DZF1 O Zero Input Detect 1 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to “H”. It always is in “L” when PS pin is “H”.
36 DZF2 O Zero Input Detect 2 Pin (Note 2)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. And when RSTN bit is “0”, PWDAN pin is “L”, this pin goes to “H”. It always is in “L” when PS pin is “H”.
37 RIN2- I ADC2 Rch Analog Negative Input Pin (SGL pin = “L”)
RIN2+ I ADC2 Rch Analog Positive Input Pin (SGL pin = “L”) 38 RIN2 I ADC2 Rch Analog Input Pin (SGL pin = “H”)
39 LIN2- I ADC2 Lch Analog Negative Input Pin (SGL pin = “L”)
LIN2+ ADC2 Lch Analog Positive Input Pin (SGL pin = “L”) 40 LIN2 I ADC2 Lch Analog Input Pin (SGL pin = “H”)
41 RIN1- I ADC1 Rch Analog Negative Input Pin (SGL pin = “L”)
RIN1+ I ADC1 Rch Analog Positive Input Pin (SGL pin = “L”) 42 RIN1 I ADC1 Rch Analog Input Pin (SGL pin = “H”)
43 LIN1- I ADC1 Lch Analog Negative Input Pin (SGL pin = “L”)
LIN1+ I ADC1 Lch Analog Positive Input Pin (SGL pin = “L”) 44 LIN1 I ADC1 Lch Analog Input Pin (SGL pin = “H”)
45 TST1 I Test Pin
This pin should be connected to VSS1. 46 SGL I Single-ended Input Mode Select Pin. “L”: ADC Differential Input Mode “H”: ADC Single-ended Input Mode
47 DZFE I Zero Input Detect Enable Pin
“L”: mode 7 (disable) at parallel mode, zero detect mode is selectable by DZFM3-0 bits at serial mode “H”: mode 0 (DZF1 is AND of all six channels)
48 SMUTE I Soft Mute Pin (Note 1)
When this pin goes to “H”, soft mute cycle is initialized. When returning to “L”, the output mute releases. Note 1. SMUTE and DFS0 pins are ORed with register data when the PS pin= “L”. Note 2. The output pin (DZF1 and DZF2) of zero detection results of each lineout channels can be selected by DZFM3-0 bits when the PS pin and DZFE pin= “L”. (Table 11) Note 3. All digital input pins except for pull-down should not be left floating. MS1277-E-02 2012/03 - 5 -
[AK4629] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 4) Parameter Symbol min max Unit Power Supplies Analog AVDD -0.3 6.0 V Digital DVDD -0.3 6.0 V Output buffer TVDD -0.3 6.0 V Input Current (any pins except for supplies) IIN - mA ±10 Analog Input Voltage VINA -0.3 AVDD+0.3 V Digital Input Voltage VIND -0.3 DVDD+0.3 V Ambient Temperature (power applied) (Note 6) Ta -40 105 °C Storage Temperature Tstg -65 150 °C Note 4. All voltages with respect to ground. Note 5. VSS1 and VSS2 must be connected to the same analog ground plane. Note 6. In case that PCB wiring density is 100% or more. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 4) Parameter Symbol min typ max Unit Power Supplies Analog AVDD 4.5 5.0 5.5 V (Note 7) Digital DVDD 4.5 5.0 5.5 V Output buffer TVDD 2.7 5.0 5.5 V Note 4. All voltages with respect to ground. Note 7. The power up sequence between AVDD, DVDD and TVDD is not critical. Do not turn off only the AK4629 under the condition that a surrounding device is powered on and the I2C bus is in use. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1277-E-02 2012/03 - 6 -
[AK4629] ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=TVDD=5V; VSS1=VSS2=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Unit ADC Analog Input Characteristics (Single-ended Inputs) Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz 84 96 dB fs=96kHz - 92 dB DR (-60dBFS) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 99 dB fs=96kHz, A-weighted 93 105 dB S/N (Note 11) fs=48kHz, A-weighted 94 102 dB fs=96kHz 88 99 dB fs=96kHz, A-weighted 93 105 dB Interchannel Isolation 90 110 dB DC Accuracy (Single-ended Inputs) Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 - ppm/°C Input Voltage AIN=0.68xVREFH 3.2 3.4 3.6 Vpp fs=48kHz 10 14 kΩ Input Resistance fs=96kHz 11 kΩ Power Supply Rejection (Note 9) 50 dB ADC Analog Input Characteristics (Differential inputs) 84 96 dB S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz - 94 dB 95 103 dB 89 100 dB DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted 94 106 dB 95 103 dB 89 100 dB S/N (Note 11) fs=48kHz, A-weighted fs=96kHz fs=96kHz, A-weighted 94 106 dB Interchannel Isolation 90 110 dB DC Accuracy (Differential inputs) Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 - ppm/°C Input Voltage AIN=0.68xVREFH (Note 8) ±3.2 ±3.4 ±3.6 Vpp fs=48kHz 22 32 kΩ Input Resistance fs=96kHz 19 kΩ Power Supply Rejection (Note 9) 50 - dB Common Mode Rejection Ratio (CMRR) (Note 10) 60 dB MS1277-E-02 2012/03 - 7 -
[AK4629] DAC Analog Output Characteristics Resolution 24 Bits S/(N+D) (0dBFS) fs=48kHz 80 98 dB fs=96kHz 78 98 dB fs=192kHz - 98 dB DR (-60dBFS) fs=48kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB fs=192kHz - 100 dB fs=192kHz, A-weighted - 106 dB S/N (Note 12) fs=48kHz, A-weighted 95 106 dB fs=96kHz 88 100 dB fs=96kHz, A-weighted 94 106 dB fs=192kHz - 100 dB fs=192kHz, A-weighted - 106 dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 - ppm/°C Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp Load Resistance 5 kΩ Load Capacitance 25 pF Power Supply Rejection (Note 10) 50 dB Note 8. (LIN+) – (LIN-) or (RIN+) – (RIN-); this value is proportional to VREFH voltage. Note 9. PSR is applied to AVDD, DVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held +5V. Note 10. VREFH is held +5V, the input bias voltage is set to AVDD1, AVDD2 x 0.5. The 1kHz, 1.52Vpp signal is applied to LIN- and LIN+ with same phase (e.g. shorted) or RIN- and RIN+. The CMRR is measured as the attenuation level from 1.52Vpp = -7dBFS. Note 11. S/N measured by CCIR-ARM is 98dB(@fs=48kHz). Note 12. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). Parameter min typ max Unit Power Supplies Power Supply Current (AVDD+DVDD+TVDD) Normal Operation (PDN = “H”) AVDD fs=48kHz, 96kHz 57 86 mA fs=192kHz 34 51 mA DVDD+TVDD fs=48kHz (Note 13) 19 29 mA fs=96kHz 27 40 mA fs=192kHz 27 40 mA Power-down mode (PDN = “L”) (Note 14) 80 200 μA Note 13. TVDD=0.1mA(typ). Note 14. In the power-down mode. All digital input pins including clock pins (MCLK, BICK, LRCK) are held VSS1. MS1277-E-02 2012/03 - 8 -
[AK4629] FILTER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min typ max Unit ADC Digital Filter (Decimation LPF): PB 0 18.9 kHz Passband (Note 15) ±0.1dB - 20.0 - kHz -0.2dB - 23.0 - kHz -3.0dB Stopband SB 28 kHz Passband Ripple PR dB ±0.04 Stopband Attenuation SA 68 dB Group Delay (Note 16) GD 16 1/fs Group Delay Distortion 0 ΔGD μs ADC Digital Filter (HPF): ) Frequency Response (Note 15 -3dB FR 1.0 Hz -0.1dB 6.5 Hz DAC Digital Filter: Passband (Note 15) -0.1dB PB 0 21.8 kHz -6.0dB - 24.0 - kHz Stopband SB 26.2 kHz Passband Ripple PR dB ±0.02 Stopband Attenuation SA 54 dB Group Delay (Note 16) GD 19.2 1/fs DAC Digital Filter + Analog Filter: FR dB ±0.2 Frequency Response: 0 ∼ 20.0kHz FR dB 40.0kHz (Note 17) ±0.3 FR dB 80.0kHz (Note 17) ±1.0 Note 15. The passband and stopband frequencies scale with fs. For example, 21.8kHz at –0.1dB is 0.454 x fs. Note 16. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. Note 17. 40.0kHz; fs=96kHz , 80.0kHz; fs=192kHz. DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min typ max Unit High-Level Input Voltage VIH 2.2 - - V Low-Level Input Voltage VIL - - 0.8 V High-Level Output Voltage (SDTO1-2 pins: Iout=-100μA) VOH TVDD-0.5 - - V (DZF1, DZF2 pins: Iout=-100μA) VOH AVDD-0.5 - - V Low-Level Output Voltage (SDTO1-2, DZF1, DZF2 pins: Iout= 100μA) VOL - - 0.5 V (SDA pin: Iout= 3mA) VOL - - 0.4 V Input Leakage Current Iin - - ±10 μA MS1277-E-02 2012/03 - 9 -
[AK4629] MS1277-E-02 2012/03 - 10 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=DVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min typ max Unit Master Clock Timing 256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd, 128fsq: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 8.192 12.288 16.384 12.288 18.432 24.576 MHz ns ns MHz ns ns MHz ns ns LRCK Timing Normal mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 128 192 kHz kHz kHz TDM256 mode (TDM0= “1”, TDM1= “0”) LRCK frequency “H” time “L” time fsn tLRH tLRL 1/256fs 1/256fs kHz ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) LRCK frequency “H” time “L” time fsn tLRH tLRL 1/128fs 1/128fs kHz ns ns Audio Interface Timing Normal mode (TDM0= “0”, TDM1= “0”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) LRCK to SDTO(MSB) BICK “↓” to SDTO1-2 SDTI1-4 Hold Time SDTI1-4 Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS ns ns ns ns ns ns ns ns ns ns TDM256 mode (TDM0= “1”, TDM1= “0”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTO1 SDTI1 Hold Time SDTI1 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS ns ns ns ns ns ns ns ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 18) BICK “↑” to LRCK Edge (Note 18) BICK “↓” to SDTO1 SDTI1-2 Hold Time SDTI1-2 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS ns ns ns ns ns ns ns ns ns Note 18. BICK rising edge must not occur at the same time as LRCK edge.
[AK4629] Parameter Symbol min typ max Unit Control Interface Timing (3-wire Serial mode): CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTI Setup Time tCDS 40 ns CDTI Hold Time tCDH 40 ns CSN “H” Time tCSW 150 ns CSN “↓” to CCLK “↑” tCSS 50 ns CCLK “↑” to CSN “↑” tCSH 50 ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 19) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0.1 0.6 kHz400 μs - μs - μs - μs - μs - μs - μs - μs 1.0 μs 0.3 μs - ns 50 pF 400 Power-down & Reset Timing PDN Pulse Width (Note 20) tPD 150 ns PDN “↑” to SDTO1-2 valid (Note 21) tPDV 522 1/fs Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 20. The AK4629 can be reset by bringing the PDN pin “L” to “H” upon power-up. Note 21. These cycles are the number of LRCK rising from the PDN pin rising edge. Note 22. I2C-bus is a trademark of NXP B.V. MS1277-E-02 2012/03 - 11 -
[AK4629] ■ Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fsn, 1/fsd LRCK VIH VIL tBCK tBCKL VIH tBCKH BICK VIL Clock Timing (TDM0 bit= “0”) 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fs LRCK VIH VIL tLRLtLRH tBCK tBCKL VIH tBCKH BICK VIL Clock Timing (TDM0 bit= “1”) MS1277-E-02 2012/03 - 12 -
[AK4629] tLRB LRCK VIH BICK VIL tLRS SDTO 50%TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Audio Interface Timing (TDM0 bit= “0”) tLRB LRCK VIH BICK VIL SDTO 50%TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Audio Interface Timing (TDM0 bit= “1”) MS1277-E-02 2012/03 - 13 -
[AK4629] tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R/W A4 tCCKL tCCKH tCDS tCDH WRITE Command Input Timing (3-wire Serial mode) CSN VIH CCLK VIL VIH CDTI VIL VIH VIL D3 D2 D1 D0 tCSW tCSH WRITE Data Input Timing (3-wire Serial mode) tHIGH SCL SDA VIH tLOW tBUF tHD:STA tR tF tHD: DAT tSU:DAT tSU:STA Stop Start Start Stop tSU:STO VIL VIH VIL tSP I2C Bus mode Timing tPD VIL PDN tPDV SDTO 50%TVDD VIH Power-down & Reset Timing MS1277-E-02 2012/03 - 14 -
it is not necessary to set DFS bits. mode, and the analog output goes to VCOM (typ). When MCLK and LRCK are input again, the AK4629 is powered up. After exiting reset following power-up, the AK4629 is not fully operational until MCLK and LRCK are input. Table 1. Sampling Speed (Manual Setting Mode) Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
Table 5. Sampling Speed (Auto Setting Mode) Table 6. System Clock Example (Auto Setting Mode) Figure 1. Differential Input (SGL pin = “L”) Figure 2. Single-ended Input (SGL pin = “H”)
DEMB1-0, DAC3: DEMC1-0, DAC4: DEMD1-0 see “Register Definitions”).
1 Normal Speed 0 1 OFF
2 Normal Speed 1 0 48kHz
3 Normal Speed 1 1 32kHz
Table 7. De-emphasis control and scales with sampling rate (fs).
the falling edge of BICK and the SDTI1-4 are latched on the rising edge of BICK. Mode 2, 3, 6, 7, 10, 11 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs. Table 8. Audio data formats (Normal mode) Table 9. In all modes the serial data is MSB-first, 2’s complement format. The SDTO1 is clocked out on the falling edge of BICK and the SDTI1 is latched on the rising edge of BICK. LOOP1-0 bits should be set to “0” at the TDM mode. and TDM1 register should be set to “1” if Double Speed Mode is selected in TDM128 Mode. Table 9. Audio data formats (TDM256 mode) Table 10. Audio data formats (TDM128 mode)
Figure 3. Mode 0 Timing Figure 4. Mode 1 Timing
0 Don’t Care
Figure 5. Mode 2 Timing Figure 6. Mode 3 Timing
256 BICK
32 BICK
32 BIC K
32 BICK 32 BICK
Figure 7. Mode 4 Timing Figure 8. Mode 5 Timing Figure 9. Mode 6 Timing Figure 10. Mode 7 Timing
128 BICK
Figure 11. Mode 8 Timing Figure 12. Mode 9 Timing Figure 13. Mode 10 Timing
Figure 14. Mode 11 Timing
channels and the DZF2 pin is disabled (“L”) at mode 0. Table 11. Zero detect control
be set by each ATT7-0 bits (Table 12). Table 12. Attenuation level of digital attenuator values is soft transition. Therefore, the switching noise does not occur in the transition. Table 13. Transition time between set values of ATT7-0 bits RSTN bit= “0”. When RSTN bit return to “1”, the ATTs fade to their current value. Note: The attenuation level is calculated in 11bit accuracy.
level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. Figure 15. Soft mute and zero detection power-down mode until MCLK and LRCK are input.
be made after power-up. In case of ADC, an analog initialization cycle star ts after exiting th e power-down mode. shows the power-down/up sequences. the click noise influences system applications. (1) The analog part of ADC is initialized after exiting the power-down state. (2) The analog part of DAC is initialized after exiting the power-down state. (4) ADC outputs “0” data in power-down state. influences system application. (6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN. (7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4629 should be in the power-down mode. (8) DZF pins are “L” in power-down mode (PDN pin= “L”). (9) Mute the analog output externally if the click noise (6) influences system application. Figure 16. Power-down/up sequence example
(1) The analog part of the ADC is initialized after exiting reset state. (3) ADC outputs “0” data in power-down state. influences system application. (5) The analog outputs become VCOM voltage. noise is output even if “0” data is input. be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed. (8) The DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”. (9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”. Figure 17. Reset Sequence Example
VCOM voltage during this initializing cycle. Figure 18 shows the reset sequence by clock stop. (1) The analog section of the ADC is initialized after exiting reset state. (2) The analog section of the DAC is initialized after exiting reset state. input have group delay (GD). (4) ADC output is “0” data during reset. (6) Click noise occurs within 20usec from MCLK, LRCK or BICK stop/start. (7) DZF1-2 pins output “L” during reset. (8) Mute the analog output externally if click noise (6) influences system applications. Figure 18. Reset 2 Sequence Example
“0”, if click noise aversely affects system performance. Figure 20 shows the power-down/up sequences by PDDA1-4 bits. (2) Analog outputs of the DAC when powered down by PDDA1-4 bits = “1” are fixed to the VCOM voltage. not reflected to DZF1-2 pins. (5) DZF detection of the DAC which is in power-down mode is ignored, and DZF1-2 pins become “H”. Figure 20. DAC partial power-down example
The AK4629’s functions are controlled through registers. The registers may be written by two types of control modes. initialized. When the PS pin state is changed, the AK4629 should be reset by the PDN pin.
- Writing to control register is invalid when the PDN pin = “L”.
CSN. The clock speed of CCLK is 5MHz(max).
- The AK4629 does not support read commands in 3wire serial control mode.
Figure 21. 3-wire Serial Control I/F Timing
[AK4629] ■ Mapping of Program Registers Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 0 0 TDM1 TDM0 DIF1 DIF0 0 SMUTE 01H Control 2 0 DFS1 LOOP1 LOOP0 0 DFS0 ACKS 0 02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0 09H ATT speed 0 PDDA4 ATS1 ATS0 PDDA3 PDDA2 PDDA1 RSTN & Power Down Control 0AH Zero detect 0 DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN 0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0DH Power Down Control 0 0 0 0 0 0 PDAD2 PDAD1 Note: For addresses 0EH and 0FH, data must not be written. When the PDN goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized to their default values. SMUTE and DFS0 bits are ORed with pins. MS1277-E-02 2012/03 - 35 -
[AK4629] ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 0 0 TDM1 TDM0 DIF1 DIF0 0 SMUTE Default 0 0 0 0 1 0 0 0 SMUTE: Soft Mute Enable 0: Normal operation 1: All DAC outputs soft-muted Register bit of SMUTE is ORed with the SMUTE pin when the PS pin= “L”. DIF1-0: Audio Data Interface Modes ( Table 8, Table 9, Table 10) Initial: “10”, mode 2 TDM1-0: TDM Format Select ( Table 8, Table 9, Table 10) Mode TDM1 TDM0 Data Output Pins Data Input Pins Sampling Speed 0 0 0 SDTO1-2 SDTI1-3 Normal, Double, Quad Speed 1 0 1 SDTO1 SDTI1 Normal Speed 2 1 0 - - N/A 3 1 1 SDTO1 SDTI1-2 Normal, Double Speed (N/A: Not Available) MS1277-E-02 2012/03 - 36 -
[AK4629] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 0 DFS1 LOOP1 LOOP0 0 DFS0 ACKS 0 Default 0 0 0 0 0 0 0 0 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS bits are ignored. When this bit is “0”, DFS0 and DFS1 bits set the sampling speed mode. DFS1-0: Sampling speed mode ( Table 1) Register bit of DFS0 is ORed with DFS0 pin when the PS pin= “L”. The settings of DFS bits are ignored at ACKS bit “1”. LOOP1-0: Loopback mode enable 00: Normal (No loop back) 0 1 : L I N 1 → LOUT1, LOUT2, LOUT3, LOUT4 RIN1 → ROUT1, ROUT2, ROUT3, ROUT4 The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-4 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting is for mode3. (Table 8) 1 0 : S D T I 1 ( L ) → SDTI2(L), SDTI3(L), SDTI4(L) S D T I 1 ( R ) → SDTI2(R), SDTI3(R), SDTI4(R) In this mode the input DAC data to SDTI2-4 is ignored. 1 1 : L I N 2 → LOUT1, LOUT2, LOUT3, LOUT4 RIN2 → ROUT1, ROUT2, ROUT3, ROUT4 The digital ADC output is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-4 is ignored. In loopback mode, the actual audio format is forced to mode2 when the SDTO audio format setting is for mode0/1/2, and the actual audio format is forced to mode3 when the setting is for mode3. (Table 8) MS1277-E-02 2012/03 - 37 -
[AK4629] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 03H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 06H LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0BH LOUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0CH ROUT4 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Default 0 0 0 0 0 0 0 0 ATT7-0: Attenuation Level ( Table 12) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H De-emphasis DEMD1 DEMD0 DEMA1 DEMA0 DEMB1 DEMB0 DEMC1 DEMC0 Default 0 1 0 1 0 1 0 1 DEMA1-0: De-emphasis response control for DAC1 data on SDTI1 ( Table 7) Initial: “01”, OFF DEMB1-0: De-emphasis response control for DAC2 data on SDTI2 ( Table 7) Initial: “01”, OFF DEMC1-0: De-emphasis response control for DAC3 data on SDTI3 ( Table 7) Initial: “01”, OFF DEMD1-0: De-emphasis response control for DAC4 data on SDTI4 ( Table 7) Initial: “01”, OFF MS1277-E-02 2012/03 - 38 -
[AK4629] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H ATT speed & 0 PDDA4 ATS1 ATS0 PDDA3 PDDA2 PDDA1 RSTN Power Down Control Default 0 0 0 0 0 0 0 1 RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation ATS1-0: Digital attenuator transition time setting ( Table 13) Initial: “00”, mode 0 PDDA4-1: Power-down control (0: Power-up, 1: Power-down) PDDA1: Power down control of DAC1 PDDA2: Power down control of DAC2 PDDA3: Power down control of DAC3 PDDA4: Power down control of DAC4 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Zero detect 0 DZFM3 DZFM2 DZFM1 DZFM0 PWVRN PWADN PWDAN Default 0 0 1 1 1 1 1 1 PWDAN: Power-down control of DAC1-4 0 : P o w e r - d o w n 1: Normal operation PWADN: Power-down control of ADC 0 : P o w e r - d o w n 1: Normal operation PWVRN: Power-down control of reference voltage 0 : P o w e r - d o w n 1: Normal operation DZFM3-0: Zero detect mode select ( Table 11) Initial: “0111”, disable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Power Down Control 0 0 0 0 0 0 PDAD2 PDAD1 Default 0 0 0 0 0 0 0 0 PDAD2-1: Power-down control (0: Power-up, 1: Power-down) PDAD1: Power down control of ADC1 PDAD2: Power down control of ADC2 MS1277-E-02 2012/03 - 39 -
24 ROUT4
Figure 32. Ground Layout Note: VSS1 and VSS2 must be connected to the same analog ground plane.
- Grounding and Power Supply Decoupling
from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4629. @fs=48kHz .The ADC output data format is 2’s complement. The internal HPF removes the DC offset. around the sampling frequency of analog inputs.
I/F example when 3.3V and 5V power supply devices are used. Figure 35. Power Supply Connection Example
[AK4629] PACKAGE 1 12 48 13 7.0 9.0 7.0 9.0 0.22 ± 0.08 48pin LQFP(Unit: mm) 0.10 37 24 25 36 0.09 ∼ 0.20 1.40 ± 0.05 0.13 ± 0.13 1.70Max 0° ∼ 10° 0.10 0.30 ~ 0.75 0.5 S S M ■ Package & Lead frame material Package molding compound: Epoxy L e a d f r a m e m a t e r i a l : C u Lead frame surface treatment: Solder (Pb free) plate MS1277-E-02 2012/03 - 44 -
[AK4629] MARKING AK4629VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4629VQ 4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents 11/01/26 00 First Edition 11/08/29 01 Specification Change
7 ANALOG CHARACTERISTICS
ADC Analog Input Characteristics (Single-ended Inputs) S/(N+D), fs=48kHz: 92 → 96dB (typ) fs=96kHz: 86 → 92dB (typ) DR, fs=96kHz: 96 → 99dB (typ) fs=96kHz, A-weighted: 102 → 105dB (typ) S/N: fs=96kHz: 96 → 99dB (typ) fs=96kHz, A-wieghted: 102 → 105dB (typ) ADC Analog Input Characteristics (Differential Inputs) S/(N+D), fs=48kHz: 92 → 96dB (typ) fs=96kHz: 86 → 94dB (typ) DR, fs=96kHz: 97 → 100dB (typ) fs=96kHz, A-weighted: 103 → 106dB (typ) S/N: fs=96kHz: 97 → 100dB (typ) fs=96kHz, A-wieghted: 103 → 106dB (typ)
8 DAC Analog Output Characteristics
S/(N+D), fs=48kHz: 90 → 98dB (typ) fs=96kHz: 88 → 98dB (typ) fs=192kHz: 88 → 98dB (typ) MS1277-E-02 2012/03 - 45 -
[AK4629] MS1277-E-02 2012/03 - 46 - Date (Y/M/D) Revision Reason Page Contents 12/03/07 02 Error Correction 3 ■ Ordering Guide AK4629 → AK4629VQ
9 DC CHARACTERISTICS
High-level Output Voltage Condition: SDTO1-2, LRCK, BICK pins → SDTO1-2 pins Low-level Output Voltage Condition: SDTO1-2, LRCK, BICK, DZF1, DZF2 pins → SDTO1-2, DZF1, DZF2 pins IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.