AK4621 AKM | Alldatasheet
Document overview
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Technical content
[AK4621] MS1258-E-01 2011/01 - 1 - GENERAL DESCRIPTION The AK4621 is a high performance 24- bit CODEC that supports up to 192kHz recording and playback. The on-board analog-to-digital converter has a hi gh dynamic range due to AKM ’s Enhanced Dual-Bit architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4621 is ideal for Pro Audio sound cards, Digital Audio Workstations, DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.
FEATURES
□ 24-bit 2-channel ADC - Full Differential Inputs - Selectable Digital Filter 1. ADC Sharp Roll Off Filter (GD=39/fs) Passband: 0 ~ 21.8kHz (@fs=48kHz) Stopband Attenuation: 100dB 2. ADC Short Delay Sharp Roll Off Filter (GD=14/fs) Passband: 0 ~ 21.7kHz (@fs=48kHz) Stopband Attenuation: 80dB - S/(N+D): 102dB - S/N: 115dB - Digital High-pass Filter for Offset Cancellation - Overflow Flag - Audio Interface Format: MSB justified or I □ 24-bit 2-channel DAC - Selectable Digital Filter 1. DAC Sharp Roll Off Filter (GD=27/fs) Passband: 0 ~ 21.8kHz (@fs=48kHz) Stopband Attenuation: 70dB 2. DAC Slow Roll Off Filter (GD=27/fs) Passband: 0 ~ 8.9kHz (@fs=48kHz) Stopband Attenuation: 73dB 3. DAC Short Delay Sharp Roll Off Filter (GD=7/fs) Passband: 0 ~ 21.8kHz (@fs=48kHz) Stopband Attenuation: 70dB - Switched-cap Low Pass Filter - Differential Outputs - S/(N+D): 100dB - S/N: 115dB - De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling - Output Digital Attenuator: 0dB ~ – 72dB, Linear 256 + 16steps - Zero Detection Function - Audio Interface Format: MSB justified, LSB justified, I □ High Jitter Tolerance □ Sampling Rate: 32kHz ~ 216kHz □ μP Interface: 3-wire Serial Interface □ Master Clock: 128fs/192fs/256fs/384fs/512fs/768fs/1024fs 24-Bit 192kHz Stereo Audio CODEC AK4621
Figure 1. Block Diagram
[AK4621] MS1258-E-01 2011/01 - 3 - ■ Ordering Guide AK4621EF −10 ∼ +70°C 30pin VSOP (0.65mm pitch) AKD4621 Evaluation board for AK4621 ■ Pin Layout
1 VCOM
9 P/S
15 OVFR/DZFR 16 OVFL/DZFL
[AK4621] MS1258-E-01 2011/01 - 4 - ■ Compatibility with AK4620B 1. Function Function AK4620B AK4621 Max fs 216kHz ← ADC Inputs Single-ended Di fferential Differential Input analog PGA 0 ~ +18dB 0.5dB/step - - Input digital ATT Mute,-63.5dB ~ 0dB 0.5dB/step Mute,-63.5dB ~ 0dB 0.5dB/step - ADC S/(N+D) 90dB 100dB 102dB ADC DR, S/N 110dB 113dB 115dB ADC Digital Filter Type Sharp Roll-off Sharp Roll-off Short Delay Sharp Roll-off ADC Digital Filter SA 100dB 100dB 80dB ADC Digital Filter GD 43.2/fs 39/fs 14/fs DAC S/(N+D) 97dB (0dBFS) 100dB (-1dBFS) DAC DR, S/N 115dB ← DAC Digital Filter Type Sharp Roll-off Slow Roll-off Sharp Roll-off Slow Roll-off Short Delay Sharp Roll-off DAC Digital Filter SA 75dB 72dB 70dB 73dB 70dB DAC Digital Filter GD 28/fs 28/fs 27/fs 27/fs 7/fs Output digital Attenuator Mute, -48dB ~ 0dB Linear 256 steps Mute, -48dB ~ 0dB Linear 256 steps Mute, -72dB ~ 0dB Linear 16 + 256 steps DAC DSD mode X - DAC Zero-data detection X ← Parallel Mode X ← X: Available, -: Not Available 2. Register (difference from AK4620B) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control SLOW DZFB ZOE ZOS SDDA PWVR PWAD PWDA 01H Reset Control D/P DCKS DCKB SDAD AML AMR RSTAD RSTDA 02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 03H Deem and Volume C ontrol SMUTE HPRN HPLN ZCEI ZTM1 ZTM0 DEM1 DEM0 04H Reserved IATTL7 IATTL6 IATTL5 IATTL4 IATTL3 IATTL2 IATTL1 IATTL0 05H Reserved IATTR7 IATTR6 IATTR5 IATTR4 IATTR3 IATTR2 IATTR1 IATTR0 06H Lch DATT Control DATTL7 DA TTL6 DATTL5 DATTL4 DATTL3 DATTL2 DATTL1 DATTL0 07H Rch DATT Control DATTR7 DATTR6 DA TTR5 DATTR4 DATTR3 DATTR2 DATTR1 DATTR0 08H Lch Extension DATT Control 0 0 EXTE 0 EATTL3 EATTL2 EATTL1 EATTL0 09H Rch Extension DATT Control 0 0 0 0 EATTR3 EATTR2 EATTR1 EATTR0 These bits were added in the AK4621. These bits were deleted in the AK4621.
[AK4621] MS1258-E-01 2011/01 - 5 - PIN/FUNCTION No. Pin Name I/O Function
1 VCOM O Common Voltage Output Pin, (AVDD)/2
Bias voltage of ADC inputs and DAC outputs.
2 AINR+ I Rch Positive Input Pin
3 AINR- I Rch Negative Input Pin
4 AINL+ I Lch Positive Input Pin
5 AINL- I Lch Negative Input Pin
6 VREF I
Voltage Reference Input Pin, AVDD Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered AVDD.
7 VSS1 - Analog Ground Pin
8 AVDD - Analog Power Supply Pin, 4.75 ∼ 5.25V
9 P/S I
Parallel/Serial Mode Select Pin “L”: Serial Mode, “H”: Parallel Mode Do not change this pin during PDN pin = “H”.
10 MCLK I Master Clock Input Pin
11 LRCK I Input/Output Channel Clock Pin
12 BICK I Audio Serial Data Clock Pin
13 SDTO O Audio Serial Data Output Pin
14 SDTI I Audio Serial Data Input Pin
OVFR O Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode) 15 DZFR O Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode) OVFL O Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode) 16 DZFL O Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode) CDTI I Control Data Input Pin (in Serial Mode) 17 CKS0 I Master Clock Select Pin (in Parallel Mode) CCLK I Control Data Clock Pin (in Serial Mode) 18 CKS1 I Master Clock Select Pin (in Parallel Mode) CSN I Chip Select Pin in Serial Mode (in Serial Mode)
19 DIF I Digital Audio Interface Select Pin (in Parallel Mode)
“L”: 24bit MSB justified, “H”: I2S compatible
20 DFS0 I Double Speed Sampling Mode Pin
21 PDN I Power-Down Mode Pin
“L”: Power down reset and initialize the control register, “H”: Power up
22 DEM0 I De-emphasis Control Pin
23 SDFIL I
“L”: Short Delay Sharp Roll Off Filter (ADC), Short Delay Sharp Roll Off Filter (DAC) “H”: Sharp Roll Off Filter (ADC), Sharp Roll Off Filter (DAC) 24 TVDD - Digital I/O Power Supply Pin, DVDD ∼ 5.25V 25 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
26 VSS2 - Digital Ground Pin
27 AOUTL- O Lch Negative Analog Output Pin
28 AOUTL+ O Lch Positive Analog Output Pin
29 AOUTR- O Rch Negativ e Analog Output Pin
30 AOUTR+ O Rch Positive Analog Output Pin
Note 1. All digital input pins (P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL) must not be left floating.
[AK4621] MS1258-E-01 2011/01 - 6 - ■ Handling of Unused Pin The unused I/O pin must be processed appropriately as below. Classification Pin Name Setting AINL+, AINL- AINL+ pin is connected to AINL- pin. Analog Input AINR+, AINR- AINR+ pin is connected to AINR- pin. Analog Output AOUTL+, AOUTL-, AOUTR+, AOUT R- These pins must be open. Digital Output OVFL/DZFL, OVFR/DZFR These pins must be open. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 2, Note 3) Parameter Symbol min max Units Power Supplies: Analog Digital Digital I/O AVDD DVDD TVDD -0.3 -0.3 -0.3 6.0 6.0 6.0 V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 4) VINA -0.3 AVDD+0.3 V Digital Input Voltage (Note 5) VIND -0.3 TVDD+0.3 V Ambient Temperature (power applied) Ta -10 70 °C Storage Temperature Tstg -65 150 °C Note 2. All voltages with respect to ground. Note 3. VSS1 and VSS2 must be connected to the same analog ground plane. Note 4. AINL+, AINL-, AINR+ and AINR- pins Note 5. P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 2) Parameter Symbol min typ max Units Power Supplies Note 6) Analog Digital Digital I/O AVDD DVDD TVDD 4.75 3.0 DVDD 5.0 3.3 5.0 5.25 3.6 5.25 V V V Voltage Reference VREF 3.0 - AVDD V Note 2. All voltages with respect to ground. Note 6: The power up sequence among AVDD, DVDD and TVDD is not critical. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Note 7. Full scale (0dB) of the input voltage. Vin (typ) = ±2.82Vpp x VREF/5. Note 8. PSR is applied to AVDD, DVDD, TVDD with 1kHz, 50mVpp. VREF pin is held a constant voltage. Note 9. 100dB at 16bit data and 114dB at 20bit data. Figure 20. External LPF Circuit Example 2. Note 11. S/N does not depend on input bit length. Note 12. The voltage on VREF is held +5V externally. Note 13. Full scale voltage (0dB). Output voltage scales with the voltage of VREF. AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.
[AK4621] MS1258-E-01 2011/01 - 8 - Parameter min typ max Units Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD - 34 51 mA DVDD+TVDD (fs=48kHz) (fs=96kHz) (fs=192kHz) mA mA mA Power-down mode (PDN pin = “L”) (Note 15) AVDD DVDD+TVDD 100 100 μA μA Note 15. All digital input pins are held TVDD or VSS2.
[AK4621] MS1258-E-01 2011/01 - 9 - ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.005dB −0.02dB −0.06dB −6.0dB PB 22.0 22.3 24.0 21.8 kHz kHz kHz kHz Stopband (Note 16) SB 26.5 - - kHz Passband Ripple PR - - ±0.005 dB Stopband Attenuation SA 100 - - dB Group Delay (Note 17) GD - 39 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 1.0 6.5 Hz Hz ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=96kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.005dB −0.02dB −0.06dB −6.0dB PB 44.1 44.5 48.0 43.7 kHz kHz kHz kHz Stopband (Note 16) SB 53.0 - - kHz Passband Ripple PR - - ±0.005 dB Stopband Attenuation SA 100 - - dB Group Delay (Note 17) GD - 39 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 2.0 13.0 Hz Hz
[AK4621] MS1258-E-01 2011/01 - 10 - ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=192kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.005dB −0.02dB −0.06dB −6.0dB PB 88.2 89.0 96.0 87.0 kHz kHz kHz kHz Stopband (Note 16) SB 106.0 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 100 - - dB Group Delay (Note 17) GD - 36 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 4.0 26.0 Hz Hz Note 16: The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz Note 17: The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC. If the signal is outputted to the SDTO pin, group delay is increased 0.5/fs from the above value.
[AK4621] MS1258-E-01 2011/01 - 11 - ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.01dB −0.1dB −3.0dB −6.0dB PB 22.1 23.8 24.4 21.7 kHz kHz kHz kHz Stopband (Note 16) SB 28.2 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 80 - - dB Group Delay (Note 17) GD - 14 - 1/fs Group Delay Distortion ΔGD - ±0.01 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 1.0 6.5 Hz Hz ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=96kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.01dB −0.1dB −3.0dB −6.0dB PB 44.2 47.6 48.9 43.3 kHz kHz kHz kHz Stopband (Note 16) SB 55.9 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 80 - - dB Group Delay (Note 17) GD - 14 - 1/fs Group Delay Distortion ΔGD - ±0.013 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 2.0 13.0 Hz Hz ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=192kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 16) −0.01dB −0.1dB −3.0dB −6.0dB PB 81.1 99.9 106.7 76.1 kHz kHz kHz kHz Stopband (Note 16) SB 141.1 - - kHz Passband Ripple PR - - ±0.01 dB Stopband Attenuation SA 79 - - dB Group Delay (Note 17) GD - 11 - 1/fs Group Delay Distortion ΔGD - 0 - μs ADC Digital Filter (HPF): Frequency Response (Note 16) −3dB −0.1dB FR 4.0 26.0 Hz Hz
[AK4621] MS1258-E-01 2011/01 - 12 - DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz) SLOW bit = “0”, SDDA bit = “0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.04dB -6.0dB PB 24.0 21.8 kHz kHz Stopband (Note 18) SB 26.2 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz - ± 0.2 - dB DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz) SLOW bit = “0”, SDDA bit = “0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.04dB -6.0dB PB 48.0 43.5 kHz kHz Stopband (Note 18) SB 52.4 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz - ± 0.3 - dB DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz) SLOW bit = “0”, SDDA bit = “0”) Parameter symbol min typ max Units Digital Filter Passband (Note 18) -0.02B -6.0dB PB 95.9 87.0 kHz kHz Stopband (Note 18) SB 105 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz - +0/-1 - dB Note 18. The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz. Note 19. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.
[AK4621] MS1258-E-01 2011/01 - 13 - DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz) SLOW bit = “1”, SDDA bit = “0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.07dB -3.0dB PB 19.8 8.9 kHz kHz Stopband (Note 18) SB 42.6 - - kHz Passband Ripple PR - - ±0.07 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz - +0/-5 - dB DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz) SLOW bit = “1”, SDDA bit = “0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.07dB -3.0dB PB 39.5 17.7 kHz kHz Stopband (Note 18) SB 85.1 - - kHz Passband Ripple PR - - ±0.07 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz - +0/-4 - dB DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz) SLOW bit = “1”, SDDA bit = “0”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.07dB -3.0dB PB 79.0 35.5 kHz kHz Stopband (Note 18) SB 170.7 - - kHz Passband Ripple PR - - ±0.07 dB Stopband Attenuation SA 73 - - dB Group Delay (Note 19) GD - 27 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz - +0/-5 - dB
[AK4621] MS1258-E-01 2011/01 - 14 - DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz) SLOW bit = “0”, SDDA bit = “1”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.04dB -6.0dB PB 24.0 21.8 kHz kHz Stopband (Note 18) SB 26.2 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 7 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz - ± 0.2 - dB DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz) SLOW bit = “0”, SDDA bit = “1”) Parameter Symbol min typ max Units Digital Filter Passband (Note 18) -0.03dB -6.0dB PB 48.0 43.5 kHz kHz Stopband (Note 18) SB 52.4 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 7 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz - ± 0.3 - dB DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz) SLOW bit = “0”, SDDA bit = “1”) Parameter symbol min typ max Units Digital Filter Passband (Note 18) -0.02dB -6.0dB PB 96.2 87.0 kHz kHz Stopband (Note 18) SB 104.9 - - kHz Passband Ripple PR - - ±0.06 dB Stopband Attenuation SA 70 - - dB Group Delay (Note 19) GD - 7 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz - +0/-1 - dB
[AK4621] MS1258-E-01 2011/01 - 15 - DC CHARACTERISTICS Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD TVDD 30%DVDD V V High-Level Output Voltage (Iout=-100μA) Low-Level Output Voltage (Iout=100μA) VOH VOL DVDD-0.5 0.5 V V Input Leakage Current Iin - - ±10 μA SWITCHING CHARACTERISTICS Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 55.296 MHz ns ns LRCK Frequency (Note 20) Normal Speed Mode (DFS0=“0”, DFS1=“0”) Double Speed Mode (DFS0=“1”, DFS1=“0”) Quad Speed Mode (DFS0=“0”, DFS1=“1”) Duty Cycle fsn fsd fsq 108 108 216 kHz kHz kHz PCM Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” ( Note 21) BICK “↑” to LRCK Edge (Note 21) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 1/128fsn 1/64fsd 1/64fsq ns ns ns ns ns ns ns ns ns ns ns Note 20. When the normal/double/quad speed modes are switched, the AK4621 must be reset by the PDN pin or RSTN bit. Note 21. BICK rising edge must not occur at the same time as LRCK edge.
[AK4621] MS1258-E-01 2011/01 - 16 - Parameter Symbol min typ max Units Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 22) RSTAD “↑” to SDTO Valid (Note 23) tPD tPDV 150 516 ns 1/fs Note 22. The AK4621 can be reset by bringing the PDN pin “L”. Note 23. These cycles are the number of LRCK rising from RSTAD bit.
(PDN pin =“L”→“H”) at power-up and other situations, the AK4621 is in power-down mode until MCLK is supplied. is out of phase by changing the clock frequencies.
- Serial mode (P/S pin= “L”)
Table 1, Table 2 and Table 3, select the MCLK frequency by setting CMODE, CKS1-0 and DFS1-0 bits. These registers are changed when RSTAD bit = RSTDA bit = “0”. Table 1. Sampling Speed in Serial Mode (N/A: Not Available) **Table 2. Master Clock frequency in Serial Mode (“*”; refer to Table 3.) (N/A: Not Available)** Table 3. Auto Setting Mode in Serial Mode (DFS1-0 bits = “01”, CMODE bit = “0”, CKS1-0 bits = “11”)
- Parallel mode (P/S pin= “H”)
be changed when the PDN pin = “L”. Table 4. Sampling Speed in Parallel Mode **Table 5. Master Clock Frequency in Parallel Mode (“*”; refer to Table 6.) (N/A: Not Available)** The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically. Table 6. Auto Setting Mode in Parallel Mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”) Table 7. Master Clock Frequency Example (N/A: Not Available)
justified formats by zeroing the unused LSBs. Table 8. Audio Data Format (Serial Mode)
2 L 24bit, MSB justified 24bit, MSB justified H/L ≥ 48fs
3 H 24bit, I 2S 24bit, I 2S L/H ≥ 48fs
Table 9. Audio Data Format (Parallel Mode) Figure 7. Mode 0 Timing Figure 8. Mode 1 Timing
Table 10. Volume calculating formula is shown in Table 13. Table 10. Output Digital Volume Transition Time Table 11. Output Digital Volume Setting (EXTE bit = “0”) within 4LRCK cycles, the volume transition may stop. Table 12. Output Digital Volume Setting (EXTE bit = “1”)
Table 13. Output Digital Volume Formula “L” for 516/fs (=10.8ms @fs=48kHz) after the PDN pin = “↑”, and then overflow detection is enabled. The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz. enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits.
DAC can be controlled by using the SDFIL pin or SDAD/SDDA/SLOW bits. Table 14. Digital Filter Selection in Parallel Mode
0 Sharp Roll Off Filter (default)
1 Short Delay Sharp Roll Off Filter
Table 15. ADC Digital Filter Selection in Serial Mode Table 16. DAC Digital Filter Selection in Serial Mode (N/A: Not Available) “0” and only the DEM0 pin can be controlled (44.1kHz or OFF). Table 17. De-emphasis control (Normal Speed Mode)
source without stopping the signal transmission. time is 1020LRCK cycles (1020/fs). If the EATT is enabled, this time is 1080LRCK cycles (1080/fs). (2) Analog output corresponding to digital input has group delay (GD). to “H”. The DZF pin immediately returns to “L” if input data are not zero after going to “H”. Figure 12. Soft Mute and Zero Detection
(1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs). (3) ADC output is “0” data in power-down state. (4) After exiting power down and reset state, ATT value fades in/out. according to fade operation. according to fade operation. value changes from YYH to ZZH according to fade operation. (5) In the power-down mode, the DAC output is VCOM level. In the reset state, the DAC output is floating (Hi-z). (6) Click noise occurs after RSTDA bit or PWDA bit is changed. (7) Mute the analog output externally if the click noise (6) influences system application. and DAC output is floating (Hi-Z). Figure 13. Reset & Power down sequence in serial mode
initialization cycle and the operation of fade-in. (1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs). (3) ADC output is “0” data in power-down state. (4) DAC output is floating (Hi-z) in power-down state. (5) Click noise occurs at the rising/falling edge of PDN. (6) Mute the analog output externally if the click noise (5) influences system application. and DAC output is floating (Hi-Z). Figure 14. Reset & Power Down Sequence in parallel mode
access to the chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values. Table 18. Function List (X: available, -: not available) Figure 15. Control I/F Timing
- READ command is not supported.
- The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
[AK4621] MS1258-E-01 2011/01 - 30 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control SLOW DZ FB ZOE ZOS SDDA PWVR PWAD PWDA 01H Reset Control 0 0 0 SDAD 0 0 RSTAD RSTDA 02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 03H Deem and Volume Control SMU TE HPRN HPLN 0 0 0 DEM1 DEM0 04H Reserved 0 0 0 0 0 0 0 0 05H Reserved 0 0 0 0 0 0 0 0 06H Lch DATT Control DATTL7 DA TTL6 DATTL5 DATTL4 DATTL3 DATTL2 DATTL1 DATTL0 07H Rch DATT Control DATTR7 DATTR6 DA TTR5 DATTR4 DATTR3 DATTR2 DATTR1 DATTR0 08H Lch Extension DATT Control 0 0 EXTE 0 EATTL3 EATTL2 EATTL1 EATTL0 09H Rch Extension DATT Control 0 0 0 0 EATTR3 EATTR2 EATTR1 EATTR0 Note 25: Data must not be written to addresses 0AH through 1FH. PDN pin = “L” resets the registers to their default values. ■ Control Register Setup Sequence When the PDN pin goes “L” to “H” upon power-up etc., the AK4621 will be ready for normal operation by the sequence below. In this case, all control registers are set to default values and the AK4621 is in the reset state. (1) Set the clock mode and the audio data interface mode. (2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H). (3) ADC output and DAC output must be muted externally until canceling each reset state. The clock mode must be changed after setting RSTAD bit a nd RSTDA bit to “0”. At that time, ADC outputs and DAC outputs must be muted externally.
[AK4621] MS1258-E-01 2011/01 - 31 - ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control SLOW DZFB ZOE ZOS SDDA PWVR PWAD PWDA Default 0 0 0 0 0 1 1 1 PWDA: DAC power down 0: Power down 1: Power up (default) When PWDA bit = “0”, only the DAC block is powered down and the AOUT becomes Hi-z immediately. In this time, all registers are not initialized, and register writings are valid. After exiting power down mode, the OATT fades in/out the setting value of the control register (06H, 07H, 08H, 09H). The analog output must be muted externally as a pop noise may occur when entering and exiting this mode. PWAD: ADC power down 0: Power down 1: Power up (default) When PWAD bit = “0”, only the ADC block is powered-down and the SDTO pin becomes “L” immediately. After exiting power down mode, the ADC outputs “0” during first 516 LRCK cycles. PWVR: Vref power down 0: Power down 1: Power up (default) When PWVR bit = “0”, all blocks are powered down. Both ADC and DAC cannot operate. In this time, all registers are not initialized, and register writings are valid. Only the VRFE block can be powered up by setting PWAD = PWDA bit = “0” and PWVR bit = “1”. SDDA: DAC Short Delay Sharp Roll Off Filter Enable ( Table 16) Default: Disable ZOS: Zero-detection/ Ove rflow-detection control for OVFL/DZFL and OVFR/DZFR pins. 0: Overflow detection for ADC input (default) 1: Zero detection for DAC input. ZOE: Zero-detection / Overflow-detection Disable 0: Enable (default) 1: Disable. Outputs “L”. DZFB: Inverting Enable of DZF 0: DZF goes “H” at Zero Detection (default) 1: DZF goes “L” at Zero Detection SLOW: DAC Slow Roll Off Filter Enable ( Table 16) Default: Disable
[AK4621] MS1258-E-01 2011/01 - 32 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Reset Control 0 0 0 SDAD 0 0 RSTAD RSTDA Default 0 0 0 0 0 0 0 0 RSTDA: DAC reset 0: Reset (default) 1: Normal Operation When RSTDA bit =“0”, the internal timing of DAC is reset and the AOUT becomes VCOM voltage immediately. In this time, all registers are not initia lized, and register writings are valid. After exiting the power down mode, the OATT fades in the setting values of the control register (06H, 07H, 08H, 09H). The analog outputs must be muted extern ally since a pop noise may occur when entering to and exiting from this mode. RSTAD: ADC reset 0: Reset (default) 1: Normal Operation When RSTAD bit =“0”, the internal timing of ADC is reset and the SDTO pin becomes “L” immediately. In this time, all registers are not initialized, and re gister writings are valid. After exiting the power down mode, the ADCs output “0” during first 516 LRCK cycles. SDAD: ADC Short Delay Sharp Roll Off Filter Enable ( Table 15) Default: Disable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 Default 0 1 0 0 0 0 0 0 DFS1-0: Sampling Speed Control ( Table 1) Default: Normal speed CMODE, CKS1-0: Master Clock Frequency Select ( Table 2) Default: 256fs DIF2-0: Audio data interface modes ( Table 8) 000: Mode 0 001: Mode 1 010: Mode 2 (default) 011: Mode 3 100: Mode 4 Default: 24bit MSB justified for both ADC and DAC
[AK4621] MS1258-E-01 2011/01 - 33 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Deem and Volume Control SMUTE HPRN HPLN 0 0 0 DEM1 DEM0 Default 0 0 0 0 0 0 0 1 DEM1-0: De-emphasis response ( Table 17) 00: 44.1kHz 01: OFF (default) 10: 48kHz 11: 32kHz HPLN/RN: Left/Right channel Digital High Pass Filter Disable 0: Enable (default) 1: Disable SMUTE: DAC Input Soft Mute control 0: Normal operation (default) 1: DAC outputs soft-muted The soft mute is independent of the output ATT and performed digitally. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Lch DATT Control DATTL7 DATTL6 DATTL5 DATTL4 DA TTL3 DATTL2 DATTL1 DATTL0 07H Rch DATT Control DATTR7 DATTR6 DATTR5 DATTR4 DATTR3 DATTR2 DATTR1 DATTR0 Default 1 1 1 1 1 1 1 1 DATT7-0: DAC Output Attenuation Level, Linear step. ( Table 12, Table 13) Default: 00H (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Lch Extension DATT Control 0 0 EXTE 0 EATTL3 EA TTL2 EATTL1 EATTL0 09H Rch Extension DATT Control 0 0 0 0 EATTR3 EATTR2 EATTR1 EATTR0 Default 0 0 0 0 1 1 1 1 EATT3-0: DAC Output Extension Attenuation Level; Linear step. ( Table 12, Table 13) Default: FH EXTE: Extension DATT Enable 0: Disable (default) 1 : E n a b l e
Figure 17. Ground Layout
- Ground and Power Supply Decoupling
order to avoid unwanted coupling into the AK4621. multiples of 128fs (@Normal Speed Mode), 64fs (@Double Speed Mode) or 32fs (@Quad Speed Mode).
composed of op-amp. Refer to an evaluation board for details. Figure 18. Input Buffer Example
Figure 20. External LPF Circuit Example 2 Table 20. Frequency Response of External LPF Circuit Example 2
[AK4621] MS1258-E-01 2011/01 - 39 - PACKAGE D et ail A N OTE: Dimension "*" does not include mold flash. 0.24± 0.0 6 0.65 *9.7±0.1 1. 5MAX A 1 15 1630 30pin VSOP (Unit: mm) 5. 6±0. 1 7.6± 0.2 0.45± 0.2 -0.05 +0.06 0. 3 0. 170.12 M 0.08 1.2± 0. 10 0.10 +0.1 0 -0 .05 0° ~ 8 ° S ■ Package & Lead frame material Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free Lead frame material: Cu Alloy Lead frame surface treatment: Solder (Pb free) plate
[AK4621] MS1258-E-01 2011/01 - 40 - MARKING AKM AK4621EF XXXXYYYYZ YYYY: Date code XXXX, Z: Internal control code
[AK4621] MS1258-E-01 2011/01 - 41 -
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page/Line Contents 10/12/07 00 First Edition 11/01/26 01 Description Change Digital filter names were changed. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor aut horized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.