AK4620A AKM | Alldatasheet

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Technical content

[AK4620A] MS0368-E-00 - 1 - GENERAL DESCRIPTION The AK4620A is a high performance 24-bit CODEC that supports up to 192kHz record and playback. The on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4620A has an input Programmable Gain Amplifier and is ideal for Pro Audio sound cards, Digital Audio Workstations, DVD-R, hard disk, CD-R recording/playback systems, and musical instrument recording.

FEATURES

  • 24-bit 2-channel ADC - Selectable Single-ended or Differential Input - High Performance Linear Phase Digital Anti-Alias Filter Passband: 0 ~ 20.25kHz (@fs=44.1kHz) Ripple: ± 0.005dB Stopband Attenuation: 100dB - S/(N+D): 92dB (single-ended) 100dB (differential) - S/N: 110dB (single-ended) 113dB (differential) - Digital High-pass Filter for Offset Cancellation - Input PGA: 0dB to +18dB, 0.5dB/step (for single-ended input) - Input Digital Attenuator: 0dB to – 63dB, 0.5dB/step - Overflow Flag - Audio Interface Format: MSB justified or I2S
  • 24-bit 2-channel DAC - 24-bit 8 times Oversampling Linear Phase Digital Filter Ripple: ±0.005dB Stopband Attenuation: 75dB - Switched-cap Low Pass Filter - Differential Outputs - S/(N+D): 100dB - S/N: 115dB - De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling - Output Digital Attenuator: Linear 255 steps - Soft Mute - Zero Detection Function - Audio interface format: MSB justified, LSB justified, I2S, or DSD
  • High Jitter Tolerance
  • Sampling Rate: Up to 216kHz
  • µP Interface: 3-wire Serial Interface
  • Master Clock - 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
  • Power Supply: 5V ± 5%(Analog), 3V~3.6V with 5V tolerant I/O(Digital)
  • Small 30-pin VSOP package
  • Ta: -10 to 70 °C 24-Bit 192kHz Audio CODEC with IPGA AK4620A

Figure 1. Block Diagram

  • Compatibility with AK4528 / AK4524 Function AK4524 AK4528 AK4620A Max fs 96kHz 108kHz 216kHz ADC Inputs Single-ended Differential Single-ended Differential Input analog PGA 0dB ~ +18dB 0.5dB/step 0 ~ +18dB 0.5dB/step Input digital ATT Mute, -72dB ~ 0dB Pseudo-log step Mute, -72dB ~ 0dB Pseudo-log step Mute,-63.5dB ~ 0dB 0.5dB/step Mute,-63.5dB ~ 0dB 0.5dB/step ADC S/(N+D) 90dB 94dB 92dB 100dB ADC DR, S/N 100dB 108dB 110dB 113dB ADC Digital Filter SA 75dB 75dB 100dB ADC Overflow detection X DAC S/(N+D) 94dB 94dB 100dB DAC DR, S/N 110dB 110dB 115dB Output digital Attenuator Mute, -72dB ~ 0dB Pseudo-log step Mute, -72dB ~ 0dB Pseudo-log step Mute, -48dB ~ 0dB Linear 256 steps Mute, -48dB ~ 0dB Linear 256 steps DAC DSD mode X DAC Zero-data detection X X’tal Oscillating Circuit X Master Mode X Parallel Mode X X X: Available, -: NOT available

[AK4620A] MS0368-E-00 - 3 - „ Ordering Guide AK4620AVF -10∼+70°C 30pin VSOP (0.65mm pitch) AKD4620A Evaluation Board „ Pin Layout VCOM AINR+ AINL+ AINR-/NC AINL-/NC VREF AGND VA Top View P/S MCLK LRCK/DSDR BICK/DCLK SDTO SDTI/DSDL AOUTR+ AOUTR- AOUTL+ AOUTL- DGND VD VT ADMODE DEM0 PDN DFS0 CSN/DIF CCLK/CKS1 CDTI/CKS0 OVFR/DZFR OVFL/DZFL

[AK4620A] MS0368-E-00 - 4 - PIN/FUNCTION No. Pin Name I/O Function VCOM O Common Voltage Output Pin, VA/2 Bias voltage of ADC inputs and DAC outputs. AINR+ I Rch Positive Input Pin I Rch Negative Input Pin (when ADMODE pin=“H”) AINR- I No Connect pin (when ADMODE pin=“L”) No internal bonding. This pin should be open. AINL+ I Lch Positive Input Pin I Lch Negative Input Pin (when ADMODE pin=“H”) AINL- I No Connect pin (when ADMODE pin=“L”) No internal bonding. This pin should be open. VREF I Voltage Reference Input Pin, VA Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered VA. AGND Analog Ground Pin VA Analog Power Supply Pin, 4.75 ∼ 5.25V P/S I Parallel/Serial Mode Select Pin “L”: Serial Mode, “H”: Parallel Mode Do not change this pin during PDN pin = “H”. MCLK I Master Clock Input Pin LRCK I Input/Output Channel Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode) DSDR I DSD Rch Data Input Pin (when D/P bit=“1” in Serial Mode) BICK I Audio Serial Data Clock Pin (in Parallel mode or when D/P bit=“0” in Serial Mode) DCLK I DSD Clock Pin (when D/P bit=“1” in Serial Mode) SDTO O Audio Serial Data Output Pin SDTI I Audio Serial Data Input Pin (in Parallel mode or when D/P bit=“0” in Serial Mode) DSDL I DSD Lch Data Input Pin (when D/P bit=“1” in Serial Mode) OVFR O Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode) DZFR O Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode) OVFL O Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode) DZFL O Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode) CDTI I Control Data Input Pin (in Serial Mode) CKS0 I Master Clock Select Pin (in Parallel Mode) CCLK I Control Data Clock Pin (in Serial Mode) CKS1 I Master Clock Select Pin (in Parallel Mode) CSN I Chip Select Pin in Serial Mode (in Serial Mode) DIF I Digital Audio Interface Select Pin (in Parallel Mode) “L”: 24bit MSB justified, “H”: I2S compatible DFS0 I Double Speed Sampling Mode Pin PDN I Power-Down Mode Pin “L”: Power down reset and initialize the control register, “H”: Power up DEM0 I De-emphasis Control Pin ADMODE I Analog Input Mode Select Pin “L”: Single-ended Input & IPGA Enable “H”: Differential Input & IPGA Bypass

[AK4620A] MS0368-E-00 - 5 - PIN/FUNCTION (Continued) VT Input Buffer Tolerant Pin, 3.0 ∼ 5.25V VD Digital Power Supply Pin, 3.0 ∼ 3.6V DGND Digital Ground Pin AOUTL- O Lch Negative Analog Output Pin AOUTL+ O Lch Positive Analog Output Pin AOUTR- O Rch Negative Analog Output Pin AOUTR+ O Rch Positive Analog Output Pin Note. Do not allow digital input pins (P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins) to float. „ Handling of Unused Pin The unused I/O pin should be processed appropriately as below. Classification Pin Name Setting AINL+, AINL-/NC, AINR+, AINR+NC These pins should be open when ADMODE pin = “L”. AINL+, AINL-/NC AINL+ pin is connected to AINL-/NC pin when ADMODE pin = “H”. Analog Input AINR+, AINR-/NC AINR+ pin is connected to AINR-/NC pin when ADMODE pin = “H”. Analog Output AOUTL+, AOUTL-, AOUTR+, AOUTR- These pins should be open. Digital Input DEM0 This pin should be connected to DVSS. Digital Output OVFL/DZFL, OVFR/DZFR These pins should be open.

[AK4620A] MS0368-E-00 - 6 - ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V;Note 1) Parameter Symbol min max Units Power Supplies: Analog Digital Input Tolerant |AGND – DGND| (Note 2) VA VD VT ∆GND -0.3 -0.3 -0.3 6.0 6.0 6.0 0.3 V V V V Input Current, Any Pin Except Supplies IIN ±10 mA Analog Input Voltage (Note 3) VINA -0.3 VA+0.3 V Digital Input Voltage (Note 4) VIND -0.3 VT+0.3 V Ambient Temperature (powered applied) Ta -10 Storage Temperature Tstg -65 150 Note 1. All voltages with respect to ground. Note 2. AGND and DGND must be connected to the same analog ground plane. Note 3. AINL+, AINL-/NC, AINR+ and AINR-/NC pins Note 4. P/S, MCLK, LRCK/DSDR, BICK/DCLK, SDTI/DSDL, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and ADMODE pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND=0V;Note 1) Parameter Symbol min typ max Units Power Supplies (Note 5) Analog Digital Input Tolerant VA VD VT 4.75 3.0 VD 5.0 3.3 5.0 5.25 3.6 5.25 V V V Voltage Reference VREF 3.0 VA V Note 5. The power up sequence among VA, VD and VT is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

[AK4620A] MS0368-E-00 - 7 - ANALOG CHARACTERISTICS (ADC: Single-ended Input) (Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units Input PGA Characteristics: Input Voltage (Note 6) 2.77 3.07 3.37 Vpp Input Resistance (Note 7) 0.7 5.1 kΩ Step Size 0.2 0.5 0.8 dB Gain Control Range dB ADC Analog Input Characteristics: IPGA=0dB Resolution Bits fs=44.1kHz BW=20kHz -1dBFS -60dBFS dB dB fs=96kHz BW=40kHz -1dBFS -60dBFS dB dB S/(N+D) fs=192kHz BW=40kHz -1dBFS -60dBFS dB dB Dynamic Range (-60dBFS with A-weighted) 110 dB S/N (A-weighted) 101 110 dB Interchannel Isolation 105 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 150 ppm/°C Power Supply Rejection (Note 8) dB ANALOG CHARACTERISTICS (ADC: Differential Input) (Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics: Resolution Bits Input Voltage (Note 9) ±2.62 ±2.82 ±3.02 Vpp Input Resistance fs=44.1kHz kΩ fs=48kHz kΩ fs=96kHz kΩ fs=192kHz kΩ fs=44.1kHz BW=20kHz -1dBFS -60dBFS 100 dB dB fs=96kHz BW=40kHz -1dBFS -60dBFS 100 dB dB S/(N+D) fs=192kHz BW=40kHz -1dBFS -60dBFS 100 dB dB Dynamic Range (-60dBFS with A-weighted) 113 dB S/N (A-weighted) 103 113 dB Interchannel Isolation 120 dB Interchannel Gain Mismatch 0.1 0.5 dB Gain Drift ppm/°C Power Supply Rejection (Note 8) dB

[AK4620A] MS0368-E-00 - 8 - Note 6. Full scale (0dB) of the input voltage at PGA=0dB. This voltage is proportional to VREF. Vin(typ) = 3.07Vpp x VREF/5. Note 7. These values become smaller when a gain of IPGA is large. IPGA=0dB; typ. 5.1kΩ, IPGA=+18dB; typ. 1.18kΩ Note 8. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage. Note 9. Full scale (0dB) of the input voltage at 0dB. This voltage is proportional to VREF. Vin (typ) = ±2.82Vpp x VREF/5. ANALOG CHARACTERISTICS (DAC) (Ta=25°C; VA=5V, VD=3.3V, VT=5V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency =1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz at fs=44.1kHz, 40Hz ∼ 40kHz at fs=96kHz, 40Hz ∼ 40kHz at fs=192kHz; unless otherwise specified) DAC Analog Output Characteristics: Parameter min typ max Units Resolution Bits Dynamic Characteristics fs=44.1kHz BW=20kHz 0dBFS −60dBFS 100 dB dB fs=96kHz BW=40kHz 0dBFS −60dBFS dB dB S/(N+D) fs=192kHz BW=40kHz 0dBFS −60dBFS dB dB Dynamic Range (−60dBFS with A-weighted) (Note 10, Note 11) 115 dB S/N (A-weighted) (Note 11, Note 12) 107 115 dB Interchannel Isolation (1kHz) 110 dB DC Accuracy Interchannel Gain Mismatch 0.15 0.3 dB Gain Drift (Note 13) ppm/°C Output Voltage (Note 14) ±2.6 ±2.8 ±3.0 Vpp Load Capacitance pF Load Resistance (Note 15) kΩ Note 10. 100dB at 16bit data and 114dB at 20bit data. Note 11. By Figure 19. External LPF Circuit Example 2 for PCM. Note 12. S/N does not depend on input bit length. Note 13. The voltage on VREF is held +5V externally. Note 14. Full-scale voltage(0dB). Output voltage scales with the voltage of VREF. AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5. Note 15. For AC-load. Parameter min typ max Units Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) VA: ADC Single-ended Mode ADC Differential Mode mA mA VD+VT (fs=44.1kHz) (fs=96kHz) (fs=192kHz) mA mA mA Power-down mode (PDN pin = “L”) (Note 16) VA VD+VT 100 100 µA µA Note 16. All digital input pins are held VT or DGND.

[AK4620A] MS0368-E-00 - 9 - ADC FILTER CHARACTERISTICS (fs=44.1kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 17) −0.005dB −0.02dB −0.06dB −6.0dB PB 20.25 20.4 22.05 19.8 kHz kHz kHz kHz Stopband (Note 17) SB 24.3 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 18) GD 43.2 1/fs Group Delay Distortion ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 17) −3dB −0.1dB FR 0.9 6.0 Hz Hz ADC FILTER CHARACTERISTICS (fs=96kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 17) −0.005dB −0.02dB −0.06dB −6.0dB PB 44.08 44.5 48.0 43.0 kHz kHz kHz kHz Stopband (Note 17) SB 53.0 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 18) GD 43.1 1/fs Group Delay Distortion ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 17) −3dB −0.1dB FR 2.0 13.0 Hz Hz FILTER CHARACTERISTICS (fs=192kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 17) −0.005dB −0.02dB −0.06dB −6.0dB PB 88.18 89.0 96.0 86.0 kHz kHz kHz kHz Stopband (Note 17) SB 106.0 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 100 dB Group Delay (Note 18) GD 38.2 1/fs Group Delay Distortion ∆GD µs ADC Digital Filter (HPF): Frequency Response (Note 17) −3dB −0.1dB FR 4.0 26.0 Hz Hz Note 17. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz. Note 18. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC.

[AK4620A] MS0368-E-00 - 10 - DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) SLOW = “0”) Parameter Symbol min typ max Units Digital Filter Passband ±0.01dB (Note 19) -6.0dB PB 22.05 20.0 kHz kHz Stopband (Note 19) SB 24.1 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz ± 0.2 dB DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) = “0”) Parameter Symbol min typ max Units Digital Filter Passband ±0.01dB (Note 19) -6.0dB PB 48.0 43.5 kHz kHz Stopband (Note 19) SB 52.5 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz ± 0.3 dB DAC SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) = “0”) Parameter symbol min typ max Units Digital Filter Passband ±0.01dB (Note 19) -6.0dB PB 96.0 87.0 kHz kHz Stopband (Note 19) SB 105 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz +0/-1 dB Note 19. The passband and stopband frequencies scale with fs. For example, PB = 0.4535×fs (@±0.01dB), SB = 0.546×fs. Note 20. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input register to the output of analog signal.

[AK4620A] MS0368-E-00 - 11 - DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) SLOW = “1”) Parameter Symbol min typ max Units Digital Filter Passband ±0.04dB (Note 21) -3.0dB PB 18.2 8.1 kHz kHz Stopband (Note 21) SB 39.2 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz +0/-5 dB DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) = “1”) Parameter Symbol min typ max Units Digital Filter Passband ±0.04dB (Note 21) -3.0dB PB 39.6 17.7 kHz kHz Stopband (Note 21) SB 85.3 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz +0/-4 dB DAC SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) = “1”) Parameter Symbol min typ max Units Digital Filter Passband ±0.04dB (Note 21) -3.0dB PB 79.1 35.5 kHz kHz Stopband (Note 21) SB 171 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA dB Group Delay (Note 20) GD 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz +0/-5 dB Note 21. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.

[AK4620A] MS0368-E-00 - 12 - DIGITAL CHARACTERISTICS Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%VD VT 30%VD V V High-Level Output Voltage (Iout=-100µA) Low-Level Output Voltage (Iout=100µA) VOH VOL VD-0.5 0.5 V V Input Leakage Current Iin ±10 µA SWITCHING CHARACTERISTICS Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 55.296 MHz ns ns LRCK Frequency (Note 22) Normal Speed Mode (DFS0=“0”, DFS1=”0”) Double Speed Mode (DFS0=“1”, DFS1=”0”) Quad Speed Mode (DFS0=“0”, DFS1=”1”) Duty Cycle fsn fsd fsq 108 108 216 kHz kHz kHz PCM Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 23) BICK “↑” to LRCK Edge (Note 23) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 1/128fsn 1/64fsd 1/64fsq ns ns ns ns ns ns ns ns ns ns ns DSD Audio Interface Timing DCLK Period DCLK Pulse Width Low Pulse Width High DCLK Edge to DSDL/R (Note 24) tDCK tDCKL tDCKH tDDD 1/64fs 160 160 -20 ns ns ns ns Note 22. When the normal/double/quad speed modes are switched, the AK4620A should be reset by PDN pin or RSTN bit. Note 23. BICK rising edge must not occur at the same time as LRCK edge. Note 24. DSD data transmitting device must meet this time.

[AK4620A] MS0368-E-00 - 13 - Parameter Symbol min typ max Units Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 25) RSTAD “↑” to SDTO valid (Note 26) tPD tPDV 150 516 ns 1/fs Note 25. The AK4620A can be reset by bringing PDN pin “L”. Note 26. These cycles are the number of LRCK rising from RSTAD bit.

[AK4620A] MS0368-E-00 - 14 - „ Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fs LRCK VIH VIL tBCK tBCKL VIH tBCKH BICK VIL Clock Timing LRCK BICK SDTO SDTI tBLR tLRB tLRS tBSD tSDS tSDH VIH VIL VIH VIL 50%VD VIH VIL Audio Interface Timing (PCM mode)

[AK4620A] MS0368-E-00 - 15 - VIH DCLK VIL tDDD VIH DSDL DSDR VIL tDCKH tDCKL tDCK Audio Serial Interface Timing (DSD Normal Mode, DCKB bit = “0”) VIH DCLK VIL tDDD VIH DSDL DSDR VIL tDCKH tDCKL tDCK tDDD Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB bit = “0”)

[AK4620A] MS0368-E-00 - 16 - tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL R/W tCCKL tCCKH tCDS tCDH WRITE Command Input Timing CSN VIH CCLK VIL VIH CDTI VIL VIH VIL tCSW tCSH WRITE Data Input Timing tPD PDN VIL Power Down & Reset Timing

3/fs to change the mode. In parallel mode, AK4620A can only process PCM data. Table 1. DSD/PCM Mode Control synchronization is out of phase by changing the clock frequencies. (DFS0 bit and DFS0 pin are internally ORd). These registers are changed when RSTAD bit = RSTDA bit = “0”. Table 2. Sampling speed in serial mode

**Table 3. Master clock frequency in serial mode (“*”: refer to Table 4)** The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically. Table 4. Auto Setting Mode in serial mode (DFS1-0 = “01”, CMODE bit = “1”, CKS1-0 bit = “11”) pins should be changed when the PDN pin = “L”. Table 5. Sampling speed in parallel mode **Table 6. Master clock frequency in parallel mode (“*”; refer to Table 7.)** The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically. Table 7. Auto Setting Mode in parallel mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)

Table 8. Master clock frequency example at power-up etc., the AK4620A is in the power-down mode until MCLK is provided. MSB justified formats by zeroing the unused LSBs. Table 9. Audio data format (Serial Mode) Table 10. Audio data format (Parallel Mode)

Figure 6. Mode 4 Timing

The AK4620A includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments. the register is “1”, the IPGA changes and when the MSB = “0” the IATT changes. The IPGA is an analog volume control that improves the S/N ratio compared with digital volume controls (Table 11). becomes invalid. The timer (channel independent) for time-out is reset and the timer restarts for the new IPGA value. ZCEI bits in the control register enable zero-crossing detection. values has 29 levels and is done by soft changes, eliminating any switching noise. Table 11. IPGA+ADC S/N (typ.) Table 12. LRCK cycles for timeout period and all 256 levels is shown in Table 13.

1 Level

Table 13. ATT Transition Time

“L” for 516/fs (=10.8ms @fs=48kHz) after PDN pin = “↑”, and then overflow detection is enabled. this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity of the DZF pin. always enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits. bits are ignored. The setting value is held even if PCM mode and DSD mode are switched. Table 14. De-emphasis control (Normal Speed Mode)

can be controlled in differential mode. Table 15. ADC Input Mode in parallel mode Table 16. ADC Input Mode in serial mode (X: Don’t care) source without stopping the signal transmission. at ATT_DATA=255 in Normal Speed Mode. (2) Analog output corresponding to digital input has group delay (GD). and returned to ATT level by the same cycle. to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”. Figure 10. Soft Mute and Zero Detection

the registers (PWAD bit, PWDA bit).

  • INITA: Initializing period of ADC analog section (516/fs).
  • PD: Power down state. The contents of all registers are held.
  • XXH, YYH: The current value in ATT registers.
  • FI: Fade in. After exiting power down and reset state, ATT value fades in.
  • FADE: After exiting power down and reset state, ATT value fades in/out. (1) When RSTDA is “L” and OATT value is written to “XXH”, OATT value changes from FFH to XXH according to fade operation. (2) When PWDA is “L” and OATT value is written to “YYH”, OATT value changes from XXH to YYH according to fade operation.
  • AOUT: Some pop noise may occur at “*”.

Figure 11. Reset & Power down sequence in serial mode

In parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN pin is set to “H”.

  • INITA: Initializing period of ADC analog section (516/fs).
  • PD: Power down state.
  • FI: Fade in. After exiting power down and reset state, ATT value fades in.
  • AOUT: Some pop noise may occur at “*”.

Figure 12. Reset & Power Down Sequence in parallel mode

chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values. Table 17. Function List (X: available, -: not available) Figure 13. Control I/F Timing

  • READ command is not supported.
  • The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.

[AK4620A] MS0368-E-00 - 29 - „ Register Map Addr Register Name 00H Power Down Control SLOW DZFB ZOE ZOS PWVR PWAD PWDA 01H Reset Control D/P DCKS DCKB AML AMR RSTAD RSTDA 02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 03H Deem and Volume Control SMUTE HPRN HPLN ZCEI ZTM1 ZTM0 DEM1 DEM0 04H Lch IPGA Control IPGL7 IPGL6 IPGL5 IPGL4 IPGL3 IPGL2 IPGL1 IPGL0 05H Rch IPGA Control IPGR7 IPGR6 IPGR5 IPGR4 IPGR3 IPGR2 IPGR1 IPGR0 06H Lch ATT Control ATTL7 ATTL6 ATTL5 ATTL4 ATTL3 ATTL2 ATTL1 ATTL0 07H Rch ATT Control ATTR7 ATTR6 ATTR5 ATTR4 ATTR3 ATTR2 ATTR1 ATTR0 Note: Data should not be written to addresses 08H through 1FH. PDN pin = “L” resets the registers to their default values. „ Control Register Setup Sequence When the PDN pin goes “L” to “H” upon power-up etc., the AK4620A will be ready for normal operation by the next sequence. In this case, all control registers are set to default values and the AK4620A is in the reset state. (1) Set the clock mode and the audio data interface mode. (2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H). (3) ADC output and DAC output should be muted externally until canceling each reset state. The clock mode should be changed after setting RSTAD bit and RSTDA bit to “0”. At that time, ADC outputs and DAC outputs should be muted externally.

[AK4620A] MS0368-E-00 - 30 - „ Register Definitions Addr Register Name 00H Power Down Control SLOW DZFB ZOE ZOS PWVR PWAD PWDA DEFAULT PWDA: DAC power down 0: Power down 1: Power up (Default) “0” powers down only the DAC section and then the AOUTs go to Hi-Z immediately. The contents of all registers are not initialized and enabled to write to the registers. After exiting power down mode, the OATTs fade in/out the setting value of the control register (06H & 07H). The analog output should be muted externally as some pop noise may occur when entering and exiting this mode. PWAD: ADC power down 0: Power down 1: Power up (Default) “0” powers down only the ADC and then the SDTO goes “L” immediately. The IPGAs also go “00H”, but the contents of all registers are not initialized and enabled to write to the registers. After exiting power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output “0” during first 516 LRCK cycles. PWVR: Vref power down 0: Power down 1: Power up (Default) “0” powers all sections down and then both ADC and DAC do not operate. The contents of all register values are not initialized and enabled to write to the registers. When PWAD and PWDA bits go to “0” and PWVR bit goes to “1”, only the VREF section can be powered up. ZOS: Zero-detection/ Overflow-detection control for #15 and 16 pins. 0: Overflow detection for ADC input (Default) 1: Zero detection for DAC input. ZOE: Zero-detection / Overflow-detection Disable 0: Enable (Default) 1: Disable. Outputs “L”. DZFB: Inverting Enable of DZF 0: DZF goes “H” at Zero Detection (Default) 1: DZF goes “L” at Zero Detection SLOW: DAC Slow Roll-off Filter Enable 0: Sharp Roll-off Filter (Default) 1: Slow Roll-off Filter

[AK4620A] MS0368-E-00 - 31 - Addr Register Name 01H Reset Control D/P DCKS DCKB AML AMR RSTAD RSTDA DEFAULT RSTDA: DAC reset 0: Reset (Default) 1: Normal Operation “0” resets the internal timing and the AOUTs go to VCOM voltage immediately. The contents of all registers are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in the setting values of the control register (06H & 07H). The analog outputs should be muted externally since pop noise may occur when entering to and exiting from this mode. RSTAD: ADC reset 0: Reset (Default) 1: Normal Operation “0” resets the internal timing and then SDTO goes to “L” immediately. The IPGAs also go “00H”, but the contents of all registers are not initialized and enabled to write to the register. After exiting the power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, the ADCs output “0” during first 516 LRCK cycles. AML, AMR: default “0” (see Table 16) DCKB: Polarity of DCLK (DSD Only) 0: DSD data is available upon DCLK falling edge. (Default) 1: DSD data is available upon DCLK rising edge. DCKS: Master Clock Frequency Select at DSD mode (DSD only) 0: 512fs (Default) 1: 768fs D/P: DSD/PCM Mode Select 0: PCM mode (Default) 1: DSD mode Addr Register Name 02H Clock and Format Control DIF2 DIF1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 DEFAULT DFS1-0: Sampling Speed Control (see Table 2) Default: Normal speed CMODE, CKS1-0: Master Clock Frequency Select (see Table 3) Default: 256fs DIF2-0: Audio data interface modes (see Table 9) 000: Mode 0 001: Mode 1 010: Mode 2 011: Mode 3 100: Mode 4 Default: 24bit MSB justified for both ADC and DAC

[AK4620A] MS0368-E-00 - 32 - Addr Register Name 03H Deem and Volume Control SMUTE HPRN HPLN ZCEI ZTM1 ZTM0 DEM1 DEM0 DEFAULT DEM1-0: De-emphasis response (see Table 3) 00: 44.1kHz 01: OFF (Default) 10: 48kHz 11: 32kHz ZTM1-0: Zero-crossing timeout period select (see Table 11) Default: 1024fs ZCEI: ADC IPGA Zero crossing enable 0: Input PGA gain changes occur immediately 1: Input PGA gain changes occur only on zero-crossing or after timeout. (Default) HPLN/RN: Left/Right channel Digital High Pass Filter Disable 0: Enable (Default) 1: Disable SMUTE: DAC Input Soft Mute control 0: Normal operation (Default) 1: DAC outputs soft-muted The soft mute is independent of the output ATT and performed digitally.

The AK4620A includes two channel-independent analog volumes (IPGA), each with 32 levels in 0.5dB increments. is the crossover point of the IPGA and DATT, and both IPGA/IATT are set to 0dB. cycles. IATTs can be controlled in differential mode. Digital volume with 0.5dB/step. Soft-changes between each level. Table 10. IPGA code table

  • AGND and DGND must be connected to the same analog ground plane.
  • All digital input pins must not be left floating.

OVFR/DZFR pin and OVFL/DZFL pin to avoid the coupling from SDTO pin. Figure 15. Typical Connection Diagram (Single-ended mode)

Figure 16. Ground Layout

  1. Grounding and Power Supply Decoupling

should be as near to the AK4620A as possible, with the small value ceramic capacitor being the nearest. to avoid unwanted coupling into the AK4620A.

filter (RC filter) to attenuate noise around 128fs. LPF (fc=370kHz) composed of op-amp. The evaluation board should be referred about the detail. Figure 17. Input Buffer example in differential mode

op-amp. Figure 19 shows an example of differential outputs and LPF circuit example by three op-amps. Figure 18. External LPF Circuit Example 1 for PCM (fc = 136kHz, Q=0.694) Table 18. Filter Response of External LPF Circuit Example 1 for PCM

Figure 19. External LPF Circuit Example 2 for PCM Table 19. Filter Response of External LPF Circuit Example 2 for PCM

filter response by combination of the internal filter (Table 20) and an external filter (Figure 20). Table 20. Internal Filter Response at DSD mode Figure 20. External 3rd order LPF Circuit Example for DSD Table 21. 3rd order LPF (Figure 20) Response

[AK4620A] MS0368-E-00 - 41 - PACKAGE Detail A NOTE: Dimension "*" does not include mold flash. 0.22±0.1 0.65 *9.7±0.1 1.5MAX A 30pin VSOP (Unit: mm) 5.6±0.1 7.6±0.2 0.45±0.2 -0.05 +0.10 0.3 0.15 0.12 M 0.08 1.2±0.10 0.10 +0.10 -0.05 „ Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb Free)

[AK4620A] MS0368-E-00 - 42 - MARKING AKM AK4620AVF XXXBYYYYC XXXBYYYYC Date code identifier XXXB : Lot number (X : Digit number, B : Alpha character) YYYYC : Assembly date (Y : Digit number, C : Alpha character)

Revision History

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Contents

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