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[AK4601] 016000391-E-01 - 1 - 2016/12 1. General Description The AK4601 is an Audio HUB CODEC including 5ch ADC, 6ch DAC and digital mixers. The analog input block consists of a 24-bit stereo ADC, a 24-bit stereo ADC with input selector and a monaural ADC, and the analog output block consists of 32 -bit 6ch DAC. The transfer block for digital signals integrates a serial interface that supports Data BUS and TDM format, realizing an audio HUB function. It gives scalability to the device for both analog and digital signals. A car audio system that is capable of processing both sound and voice such as for hands -free function simultaneously can be re alized by using the AK4601 with AKM’s multi -core DSP, the AK7707. The AK4601 is available in a space saving 48-pin LQFP package. 2. Features □ ADC1: 24-bit Stereo ADC with MIC Gain Amplifiers - Sampling Frequency: fs=8kHz to 192kHz - Channel Independent Analog Gain Amplifiers (0 to 18dB(2dB Step), 18 to 36dB(3dB step)) - Differential Input or Single-ended Input - ADC Characteristics S/N: 106dB (fs=48kHz, Differential Input, MIC Gain=0dB,) - Channel Independent Digital Volume Control (+24 to -103dB, 0.5dB Step, Mute) - Digital HPF for DC Offset Cancelling - Low Noise MIC Power Output: 2ch - 4 types of Digital Filter for Sound Color Selection □ ADC2: 24-bit Stereo ADC with Input Selector - Sampling Frequency: fs=8kHz to 192kHz - Analog Input Selector: Differential Input x1 or Single-ended Input x2, Semi-Differential Input x1 - ADC Characteristics S/N: 106dB (fs=48kHz, Differential Input) - Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute) - Digital HPF for DC Offset Cancelling - 4 types of Digital Filter for Sound Color Selection □ ADCM: 24-bit Monaural ADC - Sampling Frequency: fs=8kHz to 192kHz - Differential Input or Single-ended Input - ADC Characteristics S/N: 106dB (fs=48kHz, Differential Input) - Channel Independent Digital Volume (+24 to -103dB, 0.5dB Step, Mute) - Digital HPF for DC Offset Cancelling - 4 types of Digital Filter for Sound Color Selection □ DAC: Advanced 32-bit DAC - 2ch x3 - Sampling Frequency: fs=8kHz to 192kHz - Single-ended Output - DAC Characteristics S/N: 108dB (fs=48kHz) - Channel Independent Digital Volume Control (+12 to -115dB, 0.5dB Step, Mute) - 4 types of Digital Filter for Sound Color Selection Audio HUB CODEC with Digital Mixer AK4601
[AK4601] 016000391-E-01 - 2 - 2016/12 □ Digital Interface: - Digital Input Port: max 20ch(16ch x 1Port, 2ch x 2Port) when TDM mode - Digital Output Port: max 20ch(16ch x 1Port, 2ch x 2Port) when TDM mode - Independent LRCK/BICK Input port x 2 Lines - Data Format: MSB 32,24-bit / LSB 24,20,16-bit / I2S - PCM Short / Long Frame Supported - TDM Format Supported □ Digital Mixer Circuit □ Independent Digital Volume (+12 to -115dB, 0.5dB Step, Mute) □ PLL Circuit □ μP Interface: SPI(7MHz max), I2C-bus (max 1MHz, Fast Mode Plus) □ Power Supply: - Analog AVDD: 3.0 to 3.6V (typ. 3.3V) - I/F TVDD: 1.7 to 3.6V (typ. 3.3V) □ Operating Temperature Range: -40°C to 85°C □ Package: 48-pin LQFP (7mm x 7mm, 0.5mm pitch)
[AK4601] 016000391-E-01 - 3 - 2016/12 3. Table of Contents
- Block Diagram and Functions
Figure 1. Block Diagram
[AK4601] 016000391-E-01 - 5 - 2016/12 5. Pin Configuration and Functions ■ Pin Layout AINMP / AINM AIN5R GNDIN5 AIN5L AIN2LN / AIN4L AIN2LP / AIN3L AIN2RN / AIN4R AIN2RP / AIN3R AIN1R / INP2 INN2 AIN1L / INP1 INN1 AVDD AINMN 37 24 MPWR2 AVDD 38 23 MPWR1 AVSS 39 22 MPREF VCOM 40 LVDD 21 TESTI VREFH 41 20 DVSS2 VREFL 42 19 LVDD AOUT1R 43 18 AVDRV AOUT1L 44 17 PDN AOUT2R 45 16 SI / I2CFIL AOUT2L 46 15 SCLK / SCL AOUT3R 47 14 SO/SDA AOUT3L 48 13 CSN TVDD1 CLKO BICK1 LRCK1 SDIN1 SDOUT1 DVSS1 TVDD SDOUT2 SDIN2 LRCK2/SDOUT3 BICK2 / SDIN3 MCKI 48pin LQFP ( Top View ) *** Input Output I / O Power Pins with framed name are pulled down internally.
[AK4601] 016000391-E-01 - 6 - 2016/12 ■ Pin Functions No. Pin Name I/O Function
1 CLKO O Master Clock Output Pin
2 BICK1 I/O Serial Bit Clock 1 Pin
3 LRCK1 I/O LR Channel Select Clock 1 Pin
4 SDIN1 I Serial Digital Data Input 1 Pin
5 SDOUT1 O Serial Digital Data Output 1 Pin
6 DVSS1 - Digital Ground 1 Pin 0V
7 TVDD - Digital I/F Power Supply Pin 1.7~3.6V (typ.3.3V)
8 SDOUT2 O Serial Data Output 2 Pin
9 SDIN2 I Serial Data Input 2 Pin
LR Channel Select Clock 2 Pin (MSELN bit = “L”, default) SDOUT3 Serial Data Output 3 Pin (MSELN bit = “H”) BICK2 I/O Serial Bit Clock 2 Pin (MSELN bit = “L”, default) SDIN3 Serial Data Input 3 Pin (MSELN bit = “H”)
12 MCKI I Master Clock Pin
13 CSN I
During power-down state or when μP I/F are not in use, leave this pin “H” level. SO O Serial Data Output Pin for SPI I/F This pin outputs “Hi-Z” during power-down state. SDA I/O Serial Data In/Output Pin for I2C I/F This pin outputs “Hi-Z” during power-down state.
15 SCLK I Serial Data Clock Input Pin for SPI I/F
SCL I Serial Data Clock Input Pin for I2C I/F SI I Serial Data Input Pin for SPI I/F I2CFIL I I2C I/F Mode Select Input Pin I2CFIL = “L”: Fast Mode (400kHz) I2CFIL = “H”: Fast Mode Plus (1MHz) (should be fixed to TVDD)
17 PDN I
Use this pin to power down the AK4601. The PDN pin should be held “L” when power is supplied.
[AK4601] 016000391-E-01 - 7 - 2016/12 No. Pin Name I/O Function
18 AVDRV O
Connect a 2.2uF ceramic capacitor between this pin and DVSS2. Do not connect this pin to an external circuit. 19 LVDD - Digital Core Power Supply Pin 3.0~3.6V (typ.3.3V)
20 DVSS2 - Digital Ground 2 Pin 0V
21 TESTI I Test Input Pin
It must be tied “L”.
22 MPREF O
Ripple Filter Pin for Microphone Power Supply Connect a 1uF ceramic capacitor between this pin and AVSS. Do not connect this pin to an external circuit.
23 MPWR1 O Power Supply Output 1 Pin for Microphone
This pin outputs “Hi-Z” during power-down state.
24 MPWR2 O Power Supply Output 2 Pin for Microphone
This pin outputs “Hi-Z” during power-down state.
25 INN1 I MIC Lch Inverted Differential Input 1 Pin
26 AIN1L I MIC Lch Single-ended Input 1 Pin
INP1 I MIC Lch Non-inverted Differential Input 1 Pin
27 INN2 I MIC Rch Inverted Differential Input 2 Pin
28 AIN1R I MIC Rch Single-ended Input 1 Pin
INP2 I MIC Rch Non-inverted Differential Input 2 Pin
29 AIN2RP I ADC2 Rch Non-inverted Differential Input 2 Pin
AIN3R I ADC2 Rch Single-ended Input 3 Pin
30 AIN2RN I ADC2 Rch Inverted Differential Input 2 Pin
AIN4R I ADC2 Rch Single-ended Input 4 Pin
31 AIN2LP I ADC2 Lch Non-inverted Differential Input 2 Pin
AIN3L I ADC2 Lch Single-ended Input 3 Pin
32 AIN2LN I ADC2 Lch Inverted Differential Input 2 Pin
AIN4L I ADC2 Lch Single-ended Input 4 Pin
33 AIN5L I ADC2 Lch Pseudo Differential Input 5 Pin
34 GNDIN5 I ADC2 Pseudo Differential Ground Input 5 Pin
35 AIN5R I ADC2 Rch Pseudo Differential Input 5 Pin
36 AINMP I ADCM Non-inverted Differential Input Pin
AINM I ADCM Single-ended Input Pin
37 AINMN I ADCM Inverted Differential Input Pin
38 AVDD - Analog Power Supply Pin 3.0~3.6V (typ.3.3V)
39 AVSS - Analog Ground Pin 0V
40 VCOM O
Analog Common Voltage Output Pin Connect a 2.2uF ceramic capacitor between this pin and AVSS. Do not connect this pin to an external circuit. This pin outputs “L” during power-down state.
41 VREFH I Analog High-level Reference Voltage Input Pin
42 VREFL I Analog Low-level Reference Voltage Input Pin
43 AOUT1R O DAC1 Rch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
44 AOUT1L O DAC1 Lch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
45 AOUT2R O DAC2 Rch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
46 AOUT2L O DAC2 Lch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
47 AOUT3R O DAC3 Rch Analog Output Pin
This pin outputs “Hi-Z” during power-down state.
48 AOUT3L O DAC3 Lch Analog Output Pin
This pin outputs “Hi-Z” during power-down state. Unused I/O pins must be connected appropriately. Table 1. Handling of Unused Pins
1 CLKO Pulled-down (50K) Output Output Output
2 BICK1 Pulled-down (50K) Input
3 LRCK1 Pulled-down (50K) Input
5 SDOUT1 Pulled-down (50K) Output Output Output
8 SDOUT2 Pulled-down (50K) Output Output Output
18 AVDRV Pulled-down (70Ω) Output Output Output
21 TESTI Pulled-down (25K) Pulled-down (25K) Pulled-down (25K) Pulled-down (25K)
Table 2. Pull-down Pin Statuses (x=1~2)
1 CLKO O “L” Output 23 MPWR1 O “Hi-Z” Output
2 BICK1 I/O Input 24 MPWR2 O “Hi-Z” Output
3 LRCK1 I/O Input 40 VCOM O “L” Output
5 SDOUT1 O “L” Output 43 AOUT1R O “Hi-Z” Output
8 SDOUT2 O “L” Output 44 AOUT1L O “Hi-Z” Output
10 LRCK2/ SDOUT3 I/O Input 45 AOUT2R O “Hi-Z” Output
11 BICK2/SDIN3 I/O Input 46 AOUT2L O “Hi-Z” Output
14 SO/SDA I/O “Hi-Z” Output 47 AOUT3R O “Hi-Z” Output
18 AVDRV O “L” Output 48 AOUT3L O “Hi-Z” Output
22 MPREF O “L” Output
Table 3. Power-down Status of Output Pins
[AK4601] 016000391-E-01 - 11 - 2016/12 6. Absolute Maximum Ratings (AVSS=DVSS1=DVSS2=0V; Note 1) Parameter Symbol Min. Max. Unit Power Supplies Analog Digital1(Core) Digital2(I/F) Difference (AVSS, DVSS1 ~ 2) (Note 1) AVDD LVDD TVDD ΔGND -0.3 -0.3 -0.3 -0.3 4.3 4.3 4.3 0.3 V V V V Input Current (except power supply pins) IIN － ±10 mA Analog Input Voltage (Note 2) VINA -0.3 (AVDD+0.3) or 4.3 V Digital Input Voltage (Note 3) VIND1 -0.3 (TVDD+0.3) or 4.3 V Ambient Temperature (Power applied) Ta -40 85 C Storage Temperature Tstg -65 150 C Note 1. All voltages are with respect to ground. AVSS and DVSS1-2 must be connected to the same ground. Note 2. The maximum analog input voltage is a smaller value between (AVDD+0.3)V and 4.3V. Note 3. The maximum digital input voltage of SDIN1, SDIN2, BICK2/SDIN3, LRCK1, BICK1, MCKI, LRCK2/SDOUT3, PDN, SCLK/SCL, SO/SDA, CSN, SI/I2CFIL pins is a smaller value between (TVDD+0.3)V and 4.3V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operating Conditions (AVSS=DVSS1=DVSS2=0V; Note 1) Parameter Symbol Min. Typ. Max. Unit Power Supplies Analog Digital1(Core) Digital2(I/F) Difference1 Difference2 AVDD LVDD TVDD AVDD – LVDD LVDD – TVDD 3.0 3.0 1.7 -0.1 -0.1 3.3 3.3 3.3 3.6 3.6 3.6 +0.1 V V V V V Note 4. The power-up sequence with AVDD, LVDD, TVDD is not critical. The PDN pin should be held “L” when power is supplied. The PDN pin is allowed to be “H” after all power supplies are applied and settled. Note 5. Do not turn off the power supply of the AK4601 with the power supply of the peripheral device turned on when using the I2C interface. Pull-up resistors of SDA and SCL pins should be connected to TVDD or less voltage. WARNING: AKM assumes no responsibility for the usage beyond the conditions in the datasheet.
[AK4601] 016000391-E-01 - 12 - 2016/12 8. Electrical Characteristics ■ Analog Characteristics 1. MIC AMP Gain (Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1=DVSS2=0V, ADC1VL/R bit = “0”) MIC AMP Parameter Min. Typ. Max. Unit Input Impedance 14 20 26 kΩ Gain MGNL[3:0]bits=0h, MGNR[3:0]bits=0h -1 0 1 dB MGNL[3:0]bits=1h, MGNR[3:0]bits=1h 1 2 3 MGNL[3:0]bits=2h, MGNR[3:0]bits=2h 3 4 5 MGNL[3:0]bits=3h, MGNR[3:0]bits=3h 5 6 7 MGNL[3:0]bits=4h, MGNR[3:0]bits=4h 7 8 9 MGNL[3:0]bits=5h, MGNR[3:0]bits=5h 9 10 11 MGNL[3:0]bits=6h, MGNR[3:0]bits=6h 11 12 13 MGNL[3:0]bits=7h, MGNR[3:0]bits=7h 13 14 15 MGNL[3:0]bits=8h, MGNR[3:0]bits=8h 15 16 17 MGNL[3:0]bits=9h, MGNR[3:0]bits=9h 17 18 19 MGNL[3:0]bits=Ah, MGNR[3:0]bits=Ah 20 21 22 MGNL[3:0]bits=Bh, MGNR[3:0]bits=Bh 23 24 25 MGNL[3:0]bits=Ch, MGNR[3:0]bits=Ch 26 27 28 MGNL[3:0]bits=Dh, MGNR[3:0]bits=Dh 29 30 31 MGNL[3:0]bits=Eh, MGNR[3:0]bits=Eh 32 33 34 MGNL[3:0]bits=Fh, MGNR[3:0]bits=Fh 35 36 37 2. MIC Bias Output (Ta=25C; AVDD=VREFH=LVDD=TVDD =3.3V; AVSS=VREFL=DVSS1=DVSS2=0V; Measurement Frequency = 20Hz~20kHz) MIC Bias Parameter Min. Typ. Max. Unit Output Voltage 2.3 2.5 2.7 V Load Resistance 2 kΩ Load Capaitance 30 pF Output Noise (A -weighted) -114 -108 dBV
[AK4601] 016000391-E-01 - 13 - 2016/12 3. MIC AMP + ADC1 (Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL= DVSS1= DVSS2 =0V; Signal Frequency =1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz; Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz; ADC1VL/R bit =”0”; MGNL/R[3:0] bits = 0h (0dB)) MIC AMP + ADC1 Parameter Min. Typ. Max. Unit Resolution 24 bit Differential Input Full-scale Input Voltage Vpp (Note 8) ±0.264 ±0.290 ±0.315 S/(N+D) (-1dBFS) fs=48kHz (Note 7) 85 95 dB fs=48kHz (Note 8) 87 fs=96kHz (Note 7) 92 fs=96kHz (Note 8) 84 fs=192kHz (Note 7) 92 fs=192kHz (Note 8) 84 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) (Note 7) 98 106 dB fs=48kHz (A-weighted) (Note 8) 95 fs=96kHz (Note 7) 99 fs=96kHz (Note 8) 89 fs=192kHz (Note 7) 99 fs=192kHz (Note 8) 89 S/N fs=48kHz (A-weighted) (Note 7) 98 106 dB fs=48kHz (A-weighted) (Note 8) 95 fs=96kHz (Note 7) 99 fs=96kHz (Note 8) 89 fs=192kHz (Note 7) 99 fs=192kHz (Note 8) 89 Inter-Channel Isolation (Note 6) 90 105 dB Channel Gain Mismatch 0.0 0.3 dB PSRR (Note 7, Note 10) 50 dB CMRR (Note 11) 60 80 dB
[AK4601] 016000391-E-01 - 14 - 2016/12 Parameter Min. Typ. Max. Unit Single-ended Input Full-scale Input Voltage (Note 7) 2.1 2.3 2.5 Vpp (Note 8) 0.264 0.290 0.315 (Note 9) 2.55 2.83 3.11 S/(N+D) (-1dBFS) fs=48kHz (Note 7) 85 95 dB fs=48kHz (Note 8) 87 fs=96kHz (Note 7) 92 fs=96kHz (Note 8) 84 fs=192kHz (Note 7) 92 fs=192kHz (Note 8) 84 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) (Note 7) 96 104 dB fs=48kHz (A-weighted) (Note 8) 92 fs=96kHz (Note 7) 97 fs=96kHz (Note 8) 86 fs=192kHz (Note 7) 97 fs=192kHz (Note 8) 86 S/N fs=48kHz (A-weighted) (Note 7) 96 104 dB fs=48kHz (A-weighted) (Note 8) 92 fs=96kHz (Note 7) 97 fs=96kHz (Note 8) 86 fs=192kHz (Note 7) 97 fs=192kHz (Note 8) 86 Inter-Channel Isolation (Note 6) 90 105 dB Channel Gain Mismatch 0.0 0.3 dB PSRR (Note 7, Note 10) 50 dB Note 6. Inter-channel isolation with -1dBFS signal input between Lch and Rch. Note 7. ADC1VL/R bit = “0”,MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is propotional to AVDD (0.7 x AVDD). Note 8. ADC1VL/R bit = “0”,MGNL/R[3:0] bits = 9h (+18dB). Input full-scale voltage is propotional to AVDD (0.088 x AVDD). Note 9. ADC1VL/R bit = “1”, MGNL/R[3:0] bits = 0h (0dB). Input full-scale voltage is propotional to AVDD (0.86 x AVDD). Note 10. PSRR is applied to AVDD and VREFH with 1kHz, 50mVpp. Note 11. Common mode rejection ratio is applied 1kHz and 100mVpp sine waves to both differential input pins. It is defined as a reference value when appling 1kHz and ±100mVpp sine waves to the differential input.
[AK4601] 016000391-E-01 - 15 - 2016/12 4. ADC2 (Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1= DVSS2=0V; Signal Frequency=1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz; Measurement Frequency BW=20Hz~40kHz @fs=96kHz,192kHz; ADC2VL/R bit =”0”) ADC2 Parameter Min. Typ. Max. Unit Resolution 24 bit Input Impedance 14 20 26 kΩ Differential Input Full-scale Input Voltage (Note 12) S/(N+D) (-1dBFS) fs=48kHz 85 95 dB fs=96kHz 92 fs=192kHz 92 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 98 106 dB fs=96kHz 99 fs=192kHz 99 S/N fs=48kHz (A-weighted) 98 106 dB fs=96kHz 99 fs=192kHz 99 Inter-Channel Isolation (Note 6) 90 105 dB Channel Gain Mismatch 0.0 0.3 dB PSRR (Note 10) 50 dB CMRR (Note 11) 60 80 dB Single-ended Input, Pseudo-differential Input Full-scale Input Voltage (Note 15) S/(N+D) (-1dBFS) fs=48kHz 85 95 dB fs=96kHz 92 fs=192kHz 92 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 96 104 dB fs=96kHz 97 fs=192kHz 97 S/N fs=48kHz (A-weighted) 96 104 dB fs=96kHz 97 fs=192kHz 97 Inter-Channel Isolation (Note 6) 90 105 dB Channel Gain Mismatch 0.0 0.3 dB PSRR (Note 10) 50 dB CMRR (Pseudo-differential) (Note 16) 55 75 dB Note 12. AIN2LP, AIN2LN, AIN2RP and AIN2RN pins. Note 13. ADC2VL/R bit = “0”. Input full-scale voltage is propotional to AVDD (0.7 x AVDD). Note 14. ADC2VL/R bit = “0”. Input full-scale voltage is propotional to AVDD (0.86 x AVDD). Note 15. AIN3L, AIN3R, AIN4L, AIN4R, AIN5L and AIN5R pins. Note 16. Common mode rejection ratio is applied 1kHz and 100mVpp sine waves to both Pseudo-differential input and Pseudo-differential ground input pins. It is defined as a reference value when appling 100mVpp sine wave to the Pseudo-differential input.
[AK4601] 016000391-E-01 - 16 - 2016/12 5. ADCM (Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1=DVSS2=0V; Signal Frequency=1kHz; 24bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz; Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz; ADCMV bit =”0”) ADCM Parameter Min. Typ. Max. Unit Resolution 24 bit Input Impedance 14 20 26 kΩ Differential Input Full-scale Input Voltage (Note 17) S/(N+D) (-1dBFS) fs=48kHz 85 95 dB fs=96kHz 92 fs=192kHz 92 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 98 106 dB fs=96kHz 99 fs=192kHz 99 S/N fs=48kHz (A-weighted) 98 106 dB fs=96kHz 99 fs=192kHz 99 PSRR (Note 10) 50 dB CMRR (Note 11) 60 80 dB Single-ended Input Full-scale Input Voltage (Note 20) S/(N+D) (-1dBFS) fs=48kHz 85 95 dB fs=96kHz 92 fs=192kHz 92 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 96 104 dB fs=96kHz 97 fs=192kHz 97 S/N fs=48kHz (A-weighted) 96 104 dB fs=96kHz 97 fs=192kHz 97 PSRR (Note 10) 50 dB Note 17. AINMP and AINMN pins. Note 18. ADCMV bit = “0”. Input full-scale voltage is propotional to AVDD (0.7 x AVDD). Note 19. ADCMV bit = “1”. Input full-scale voltage is propotional to AVDD (0.86 x AVDD). Note 20. AINM pin
[AK4601] 016000391-E-01 - 17 - 2016/12 6. DAC (Ta=25C; AVDD=VREFH=LVDD=TVDD=3.3V; AVSS=VREFL=DVSS1= DVSS2=0V; SignalFrequency=1kHz; 32bit Data; BICK=64fs; Measurement Frequency BW=20Hz ~ 20kHz @fs=48kHz;Measurement Frequency BW=20Hz ~ 40kHz @fs=96kHz,192kHz) DAC1 DAC2 DAC3 Parameter Min. Typ. Max. Unit Resolution 32 bit Output Voltage (Note 21) 2.55 2.83 3.11 Vpp S/(N+D) (0dBFS) fs=48kHz 80 91 dB fs=96kHz 89 fs=192kHz 89 Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 100 108 dB fs=96kHz 101 fs=192kHz 101 S/N fs=48kHz (A -weighted) 100 108 dB fs=96kHz 101 fs=192kHz 101 Inter-Channel Isolation (fin=1kHz) (Note 22) 90 110 dB Channel Gain Mismatch 0.0 0.7 dB Load Resistance (Note 23) 10 kΩ Load Capacitance 30 pF PSRR (Note 10) 50 dB Note 21. Full-scale output Voltage. Output full-scale voltage is propotional to AVDD (0.86 x AVDD). Note 22. Inter-channel isolation between each DAC of Lch and Rch with 0dBFS signal input. (AOUT1L and AOUT1R, AOUT2L and AOUT2R and AOUT3L and AOUT3R) Note 23. to AC Load.
[AK4601] 016000391-E-01 - 18 - 2016/12 ■ Power Consumption TVDD=1.7~3.6V(typ=3.3V, max=3.6V); AVSS=VREFL=DVSS1=DVSS2=0V) Parameter Symbol Min. Typ. Max. Unit Operation Current Consumption (Note 24) (PDN pin= “H”) AVDD 30 43 mA LVDD 13.5 30 mA TVDD 5 8 mA Power-down Current (PDN pin= “L”) AVDD 0.01 mA LVDD 0.01 mA TVDD 0.01 mA Note 24. The current consumption of LVDD varies depending on the system frequency.
[AK4601] 016000391-E-01 - 19 - 2016/12 9. Digital Filter Characteristics 1. ADC Block =DVSS2=0V) 1-1 Sharp Roll-Off Filter (ADSD bit = “0”, ADSL bit = “0”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 25) 0dB/-0.06dB PB 0 - 22.1 kHz -3.0dB PB - 23.7 - kHz Stopband (Note 25) SB 27.8 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~20kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 20 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.0 - Hz fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 25) 0dB/-0.06dB PB 0 - 44.2 kHz -3.0dB PB - 47.5 - kHz Stopband (Note 25) SB 55.6 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 20 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.9 - Hz fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 25) 0dB/-0.04dB PB 0 - 83.7 kHz -3.0dB PB - 96.0 - kHz Stopband (Note 25) SB 122.9 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 16 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 3.9 - Hz
[AK4601] 016000391-E-01 - 20 - 2016/12 1-2 Slow Roll-Off Filter (ADSD bit = “0”, ADSL bit = “1”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 25) 0dB/-0.074dB PB 0 - 12.5 kHz -3.0dB - 19.2 - kHz Stopband (Note 25) SB 36.5 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~20kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 8 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.0 - Hz fs=96kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 25) 0dB/-0.074dB PB 0 - 25 kHz -3.0dB - 38.5 - kHz Stopband (Note 25) SB 73 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 8 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.9 - Hz fs=192kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 25) 0dB/-0.1dB PB 0 - 31.1 kHz -3.0dB - 62.3 - kHz Stopband (Note 25) SB 145.9 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - 0 - 1/fs Group Delay (Note 26) GD - 9 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 3.88 - Hz
[AK4601] 016000391-E-01 - 21 - 2016/12 1-3 Short Delay Sharp Roll-Off Filter (ADSD bit = “1”, ADSL bit = “0”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 25) 0dB/-0.06dB PB 0 - 22.1 kHz -3.0dB - 23.7 - kHz Stopband (Note 25) SB 27.8 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~20kHz GD - - 2.6 1/fs Group Delay (Note 26) GD - 6 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.0 - Hz fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 25) 0dB/-0.06dB PB 0 - 44.2 kHz -3.0dB - 47.5 - kHz Stopband (Note 25) SB 55.6 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - - 2.6 1/fs Group Delay (Note 26) GD - 6 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.9 - Hz fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 25) 0dB/-0.04dB PB 0 - 83.7 kHz -3.0dB - 96.0 - kHz Stopband (Note 25) SB 122.9 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - 0 0.2 1/fs Group Delay (Note 26) GD - 7 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 3.88 - Hz
[AK4601] 016000391-E-01 - 22 - 2016/12 1-4 Short Delay Slow Roll-Off Filter (ADSD bit = “1”, ADSL bit = “1”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 25) 0dB/-0.074dB PB 0 - 12.5 kHz -3.0dB - 19.2 - kHz Stopband (Note 25) SB 36.5 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~20kHz GD - - 2.6 1/fs Group Delay (Note 26) GD - 6 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.0 - Hz fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 25) 0dB/-0.074dB PB 0 - 25 kHz -3.0dB - 38.5 - kHz Stopband (Note 25) SB 73 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - - 2.6 1/fs Group Delay (Note 26) GD - 6 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 1.9 - Hz fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 25) 0db/-0.1dB PB 0 - 31.1 kHz -3.0dB - 63.2 - kHz Stopband (Note 25) SB 145.9 - - kHz Stopband Attenuation SA 85 - - dB Group Delay Distortion : 0Hz~40kHz GD - - 0.5 1/fs Group Delay (Note 26) GD - 7 - 1/fs ADC Digital Filter(HPF) Frequency Response -3.0dB FR - 3.88 - Hz Note 25. The passband and stopband frequencies are proportional to fs (sampling rate). High-pass filter characteristics are not included. A reference value of each passband and stopband frequency is the maximum value of frequency response. Note 26. Delay time caused by the digital filter calculation. This time is measured from an impulse signal input until impulse data are set into the output register. It includes group delay by HPF.
[AK4601] 016000391-E-01 - 23 - 2016/12 2. DAC Block DVSS2=0V) 2-1 Sharp Roll-Off Filter (DASD bit = “0”, DASL bit = “0”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 21.7 kHz 3.0dB PB 23.4 kHz Passband Ripple (Note 28) PR -0.0032 0.0032 dB Stopband (Note 27) SB 26.3 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 27.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 20.0kHz -0.3 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 43.5 kHz 3.0dB PB 46.8 kHz Passband Ripple (Note 28) PR -0.0032 0.0032 dB Stopband (Note 27) SB 52.5 0 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 27.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 40.0kHz -0.5 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 87.0 kHz 3.0dB PB 93.6 kHz Passband Ripple (Note 28) PR -0.0032 0.0032 dB Stopband (Note 27) SB 105 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 27.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 80.0kHz -1.9 0.1 dB Note 27. The passband and stopband frequencies are proportional to fs (sampling rate). “PB=0.4535 fs, SB=0.546 fs” Note 28. Pass-band gain amplitude of double seep over sampling filter at the first step of Interpolator. Note 29. Delay time caused by the digital filter calculation. This time is measured from setting of the 16/20/24/32-bit impulse data to the input registers to output of the analog peak signal. Note 30. The output level with a 1kHz, 0dB sine wave input is defined as 0dB. Note 31. Band width of Stopband Attenuation ranges from 0kHz to fs.
[AK4601] 016000391-E-01 - 24 - 2016/12 2-2 Slow Roll-Off Filter (DASD bit = “0”, DASL bit = “1”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 32) 0.05dB PB 0 8.8 kHz 3.0dB PB 19.8 kHz Passband Ripple (Note 28) PR -0.043 0.043 dB Stopband (Note 32) SB 42.7 kHz Stopband Attenuation (Note 30, Note 31) SA 73 dB Group Delay (Note 29) GD - 6.8 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 20.0kHz -5.0 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 32) 0.05dB PB 0 17.7 kHz 3.0dB PB 39.5 kHz Passband Ripple (Note 28) PR -0.043 0.043 dB Stopband (Note 32) SB 85.3 kHz Stopband Attenuation (Note 30, Note 31) SA 73 dB Group Delay (Note 29) GD - 6.8 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 40.0kHz -5.2 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit SLOW ROLL-OFF Passband (Note 32) 0.05dB PB 0 35.5 kHz 3.0dB PB 79.0 kHz Passband Ripple (Note 28) PR -0.043 0.043 dB Stopband (Note 32) SB 171 kHz Stopband Attenuation (Note 30, Note 31) SA 73 dB Group Delay (Note 29) GD - 6.8 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 80.0kHz -5.90 0.1 dB Note 32. The passband and stopband frequencies are proportional to fs (sampling rate). “PB=0.185 fs, SB=0.888 fs”
[AK4601] 016000391-E-01 - 25 - 2016/12 2-3 Short Delay Sharp Roll-Off Filter (DASD bit = “1”, DASL bit = “0”) fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 21.7 kHz 3.0dB PB 23.4 kHz Passband Ripple (Note 28) PR -0.0031 0.0031 dB Stopband (Note 27) SB 26.3 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 20.0kHz -0.3 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 43.5 kHz 3.0dB PB 46.8 kHz Passband Ripple (Note 28) PR -0.0031 0.0031 dB Stopband (Note 27) SB 52.5 0 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 40.0kHz -0.5 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SHARP ROLL-OFF Passband (Note 27) 0.05dB PB 0 87.0 kHz 3.0dB PB 93.6 kHz Passband Ripple (Note 28) PR -0.0031 0.0031 dB Stopband (Note 27) SB 105 kHz Stopband Attenuation (Note 30, Note 31) SA 80 dB Group Delay (Note 29) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 80.0kHz -1.9 0.1 dB
[AK4601] 016000391-E-01 - 26 - 2016/12
9.4 Short Delay Slow Roll-Off Filter (DASD bit = “1”, DASL bit = “1”)
fs=48kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 33) 0.05dB PB 0 12.0 kHz 3.0dB PB 21.1 kHz Passband Ripple (Note 28) PR -0.05 0.05 dB Stopband (Note 33) SB 41.5 kHz Stopband Attenuation (Note 30, Note 31) SA 82 dB Group Delay (Note 29) GD - 5.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 20.0kHz -4.8 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 33) 0.05dB PB 0 24.2 kHz 3.0dB PB 42.1 kHz Passband Ripple (Note 28) PR -0.05 0.05 dB Stopband (Note 33) SB 83.0 kHz Stopband Attenuation (Note 30, Note 31) SA 82 dB Group Delay (Note 29) GD - 5.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 40.0kHz -5.0 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit SHORT DELAY SLOW ROLL-OFF Passband (Note 33) 0.05dB PB 0 48.4 kHz 3.0dB PB 84.3 kHz Passband Ripple (Note 28) PR -0.05 0.05 dB Stopband (Note 33) SB 165.9 kHz Stopband Attenuation (Note 30, Note 31) SA 82 dB Group Delay (Note 29) GD - 5.3 - 1/fs Digital Filter + SCF + SMF (Note 30) Frequency Response: 0 80.0kHz -5.7 0.1 dB Note 33. The passband and stopband frequencies are proportional to fs (sampling rate). “PB=0.252 fs, SB=0.864 fs”
[AK4601] 016000391-E-01 - 27 - 2016/12 10. DC Characteristics ■ DC Characteristics DVSS2=0V) Parameter Symbol Min. Typ. Max. Unit High-Level Input Voltage 1 (Note 34) VIH1 80%TVDD V Low-Level Input Voltage 1 (Note 34) VIL1 20%TVDD V High-Level Input Voltage 2 (Note 35) VIH2 70%TVDD V Low-Level Input Voltage 2 (Note 35) VIL2 30%TVDD V High-Level Output Voltage Iout= -100A (Note 34) VOH1 TVDD-0.3 V Low-Level Output Voltage Iout=100A (Note 34) VOL1 0.3 V SDA Low Level Output Voltage Fast Mode TVDD ≥ 2.0V (Iout=3mA) VOL2 0.4 V TVDD < 2.0V (Iout=3mA) VOL2 20%TVDD V Fast Mode Plus TVDD ≥ 2.0V (Iout=20mA) VOL2 0.4 V TVDD < 2.0V (Iout=3mA) VOL2 20%TVDD V Input Leak Current (Note 36) Iin ±10 A Note 34. CLKO, SDIN1, SDIN2, BICK2/SDIN3, SDOUT1, SDOUT2, LRCK2/SDOUT3, LRCK1, BICK1, PDN, SCLK, SO, CSN and SI/I2CFIL pins. Note 35. SCL and SDA pins. Note 36. SDIN1, SDIN2, SDIN3, PDN, SCLK/SCL, SO/SDA, CSN and SI/I2CFIL pins.
[AK4601] 016000391-E-01 - 28 - 2016/12 11. Switching Characteristics 1. System Clock DVSS2=0V; CL=20pF) Parameter Symbol Min. Typ. Max. Unit MCKI Input Timing Duty Cycle Duty 40 50 60 % Input Frequency fCLK 0.256 24.576 MHz CLKO Output Timing Output Frequency fCLKO 2.048 24.576 MHz Duty Cycle dCLKO 50 % LRCK/BICK Input Timing (Slave Mode) LRCK Input Timing Frequency fs 8 192 kHz BICK Input Timing Frequency (Note 37) fBCLK 0.256 24.576 MHz Pulse Width Low tBCLKL 0.4 / fBCLK ns Pulse Width High tBCLKH 0.4 / fBCLK ns LRCK/BICK Output Timing (Master Mode) LRCK Output Timing Frequency fs 8 192 kHz Pulse Width High PCM Short/Long Frame I2S/DSP Mode tLRCKH tLRCKH 1/fBCLK ns BICK Output Timing Frequency (Note 37) fBCLK 0.256 24.576 MHz Duty dBCLK 50 % Note 37. Required to meet the following expression: “fBCLK ≥ 2 x fs x (Input/Output Data Length)”
[AK4601] 016000391-E-01 - 30 - 2016/12 3. Serial Data Interface (SDINx, SDOUTx) DVSS2=0V; CL=20pF) Parameter Symbol Min. Typ. Max. Unit Slave Mode Delay Time from BICK “↑” to LRCK (Note 39) tBLRD 10 ns Delay Time from LRCK to BICK “↑” (Note 39) tLRBD 10 ns Serial Data Input Latch Setup Time tBSIDS 10 ns Serial Data Input Latch Hold Time tBSIDH 5 ns Delay Time from BICK“↓”to Serial Data Output (Note 40) tBSOD1 20 ns Delay Time from BICK “↑”to Serial Data Output (Note 39, Note 41) tBSOD2 5 30 ns Master Mode BICK Frequency fBCLK 32, 48, 64, 128, 256, 512 fs BICK Duty Cycle Duty 50 % Delay Time from BICK “↓” to LRCK (Note 40) tMBL -10 10 ns Serial Data Input Latch Setup Time tBSIDS 10 ns Serial Data Input Latch Hold Time tBSIDH 10 ns Delay Time from BICK“↓”to Serial Data Output (Note 40, Note 41) tBSOD 10 ns Note 39. It is measured from BICK “↓” when the BICK polarity is inverted by setting BCKPx bit = “1”. Note 40. It is measured from BICK “↑” when the BICK polarity is inverted by setting BCKPx bit = “1”. Note 41. Set SDOPHx bit to “1” and the data from SDOUTx pin should be output based on BICK “↑” when BICKx speed is more than 12.288MHz such as TDM512 mode with 48kHz sampling frequency, TDM256 mode with 96kHz sampling frequency or TDM128 mode with 192kHz sampling frequency in slave mode. SDOPHx bit must be set to “0” in master mode.
Figure 12. I2C BUS Interface Timing
000 MCKI pin (default)
001 BICK1 pin
010 BICK2 pin
Table 4. PLL Reference Clock Frequency Setting Table 5. Reference Clock Frequency Setting 122.88MHz/112.896MHz master clock (PLL_MCLK) for internal operation (Table 6). Table 6. Internal Operation Master Clock
data of the AK4601 must be synchronized with one of these two Clock Sync Domains. When MSNx bit =“0”, input pins (LRCKx pin/BICKx pin) are selected for the clock sync reference clock.
0 Input Pin (LRCKx pin/BICKx pin)
CKSx[2:0], BDVx[8:0] and SDVx[2:0] bits settings. Table 7. Reference Clock of Clock Sync Domain Figure 14. Clock Sync Domain
generated by dividing the selected clock source according to the BDVx[8:0] bits setting (Table 9). Additionally, MLRCKx is generated by dividing this MBICKx by setting SDVx[2:0] bits (Table 8).
000 TieLow (default)
001 PLL MCLK
010 MCKI
011 BICK1
100 BICK2
Table 8. Clock Source of Internal Dividing Clock
101 N/A
110 N/A
Table 10. MLRCKx Setting (N/A: Not available) Clock Sync Domain settings when PLL MCLK is selected as the clock source are shown in Table 11.
Table 11. Clock Sync Domain Setting when PLL MCLK is Clock Source when the MCKI or BICK pin input is selected as the clock source, as well as the PLL MCLK.
The ADC, DAC blocks of the AK4601 are operated by a master clock generated by dividing PLL MCLK. CODEC) are set by FSMODE[4:0] bits (Table 12). Table 12. Sampling Frequency Settings of Internal Blocks (fs=48kHz base) the sampling frequency of the CODEC should also be the same.
e.g.) Input pin is selected for PLL Reference Clock.
- PLL Setting REFSEL[2:0] bits = “010” (PLL Reference Clock is set to BICK2 pin=3.072MHz)
- Clock Sync Domain Setting SDADC1[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “0”, BICK_SD1 = BICK1 pin = 64fs (0.512MHz), LRCK_SD1 = LRCK1 pin = 8kHz BICK_SD2 = BICK2 pin = 64fs (3.072MHz),LRCK_SD2 = LRCK2 pin = 48kHz
- ADC1 and CODEC Setting FSMODE[4:0] bits=” 01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz) PLL_MCLK=122.88MHz MSN1=”0” LRCK_SD1(fs=8kHz) BICK_SD1(64fs) Internal Dividing Clock BICK1 pin(64fs) LRCK1 pin(fs=8kHz) SDOUT1～ ADC2,M ADC2,M DAC1-3 SDOUT1～ DAC1-3 PLL Divide DATA BUS MSN2=”0” LRCK_SD2(fs=48kHz) BICK_SD2(64fs) BICK2 pin(64fs) LRCK2 pin(fs=48kHz) MLRCK1 MBICK1 Internal Dividing Clock MLRCK2 MBICK2 SDOUT1～ ADC1 ADC1 DATA BUS Divide fs=48kHz fs=8kHz FSMODE1[4:0] bits=”01010” fs=8kHz FSMODE[4:0] bits=”01010” fs=48kHz BICK2 pin=3.072MHz
Figure 15. ADC, DAC Setting Example (MSNx bit = “0”: Input pin is selected as PLL Reference Clock) Note 42. BICK1/LRCK1 and BICK2/LRCK2 must be synchronized.
- PLL Setting REFSEL[2:0] bits = “000” (PLL Reference Clock is MCKI pin = 3.072MHz), PLL MCLK = 122.88MHz
- Clock Sync Domain Setting SDADC[2:0] bits = “001”, SDCODEC[2:0] bits = “002”, MSN1 bit = MSN2 bit = “1”, CKS1[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 1) BDV1[8:0] = “0x0EF” (BICK SD1 = MBICK1 = 122.88MHz/240 = 0.512MHz) SDV1[2:0] = “000” (LRCK SD1 = MLRCK1 = 0.512MHz/64 = 8kHz) CKS2[2:0] = “001” (PLL MCLK is set as the reference clock of Clock Sync Domain 2) BDV2[8:0] = “0x027” (BICK SD2 = MBICK2 = 122.88MHz/40 = 3.072MHz) SDV2[2:0] = “000” (LRCK SD2 = MLRCK2 = 3.072MHz/64 = 48kHz)
- ADC1 and CODEC Setting FSMODE[4:0] bits= “01010” (Set fs = 8kHz for ADC1, Set CODEC, fs = 48kHz) MSN1=”1” LRCK_SD1(fs=8kHz) BICK_SD1(64fs) Internal Dividing Clock BICK1 pin(64fs) LRCK1 pin(fs=8kHz) ADC2,M DAC1-3 SDOUT1～ DAC1-3 PLL Divide DATA BUS MSN2=”1” LRCK_SD2(fs=48kHz) BICK_SD2(64fs) BICK2 pin(64fs) LRCK2 pin(fs=48kHz) MLRCK1(fs=8kHz) MBICK1(64fs) ADC1 DATA BUS Divide fs=48kHz fs=8kHz FSMODE[4:0] bits=”01010” fs=8kHz Internal Dividing Clock MLRCK2(fs=48kHz) MBICK2(64fs) FSMODE[4:0] bits=”01010” fs=48kHz PLL_MCLK=122.88MHz MCKI pin=3.072MHz SDOUT1～ ADC2,M SDOUT1～ ADC1
Figure 16. ADC, DAC, Setting Example
CLKO pin is controlled by CLKOSEL[2:0] bits (Table 13). Table 13. CLKO Pin Setting LRCK2/SDOUT3 pin works as the SDOUT3 pin.
0 BICK2 (default)
1 SDIN3
Table 14. BICK2/SDIN3 Pin Setting 1 The AK4601 has three SDIN pins and two BICK/LRCK pins. They are independent each other.
001 BICK1 pin, LRCK1 pin
010 BICK2 pin, LRCK2 pin
Table 15. BICKx/LRCKx pin Setting for Synchronization to SDINx pin
0 Slave Mode (Input) (default)
1 Master Mode (Output)
Table 16. BICKx pin/LRCKx pin Mode Select
Note 43. Set MSNx bit to “0” when using the BICKx pin as PLL reference clock input pin. the LRCK2/SDOUT3 pin works as SDOUT3 (Output) even setting MSN2 bit to “0”. Table 17. BICK2/SDIN3 Pin Setting 2 Table 18. Clock Sync Domain Setting of BICKx/LRCKx Pin
frequency of these clocks are synchronized. However, frequencies of BICK SDx can be different. sampling frequencies or different reference clocks. Figure 17. Data Path, Input/Output Port
Figure 20. Clock Sync Domain Setting of Input/Output Port
- Source Address, Source Selecting Registers
selected SDOUTx pins (Table 21). Table 20. Clock Sync Domain Setting for Source Address and Input Port MSNx bit and SDBCKx[2:0] bits (Table 15, Table 16, Table 18).
obtaining data from the data bus. necessary since an audio data port inherits the sync domain of the input data. Table 21. Clock Sync Domain Settings for Source Select Registers and Output Port
- Input/Output Serial Interface Format
The AK4601 has two independent BICK/LRCK pins that are able to switch master and slave mode. mode, set DCFx[2:0] bits according to the input clock format. Table 22. AK4601 Data Clock Format Clock edge relationship can be controlled by BCKPx bit.
0 Falling Edeg (FE) (default)
1 Rising Edge (RE)
Table 23. Clock Edge Relationship between BICKx and LRCKx
DOEDGENx, DOLSBEx and DODLx[1:0] bits settings (x=1~3). DISLx[1:0] bits / DOSLx[1:0] bits (x=1~3) control input/output data slot length. Table 24. Slot Length Setting of Input/Output Data DIDLx[1:0] bits / DODLx[1:0] bits (x=1~3) control input/output audio data word length. Table 25. Word Length Setting of Input/Output Audio Data DILSBEx bit/ DOLSBEx bit (x=1~3) selects the audio data format of a slot.
0 MSB First (default)
1 LSB First
Table 26. Slot Data Format Setting
0 LRCK Edge Basis (default)
1 Slot Length Basis
Table 27. Data Transmission Start Timing of The Data After Second Channel immediately without waiting a LRCK edge after transmitted one slot data (Figure 29 ~ Figure 32). until a LRCK edge even finished transmitting one slot data (Figure 26 ~ Figure 28).
when DIEDGENx bit = “1”. BICK clock is supported up to 24.576MHz. word length of the SDINx pin. The slot data format is set by DILSBEx bit. are LRCK edge basis. DISLx[1:0] bits setting are ignored when DIEDGENx bit = “0”. SDOUTx pin. The slot data format is set by DOLSBEx bit. are LRCK edge basis. DOSLx[1:0] bits setting are ignored when DIEDGENx bit = “0”. Setting example of stereo mode is shown in Table 28.
0 I2S Compatible 000 0 0 x Word Length
1 MSB Justified 101 0 0 x Word Length
2 LSB Justified 101 1 0 x Word Length
3 PCM Short Frame 110 0 1 Slot Length Word Length
4 PCM Long Frame 111 0 1 Slot Length Word Length
5 Irregular I2S 000 0 1 Slot Length Word Length
Table 28. Input/Output Data Format Setting Example (x: Do Not Care) Figure 26. I²S Compatible Format
512fs when using TDM mode. Up to 192kHz in 128fs mode (max. fs=128kHz in 192 mode, max. fs=96kHz in 256 mode, max. fs=48kHz in 512 mode) sampling frequency is supported. maximum. A source address is assigned to each 2 slot of SDIN1 input pin when using TDM mode. input data word length of the SDIN1 pin. The slot data format is set by DILSBE1 bit. Setting example of TDM mode is shown in Table 29.
0 I2S Compatible 000 0 1 11 (32bit) Word Length
1 MSB Justified 101 0 1 11 (32bit) Word Length
2 LSB Justified 101 1 1 11 (32bit) Word Length
Table 29. TDM Mode Setting Example
32 BICK
Figure 34. TDM Mode I2S Compatible (BICK = 512fs)
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 35. TDM Mode I2S Compatible (BICK = 256fs)
32 BICK 32 BICK 32 BICK 32 BICK
Figure 36. TDM Mode I2S Compatible (BICK = 128fs)
Figure 37. TDM Mode MSB Justified Format (BICK = 512fs) Figure 38. TDM Mode MSB Justified Format (BICK = 256fs) Figure 39. TDM Mode MSB Justified Format (BICK = 128fs)
Figure 40. TDM Mode LSB Justified Format (BICK = 512fs) Figure 41. TDM Mode LSB Justified Format (BICK = 256fs) Figure 42. TDM Mode LSB Justified Format (BICK = 128fs)
made with an interval of 1ms or more after the PDN pin = “H”. before a clock reset release. The system clock must not be stopped except during clock reset and power-down mode (PDN pin = “L”). Figure 52. Power-up Sequence 100 msec if the capacitance is 1 µF. capacitor at the MPREF pin. It will be 100 msec if the capacitance is 1 µF.
and control register settings can be made 1ms after the power-down release (PDN pin=“H”). reset by the PDN pin after removing the problems.
- AK4601 Power-down and Reset Statuses and Power Management
CKRESETN bit (Clock Reset) and power management bits for each block. the ADC, DAC, blocks are not in operation because the PLL circuit and internal clocks are stopped. Table 30. Reset State Definitions of the AK4601 (x: Don’t Care) Note 49. A stable clock should be supplied before releasing clock reset (CKRESETN bit = “1”). or longer after setting the PDN pin = “H”.
power-save mode. Even the internal PLL for master clock generation is powered down. the blocks by setting each power-management bit. PLL starts operation by setting CKRESETN bit to “1”. stabilization of PLL after clock reset is released. Figure 53. Clock Mode Switching Sequence
PLL lock signal can be read out from the STO bit when PLLLOCKE bit = “1”.
0 No Error Detected: 1 (default)
1 No Error Detected: 1
Table 31. STO Bit Status Input “0xDE → 0xADDA → 0x7A” to the SI/I2CFIL pin while the CSN pin is “L” for the dummy command. The data is in MSB first format. Figure 54. Dummy Command Write Sequence Table 32. μP Interface Setting Note 50. The CSN pin and the SI/I2CFIL pin should be fixed to “L” or “H” when using I2C interface mode.
Mixer A is controlled by SFTA1[1:0] bits, SFTA2[1:0] bits, SWPA1[1:0] bits and SWPA2[1:0] bits. Mixer B is controlled by SFTB1[1:0] bits, SFTB2[1:0] bits, SWPB1[1:0] bits and SWPB2[1:0] bits. Figure 65. Block Diagram of the Mixer Table 34. Level Adjustment of the Mixer Table 35. Data Change Function of the Mixer
Table 36. Digital Volume Settings ATSPVOL bit controls transition time between setting values of the volume. Table 37. Volume Transition Time during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 18H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, each channel of volume circuit is initialized to 18H. Table 38. Volume Transition Time between 00h and FFh
Table 39. Digital Volume Level Setting of the VOL Circuit
independently selected by MGNL[3:0] and MGNR[3:0] bits (Table 40). The input impedance is typ. When writing to MGNL/R[3:0] bits continuously, take an interval of zero crossing timeout period or more. continuously is possible with a shorter interval of the zero crossing timeout period. Table 40. Microphone Input Gain Table 41. Zero Crossing Timeout Period noise may occur just after the ADC is powered up if this wait time is not enough.
- Microphone Input Selector
single-ended input and differential input by AD1LSEL bit or AD1RSEL bit. Figure 66. Microphone Input Selector
0 INP1/INN1 (default) 0 INP2/INN2 (default)
1 AIN1L 1 AIN1R
Table 42. Microphone Input Selector from the MPWR1 pin and the MPWR2 pin by setting PMMB1 bit = “1” and PMMB2 bit = “1”, respectively. The output voltage is 2.5V (AVDD=3.3V) and the load resistance is min. 2kΩ.
0 Hi-Z (default) 0 Hi-Z (default)
1 Output 1 Output
Table 43. Microphone Bias Output Figure 67. MIC Block Circuit (Differential Input) Figure 68. MIC Block Circuit (Single-end Input)
- ADC Block High Pass Filter
frequency of the HPF is about 0.93Hz (fs=48kHz), depending on operation frequency. Table 44. HPF Cut-off Frequency Table 45. ADC Digital Volume Control Setting The transition time between set values is selected by ATSPAD bit. Table 46. ADC Volume Level Transition Time during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, each channel of the ADC is initialized to 30H. Table 47. ADC Volume Transition Time between 00h and FFh
Table 48. ADC Digital Volume Level Setting
The ADC block has a digital soft mute circuit. The soft mute operation is performed at digital domain. mute is effective for changing the signal source without stopping the signal transmission. available when each ADC is in operation. The attenuation value is initialized by setting the PDN pin = “L”. Figure 69. ADC Soft Mute and 1 stereo semi-differential input. Differential or single-ended input can be selected for the ADCM. changed during operation, mute output signal to reduce switching noise as needed. Table 49. ADC2 Input Select Table 50. ADCM Input Select
Figure 70. ADC2 Input Channel Switching Sequence Example level from 0dB to - is shown below. releasing the soft mute after changing the channel (period (3)).
- ADC Digital Filter Select
The AK4601 has four kinds of digital filters in ADC block. ADSD and ADSL bits select a digital filter. Table 51. ADC Digital Filter Select ADCMV bit, respectively (Table 52). Table 52. ADC Input Voltage
Table 53. DAC Digital Volume Setting Transition time between set values can be selected by ATSPDA bit. Table 54. DAC Volume Transition Time Setting during these transitions. In Mode 0, it takes 1020/fs (21.3ms@fs=48kHz) from 00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, each channel of the DAC is initialized to 18H. Table 55. DAC Volume Transition Time between 00h and FFh
Table 56. DAC Digital Volume Level Setting The DAC block has a digital soft mute circuit. The soft mute operation is performed at digital domain. mute is effective for changing the signal source without stopping the signal transmission. available when each DAC is in operation. The attenuation value is initialized by setting the PDN pin = “L”.
Table 58. De-emphasis Filter Control set to the default setting “01” when the AK4601 is operated with other sampling frequencies.
- In the case that the AK4601 is operated with a sampling frequency other than shown in Table 58. The frequency characteristics of the de-emphasis filter will track the sampling frequency of the actual operation. (e.g. The cut-off frequency exists around 1kHz in 48kHz mode, around 2kHz in 96kHz mode and around 0.5kHz in 24kHz mode.)
[AK4601] 016000391-E-01 - 86 - 2016/12 ■ Register Map Control registers can be initialized by a power-down release (PDN pin = “L” → “H”). Do not write to registers in the address after 008CH and write "0" into 0 bits and write "1" into 1 bit. Normal Registers Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default
0000 System Clock Setting 1 REFSEL[2:0] REFMODE[4:0] 00
0001 System Clock Setting 2 CKRESETN 0 0 FSMODE[4:0] 00
0002 Mic Bias Power Management PSW1N PSW2N 0 0 0 0 PMMB1 PMMB2 00
0003 Sync Domain 1 Setting 1 MSN1 CKS1[2:0] BDV1[8] SDV1[2:0] 00
0004 Sync Domain 1 Setting 2 BDV1[7:0] 00
0005 Sync Domain 2 Setting 1 MSN2 CKS2[2:0] BDV2[8] SDV2[2:0] 00
0006 Sync Domain 2 Setting 2 BDV2[7:0] 00
0007 Reserved 0 00
0008 Reserved 0 00
0009 Reserved 0 00
000F CLKO Output Setting 0 0 0 0 CLKOE CLKOSEL[2:0] 00
0010 Pin Setting 0 0 0 0 0 0 0 MSELN 00
0011 Sync Domain Select 1 0 SDBCK1[2:0] 0 SDBCK2[2:0] 00
0012 Reserved 0 00
0013 Sync Domain Select 3 0 0 0 0 0 EXBCK1[2:0] 00
0014 Sync Domain Select 4 0 EXBCK2[2:0] 0 EXBCK3[2:0] 00
0015 Reserved 0 00
0016 Sync Domain Select 6 0 SDDO1[2:0] 0 SDDO2[2:0] 00
0017 Sync Domain Select 7 0 SDDO3[2:0] 0 0 0 0 00
0018 Sync Domain Select 8 0 0 0 0 0 SDVOL1[2:0] 00
0019 Sync Domain Select 9 0 SDVOL2[2:0] 0 SDVOL3[2:0] 00
001F Sync Domain Select 15 0 SDMIXA[2:0] 0 SDMIXB[2:0] 00
0020 Sync Domain Select 16 0 SDADC1[2:0] 0 SDCODEC[2:0] 00
0021 SDOUT1 TDM SLOT1-2 Data Select 0 0 SELDO1A[5:0] 00
0022 SDOUT1 TDM SLOT3-4 Data Select 0 0 SELDO1B[5:0] 00
0023 SDOUT1 TDM SLOT5-6 Data Select 0 0 SELDO1C[5:0] 00
0024 SDOUT1 TDM SLOT7-8 Data Select 0 0 SELDO1D[5:0] 00
0025 SDOUT1 TDM SLOT9-10 Data Select 0 0 SELDO1E[5:0] 00
0026 SDOUT1 TDM SLOT11-12 Data Select 0 0 SELDO1F[5:0] 00
0027 SDOUT1 TDM SLOT13-14 Data Select 0 0 SELDO1G[5:0] 00
0028 SDOUT1 TDM SLOT15-16 Data Select 0 0 SELDO1H[5:0] 00
0029 SDOUT2 Output Data Select 0 0 SELDO2[5:0] 00
002A SDOUT3 Output Data Select 0 0 SELDO3[5:0] 00 002B Reserved 0 00 002C Reserved 0 00 002D Reserved 0 00 002E Reserved 0 00 002F Reserved 0 00
0030 Reserved 0 00
0031 Reserved 0 00
[AK4601] 016000391-E-01 - 87 - 2016/12 Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default
0032 Reserved 0 00
0033 Reserved 0 00
0034 Reserved 0 00
0035 DAC1 Input Data Select 0 0 SELDA1[5:0] 00
0036 DAC2 Input Data Select 0 0 SELDA2[5:0] 00
0037 DAC3 Input Data Select 0 0 SELDA3[5:0] 00
0038 VOL1 Input Data Select 0 0 SELVOL1[5:0] 00
0039 VOL2 Input Data Select 0 0 SELVOL2[5:0] 00
003A VOL3 Input Data Select 0 0 SELVOL3[5:0] 00 003B Reserved 0 00 003C Reserved 0 00 003D Reserved 0 00 003E Reserved 0 00 003F Reserved 0 00
0040 Reserved 0 00
0041 Reserved 0 00
0042 Reserved 0 00
0043 Reserved 0 00
0044 Reserved 0 00
0045 Mixer A Ch1 Input Data Select 0 0 SELMIXAI1[5:0] 00
0046 Mixer A Ch2 Input Data Select 0 0 SELMIXAI2[5:0] 00
0047 Mixer B Ch1 Input Data Select 0 0 SELMIXBI1[5:0] 00
0048 Mixer B Ch2 Input Data Select 0 0 SELMIXBI2[5:0] 00
0049 Reserved 0 00
004C Clock Format Setting 1 BCKP1 DCF1[2:0] BCKP2 DCF2[2:0] 00 004D Reserved 0 00 004E Reserved 0 00 004F Reserved 0 00
0050 SDIN1 Digital Input Format DIEDGEN1 0 DISL1[1:0] DILSBE1 0 DIDL1[1:0] 00
0051 SDIN2 Digital Input Format DIEDGEN2 0 DISL2[1:0] DILSBE2 0 DIDL2[1:0] 00
0052 SDIN3 Digital Input Format DIEDGEN3 0 DISL3[1:0] DILSBE3 0 DIDL3[1:0] 00
0053 Reserved 0 00
0054 Reserved 0 00
0055 SDOUT1 Digital Output Format DOEDGEN1 0 DOSL1[1:0] DOLSBE1 0 DODL1[1:0] 00
0056 SDOUT2 Digital Output Format DOEDGEN2 0 DOSL2[1:0] DOLSBE2 0 DODL2[1:0] 00
0057 SDOUT3 Digital Output Format DOEDGEN3 0 DOSL3[1:0] DOLSBE3 0 DODL3[1:0] 00
0058 Reserved 0 00
0059 Reserved 0 00
005A SDOUT Phase Setting 0 0 0 0 0 SDOPH3 SDOPH2 SDOPH1 00 005B Reserved 0 00 005C Reserved 0 00 005D Reserved 0 00 005E Output Port Enable Setting 0 0 SDOUT1E SDOUT2E SDOUT3E 0 0 0 00 005F Reserved 0 00
0060 Mixer A Setting SFTA2[1:0] SFTA1[1:0] SWPA2[1:0] SWPA1[1:0] 00
0061 Mixer B Setting SFTB2[1:0] SFTB1[1:0] SWPB2[1:0] SWPB1[1:0] 00
0062 MIC AMP Gain MGNL[3:0] MGNR[3:0] 00
0063 Analog Input Gain Control ADC1VL ADC1VR ADC2VL ADC2VR ADCMV 0 MICLZCE MICRZCE 00
0064 ADC1 Lch Digital Volume VOLAD1L[7:0] 30
0065 ADC1 Rch Digital Volume VOLAD1R[7:0] 30
0066 ADC2 Lch Digital Volume VOLAD2L[7:0] 30
0067 ADC2 Rch Digital Volume VOLAD2R[7:0] 30
0068 ADCM Digital Volume VOLADM[7:0] 30
0069 Reserved 0 00
[AK4601] 016000391-E-01 - 88 - 2016/12 Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default 006B Analog Input Select Setting ADSD ADSL 0 ADMSEL AD1LSEL AD1RSEL AD2SEL[1:0] 00 006C ADC Mute & HPF Control ATSPAD AD1MUTE AD2MUTE ADMMUTE 0 AD1HPFN AD2HPFN ADMHPFN 00 006D DAC1 Lch Digital Volume VOLDA1L[7:0] 18 006E DAC1 Rch Digital Volume VOLDA1R[7:0] 18 006F DAC2 Lch Digital Volume VOLDA2L[7:0] 18
0070 DAC2 Rch Digital Volume VOLDA2R[7:0] 18
0071 DAC3 Lch Digital Volume VOLDA3L[7:0] 18
0072 DAC3 Rch Digital Volume VOLDA3R[7:0] 18
0073 DAC Mute & Filter Setting ATSPDA DA1MUTE DA2MUTE DA3MUTE 0 DSMN DASD DASL 02
0074 DAC DEM Setting 0 0 DEM3[1:0] DEM2[1:0] DEM1[1:0] 15
0075 VOL1 Lch Digital Volume VOL1L[7:0] 18
0076 VOL1 Rch Digital Volume VOL1R[7:0] 18
0077 VOL2 Lch Digital Volume VOL2L[7:0] 18
0078 VOL2 Rch Digital Volume VOL2R[7:0] 18
0079 VOL3 Lch Digital Volume VOL3L[7:0] 18
007A VOL3 Rch Digital Volume VOL3R[7:0] 18 007B Reserved 0 0 0 1 1 0 0 0 18 007C Reserved 0 0 0 1 1 0 0 0 18 007D Reserved 0 0 0 1 1 0 0 0 18 007E Reserved 0 0 0 1 1 0 0 0 18 007F VOL Setting ATSPVOL 0 0 0 0 0 0 0 00
0080 Reserved 0 00
0081 Reserved 0 00
0082 Reserved 0 00
0083 STO Flag Setting 1 0 PLLLOCKE 0 0 0 0 0 0 00
0084 Reserved 0 00
0085 Reserved 0 00
0086 Reserved 0 0 0 0 0 1 0 0 04
0087 Reserved 0 0 0 0 0 0 1 0 02
0088 Reserved 0 00
0089 Reserved 0 00
008A Power Management 1 0 0 PMAD1 PMAD2 PMADM PMDA1 PMDA2 PMDA3 00 008B Reserved 0 00 008C Reset Control 0 0 1 CRESETN 0 0 0 HRESETN 20 Read Only Registers Read these registers after Clock reset is released (when PLL is stabilized). Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0 Default
0100 Reserved 0 00
0101 Reserved 0 00
0102 Status Read Out 0 STO 0 0 0 0 0 0 40
[AK4601] 016000391-E-01 - 89 - 2016/12 ■ Register Definitions Normal Registers Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0000 System Clock Setting 1 REFSEL[2:0] REFMODE[4:0]
REFSEL[3:0]: PLL Reference Clock Input Pin Setting (Table 4) Default: “000” (MCKI) REFMODE[4:0]: PLL Reference Clock Frequency Setting (Table 5) Default: 00H (256kHz) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0001 System Clock Setting 2 CKRESETN 0 FSMODE[4:0]
CKRESETN: Clock Reset 0: Clock Reset (default) 1: Clock Reset Release FSMODE[4:0]: Operation Sampling Frequency Mode Setting for each Block (Table 12) Default: 00H (8kHz) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0002 Mic Bias Power Management PSW1N PSW2N 0 PMMB1 PMMB2
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PSW1N: Pull-down Setting for BICK1pin / LRCK1 pin (Table 2) 0: Pulled Down (46kΩ) (default) 1: Release PSW2N: Pull-down Setting for BICK2 pin/ LRCK2 pin (Table 2) 0: Pulled Down (46kΩ) (default) 1: Release PMMB1: Power Management Setting for MIC Bias Output 1 0: Power Save Mode (default) 1: Normal Operation PMMB2: Power Management Setting for MIC Bias Output 2 0: Power Save Mode (default) 1: Normal Operation
[AK4601] 016000391-E-01 - 90 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0003 Sync Domain 1 Setting 1 MSN1 CKS1[2:0] BDV1[8] SDV1[2:0]
0004 Sync Domain 1 Setting 2 BDV1[7:0]
MSN1: Slave/Master Mode Setting for BICK1 pin/LRCK1 pin (Table 16) 0: Slave Mode (default) 1: Master Mode CKS1[2:0]: MBICK1 Divider Reference Clock Setting of Clock Sync Domain 1 (Table 8) Default: “000” (TieLow) BDV1[8:0]: MBICK1 Divider Setting (Table 9) Default: 000H (Divided by 1) SDV1[2:0]: MLRCK1 Divider Setting (Table 10) Default: “000” (Divided by 64) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0005 Sync Domain 2 Setting 1 MSN2 CKS2[2:0] BDV2[8] SDV2[2:0]
0006 Sync Domain 2 Setting 2 BDV2[7:0]
MSN2: Slave/Master Mode Setting for BICK2 pin/LRCK2 pin (Table 16) 0: Slave Mode (default) 1: Master Mode CKS2[2:0]: MBICK2 Divider Reference Clock Setting of Clock Sync Domain 2 (Table 8) Default: “000” (TieLow) BDV2[8:0]: MBICK2 Divider Setting (Table 9) Default: 000H (Divided by 1) SDV2[2:0]: MLRCK2 Divider Setting (Table 10) Default: “000” (Divided by 64) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 000F CLKO Output Setting 0 CLKOE CLKOSEL[2:0] R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 000 CLKOE: CLKO pin Output Enable 0: CLKO pin = “L” (default) 1: CLKO Output Enable CLKOSEL[2:0]: CLKO pin Output Clock Frequency Setting (Table 13) Default: “000” (12.288MHz / 11.2896MHz)
[AK4601] 016000391-E-01 - 91 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0010 Pin Setting 0 MSELN
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 MSELN: BICK2/SDIN3 pin and LRCK2/SDOUT3 pin setting 0: BICK2 pin, LRCK2 pin (default) 1: SDIN3 pin, SDOUT3 pin Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0011 Sync Domain Select 1 0 SDBCK1[2:0] 0 SDBCK2[2:0]
0013 Sync Domain Select 3 0 EXBCK1[2:0]
0014 Sync Domain Select 4 0 EXBCK2[2:0] 0 EXBCK3[2:0]
0016 Sync Domain Select 6 0 SDDO1[2:0] 0 SDDO2[2:0]
0017 Sync Domain Select 7 0 SDDO3[2:0] 0
0018 Sync Domain Select 8 0 SDVOL1[2:0]
0019 Sync Domain Select 9 0 SDVOL2[2:0] 0 SDVOL3[2:0]
001F Sync Domain Select 15 0 SDMIXA[2:0] 0 SDMIXB[2:0]
0020 Sync Domain Select 16 0 SDADC1[2:0] 0 SDCODEC[2:0]
SDxxxx[2:0]: Clock Sync Domain Setting for Input/Output Port (Table 20, Table 21) Default: “000” (Not Assigned) EXBCKx[2:0]: SDINx pin Symchronizing Clock Select (Table 15) Default: “000” (Not Assigned)
[AK4601] 016000391-E-01 - 92 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0021 SDOUT1 TDM SLOT1-2 Data Select 0 SELDO1A[5:0]
0022 SDOUT1 TDM SLOT3-4 Data Select 0 SELDO1B[5:0]
0023 SDOUT1 TDM SLOT5-6 Data Select 0 SELDO1C[5:0]
0024 SDOUT1 TDM SLOT7-8 Data Select 0 SELDO1D[5:0]
0025 SDOUT1 TDM SLOT9-10 Data Select 0 SELDO1E[5:0]
0026 SDOUT1 TDM SLOT11-12 Data Select 0 SELDO1F[5:0]
0027 SDOUT1 TDM SLOT13-14 Data Select 0 SELDO1G[5:0]
0028 SDOUT1 TDM SLOT15-16 Data Select 0 SELDO1H[5:0]
0029 SDOUT2 Output Data Select 0 SELDO2[5:0]
002A SDOUT3 Output Data Select 0 SELDO3[5:0]
0035 DAC1 Input Data Select 0 SELDA1[5:0]
0036 DAC2 Input Data Select 0 SELDA2[5:0]
0037 DAC3 Input Data Select 0 SELDA3[5:0]
0038 VOL1 Input Data Select 0 SELVOL1[5:0]
0039 VOL2 Input Data Select 0 SELVOL2[5:0]
003A VOL3 Input Data Select 0 SELVOL3[5:0]
0045 Mixer A Ch1 Input Data Select 0 SELMIXAI1[5:0]
0046 Mixer A Ch2 Input Data Select 0 SELMIXAI2[5:0]
0047 Mixer B Ch1 Input Data Select 0 SELMIXBI1[5:0]
0048 Mixer B Ch2 Input Data Select 0 SELMIXBI2[5:0]
SELxxx[5:0]: Data Source Select of Output Port (Table 21) Default: 00H (ALL0)
[AK4601] 016000391-E-01 - 93 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 004C Clock Format Setting 1 BCKP1 DCF1[2:0] BCKP2 DCF2[2:0] R/W R/W R/W R/W R/W Default 0 000 0 000 BCKP1: Relationship of LRCK1 and BICK1 Edges (Table 23) 0: LRCK1 starts on a BICK1 falling edge (default) 1: LRCK1 starts on a BICK1 rising edge DCF1[2:0]: LRCK1/BICK1 Clock Format Setting (Table 22) Default: “000” (I2S Mode) BCKP2: Relationship of LRCK2 and BICK2 Edges (Table 23) 0: LRCK2 starts on a BICK2 falling edge (default) 1: LRCK2 starts on a BICK2 rising edge DCF2[2:0]: LRCK2/BICK2 Clock Format Setting (Table 22) Default: “000” (I2S Mode) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0050 SDIN1 Digital Input Format DIEDGEN1 0 DISL1[1:0] DILSBE1 0 DIDL1[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DIEDGEN1: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN1 0: LRCK Edge Basis (default) 1: Slot Length Basis DISL1[1:0]: SDIN1 Data Slot Length Setting (Table 24) Default: “00” (24bit) DILSBE1: MSB/LSB Setting of Audio Data in Data Slot of SDIN1 0: MSB (default) 1: LSB DIDL1[1:0]: Audio Data Word Length Setting of SDIN1 (Table 25) Default: “00” (24bit) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0051 SDIN2 Digital Input Format DIEDGEN2 0 DISL2[1:0] DILSBE2 0 DIDL2[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DIEDGEN2: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN2 0: LRCK Edge Basis (default) 1: Slot Length Basis DISL2[1:0]: SDIN2 Data Slot Length Setting (Table 24) Default: “00” (24bit) DILSBE2: MSB/LSB Setting of Audio Data in Data Slot of SDIN2 0: MSB (default) 1: LSB DIDL2[1:0]: Audio Data Word Length Setting of SDIN2 (Table 25) Default: “00” (24bit)
[AK4601] 016000391-E-01 - 94 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0052 SDIN3 Digital Input Format DIEDGEN3 0 DISL3[1:0] DILSBE3 0 DIDL3[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DIEDGEN3: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDIN3 0: LRCK Edge Basis (default) 1: Slot Length Basis DISL3[1:0]: SDIN3 Data Slot Length Setting (Table 24) Default: “00” (24bit) DILSBE3: MSB/LSB Setting of Audio Data in Data Slot of SDIN3 0: MSB (default) 1: LSB DIDL3[1:0]: Audio Data Word Length Setting of SDIN3 (Table 25) Default: “00” (24bit) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0055 SDOUT1 Digital Output Format DOEDGEN1 0 DOSL1[1:0] DOLSBE1 0 DODL1[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DOEDGEN1: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT1 0: LRCK Edge Basis (default) 1: Slot Length Basis DOSL1[1:0]: SDOUT1 Data Slot Length Setting (Table 24) Default: “00” (24bit) DOLSBE1: MSB/LSB Setting of Audio Data in Data Slot of SDOUT1 0: MSB (default) 1: LSB DODL1[1:0]: Audio Data Word Length Setting of SDOUT1 (Table 25) Default: “00” (24bit) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0056 SDOUT2 Digital Output Format DOEDGEN2 0 DOSL2[1:0] DOLSBE2 0 DODL2[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DOEDGEN2: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT2 0: LRCK Edge Basis (default) 1: Slot Length Basis DOSL2[1:0]: SDOUT2 Data Slot Length Setting (Table 24) Default: “00” (24bit) DOLSBE2: MSB/LSB Setting of Audio Data in Data Slot of SDOUT2 0: MSB (default) 1: LSB DODL2[1:0]: Audio Data Word Length Setting of SDOUT2 (Table 25) Default: “00” (24bit)
[AK4601] 016000391-E-01 - 95 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0057 SDOUT3 Digital Output Format DOEDGEN3 0 DOSL3[1:0] DOLSBE3 0 DODL3[1:0]
R/W R/W R/W R/W R/W R/W R/W Default 0 0 00 0 0 00 DOEDGEN3: Start Timing Setting of Data Transferring for Second and Succeeding Channels of SDOUT3 0: LRCK Edge Basis (default) 1: Slot Length Basis DOSL3[1:0]: SDOUT3 Data Slot Length Setting (Table 24) Default: “00” (24bit) DOLSBE3: MSB/LSB Setting of Audio Data in Data Slot of SDOUT3 0: MSB (default) 1: LSB DODL3[1:0]: Audio Data Word Length Setting of SDOUT3 (Table 25) Default: “00” (24bit) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 005A SDOUT Phase Setting 0 SDOPH3 SDOPH2 SDOPH1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SDOPH3: High speed mode setting for SDOUT3 in slave mode (Note 41) 0: Normal Mode (default) 1: High speed mode SDOPH2: High speed mode setting for SDOUT2 in slave mode (Note 41) 0: Normal Mode (default) 1: High speed mode SDOPH1: High speed mode setting for SDOUT1 in slave mode (Note 41) 0: Normal Mode (default) 1: High speed mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 005E Output Port Enable Setting 0 SDOUT1E SDOUT2E SDOUT3E 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SDOUT1E: SDOUT1 Output Enable 0: SDOUT1 pin = “L” (default) 1: SDOUT1 Output Enable SDOUT2E: SDOUT2 Output Enable 0: SDOUT2 pin = “L” (default) 1: SDOUT2 Output Enable SDOUT3E: SDOUT3 Output Enable 0: SDOUT3 pin = “L” (default) 1: SDOUT3 Output Enable
[AK4601] 016000391-E-01 - 96 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0060 Mixer A Setting SFTA2[1:0] SFTA1[1:0] SWPA2[1:0] SWPA1[1:0]
SFTA2[1:0]: Level Adjustment Function Setting for Input2 of Mixer A (Table 34) Default: “00” (Not Shifted) SFTA1[1:0]: Level Adjustment Function Setting for Input1 of Mixer A (Table 34) Default: “00” (Not Shifted) SWPA2[1:0]: Data Change Setting for Input 2 of Mixer A (Table 35) Default: “00” (Through) SWPA1[1:0]: Data Change Setting for Input 1 of Mixer A (Table 35) Default: “00” (Through) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0061 Mixer B Setting SFTB2[1:0] SFTB1[1:0] SWPB2[1:0] SWPB1[1:0]
SFTB2[1:0]: Level Adjustment Function Setting for Input2 of Mixer B (Table 34) Default: “00” (Not Shifted) SFTB1[1:0]: Level Adjustment Function Setting for Input1 of Mixer B (Table 34) Default: “00” (Not Shifted) SWPB2[1:0]: Data Change Setting for Input 2 of Mixer B (Table 35) Default: “00” (Through) SWPB1[1:0]: Data Change Setting for Input 1 of Mixer B (Table 35) Default: “00” (Through) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0062 MIC AMP Gain MGNL[3:0] MGNR[3:0]
MGNL[3:0]: MIC Input Lch Gain Setting (Table 40) Default: 0H (0dB) MGNR[3:0]: MIC Input Rch Gain Setting (Table 40) Default: 0H (0dB)
[AK4601] 016000391-E-01 - 97 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0063 Analog Input Gain Control ADC1VL ADC1VR ADC2VL ADC2VR ADCMV 0 MICLZCE MICRZCE
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ADC1VL: Lch Input Voltage Setting of ADC1 (Table 52) Default: “0”(2.3Vpp(±2.3Vpp)) ADC1VR: Rch Input Voltage Setting of ADC1 (Table 52) Default: “0”(2.3Vpp(±2.3Vpp)) ADC2VL: Lch Input Voltage Setting of ADC2 (Table 52) Default: “0”(2.3Vpp(±2.3Vpp)) ADC2VR: Rch Input Voltage Setting of ADC2 (Table 52) Default: “0”(2.3Vpp(±2.3Vpp)) ADCMV: Input Voltage Setting of ADCM (Table 52) Default: “0”(2.3Vpp(±2.3Vpp)) MICLZCE: MIC Gain Zero Crossing Enable for Lch 0: Lch Zero Crossing Detection is OFF (default) 1: Lch Zero Crossing Detection is ON MICRZCE: MIC Gain Zero Crossing Enable for Rch 0: Rch Zero Crossing Detection is OFF (default) 1: Rch Zero Crossing Detection is ON Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0064 ADC1 Lch Digital Volume VOLAD1L[7:0]
0065 ADC1 Rch Digital Volume VOLAD1R[7:0]
0066 ADC2 Lch Digital Volume VOLAD2L[7:0]
0067 ADC2 Rch Digital Volume VOLAD2R[7:0]
0068 ADCM Digital Volume VOLADM[7:0]
VOLAD1L[7:0]: Lch Digital Volume Setting of ADC1 (Table 45) Default: 30H (0dB) VOLAD1R[7:0]: Rch Digital Volume Setting of ADC1 (Table 45) Default: 30H (0dB) VOLAD2L[7:0]: Lch Digital Volume Setting of ADC2 (Table 45) Default: 30H (0dB) VOLAD2R[7:0]: Rch Digital Volume Setting of ADC2 (Table 45) Default: 30H (0dB) VOLADM[7:0]: Digital Volume Setting of ADCM (Table 45) Default: 30H (0dB)
[AK4601] 016000391-E-01 - 98 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 006B Analog Input Select Setting ADSD ADSL 0 ADMSEL AD1LSEL AD1RSEL AD2SEL[1:0] R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 00 ADSD, ADSL: ADC Digital Filter Select (Table 51) 00: Sharp Roll-Off Filter (default) 01: Slow Roll-Off Filter 10: Short Delay Sharp Roll-Off Filter 11: Short Delay Slow Roll-Off Filter ADMSEL: ADCM Input Pin Select (Table 50) 0: AINMP, AINMN (default) 1: AINMP AD1LSEL: ADC1 Lch Input Pin Select (Table 42) 0: INP1/INN1 (default) 1: AIN1L AD1RSEL: ADC1 Rch Input Pin Select (Table 42) 0: INP2/INN2 (default) 1: AIN1R AD2SEL[1:0]: ADC2 Input Pin Select (Table 49) Default: “00” (AIN2LP, AIN2LN, AIN2RP, AIN2RN)
[AK4601] 016000391-E-01 - 99 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 006C ADC Mute & HPF Control ATSPAD AD1MUTE AD2MUTE ADMMUTE 0 AD1HPFN AD2HPFN ADMHPFN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ATSPAD: ADC Digital Volume Transition Time Setting (Table 46) 0: 4/fs (default) 1: 16/fs AD1MUTE: ADC1 Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable AD2MUTE: ADC2 Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable ADMMUTE: ADCM Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable AD1HPFN: ADC1 HPF Enable for DC Offset Cancelling 0: HPF Enable (default) 1: HPF Disable AD2HPFN: ADC2 HPF Enable for DC Offset Cancelling 0: HPF Enable (default) 1: HPF Disable ADMHPFN: ADCM HPF Enable for DC Offset Cancelling 0: HPF Enable (default) 1: HPF Disable
[AK4601] 016000391-E-01 - 100 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 006D DAC1 Lch Digital Volume VOLDA1L[7:0] 006E DAC1 Rch Digital Volume VOLDA1R[7:0] 006F DAC2 Lch Digital Volume VOLDA2L[7:0]
0070 DAC2 Rch Digital Volume VOLDA2R[7:0]
0071 DAC3 Lch Digital Volume VOLDA3L[7:0]
0072 DAC3 Rch Digital Volume VOLDA3R[7:0]
VOLDA1L[7:0]: Lch Digital Volume Setting of DAC1 (Table 53) Default: 18H (0dB) VOLDA1R[7:0]: Rch Digital Volume Setting of DAC1 (Table 53) Default: 18H (0dB) VOLDA2L[7:0]: Lch Digital Volume Setting of DAC2 (Table 53) Default: 18H (0dB) VOLDA2R[7:0]: Rch Digital Volume Setting of DAC2 (Table 53) Default: 18H (0dB) VOLDA3L[7:0]: Lch Digital Volume Setting of DAC3 (Table 53) Default: 18H (0dB) VOLDA3R[7:0]: Rch Digital Volume Setting of DAC3 (Table 53) Default: 18H (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0073 DAC Mute & Filter Setting ATSPDA DA1MUTE DA2MUTE DA3MUTE 0 DSMN DASD DASL
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 ATSPDA: DAC Digital Volume Transition Time Setting (Table 54) 0: 4/fs (default) 1: 16/fs DA1MUTE: DAC1 Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable DA2MUTE: DAC2 Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable DA3MUTE: DAC3 Soft Mute Enable 0: Soft Mute Disable (default) 1: Soft Mute Enable DSMN: Sampling Clock Setting for Delta Sigma Module of DAC 0: 12.288MHz / 11.2896MHz Fixed (default) 1: fs Based DASD, DASL: DAC Digital Filter Select (Table 57) 00: Sharp Roll-Off Filter 01: Slow Roll-Off Filter 10: Short Delay Sharp Roll-Off Filter (default ) 11: Short Delay Slow Roll-Off Filter
[AK4601] 016000391-E-01 - 101 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0074 DAC DEM Setting 0 DEM3[1:0] DEM2[1:0] DEM1[1:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 0 1 0 1 DEM1[1:0]: De-emphasis Filter Setting of DAC1 (Table 58) 00: 44.1kHz 01: OFF (default) 10: 48kHz 11: 32kHz DEM2[1:0]: De-emphasis Filter Setting of DAC2 (Table 58) 00: 44.1kHz 01: OFF (default) 10: 48kHz 11: 32kHz DEM3[1:0]: De-emphasis Filter Setting of DAC3 (Table 58) 00: 44.1kHz 01: OFF (default) 10: 48kHz 11: 32kHz
[AK4601] 016000391-E-01 - 102 - 2016/12 Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0
0075 VOL1 Lch Digital Volume VOL1L[7:0]
0076 VOL1 Rch Digital Volume VOL1R[7:0]
0077 VOL2 Lch Digital Volume VOL2L[7:0]
0078 VOL2 Rch Digital Volume VOL2R[7:0]
0079 VOL3 Lch Digital Volume VOL3L[7:0]
007A VOL3 Rch Digital Volume VOL3R[7:0] R/W R/W Default 18H VOL1L[7:0]: Lch Digital Volume Setting of VOL1 (Table 36) Default: 18H (0dB) VOL1R[7:0]: Rch Digital Volume Setting of VOL1 (Table 36) Default: 18H (0dB) VOL2L[7:0]: Lch Digital Volume Setting of VOL2 (Table 36) Default: 18H (0dB) VOL2R[7:0]: Rch Digital Volume Setting of VOL2 (Table 36) Default: 18H (0dB) VOL3L[7:0]: Lch Digital Volume Setting of VOL3 (Table 36) Default: 18H (0dB) VOL3R[7:0]: Rch Digital Volume Setting of VOL3 (Table 36) Default: 18H (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 007F VOL Setting ATSPVOL 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ATSPVOL: Digital Volume Transition Speed Setting of VOL (Table 37) 0: 4/fs (default) 1: 16/fs Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
0083 STO Flag Setting 1 0 PLLLOCKE 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PLLLOCKE: STO bit Setting of PLL Lock Signal 0: Do Not Output to STO bit (default) 1: Output to STO bit
[AK4601] 016000391-E-01 - 103 - 2016/12 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 008A Power Management 1 0 PMAD1 PMAD2 PMADM PMDA1 PMDA2 PMDA3 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMAD1: ADC1 Power Management Setting 0: Power Save Mode (default) 1: Normal Operation PMAD2: ADC2 Power Management Setting 0: Power Save Mode (default) 1: Normal Operation PMADM: ADCM Power Management Setting 0: Power Save Mode (default) 1: Normal Operation PMDAx(x=1~3): DAC1~3 Power Management Setting 0: Power Save Mode (default) 1: Normal Operation Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 008C Reset Control 0 0 1 CRESETN 0 HRESETN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 0 0 CRESETN: ADC1 and CODEC Reset 0: ADC1 and CODEC Reset (default) 1: Reset Release CODEC means ADC2, ADC, DAC1, DAC2 and DAC3. HRESETN: HUB Reset 0: HUB Reset (default) All ADC1/2, ADCM, DAC1/2/3 and Serial Signal Bus are Reset 1: HUB Reset Release Read Only Registers Addr [Hex] Register Name D7 D6 D5 D4 D3 D2 D1 D0
0102 Status Read Out 0 STO 0
STO: STO bit Status Read 0: Error State 1: Normal Operation (default)
- Recommended External Circuits
36 AINMP/AINM
37 AINMN
33 AIN5L
34 GNDIN5
35 AIN5R
31 AIN2LP/AIN3L
32 AIN2LN/AIN4L
29 AIN2RP/AIN3R
30 AIN2RN/AIN4R
26 AIN1L/INP1
25 INN1
28 AIN1R/INP2
27 INN2
41 VREFH
Figure 73. I2C Interface Connection Example
Figure 74. SPI Interface Connection Example
capacitors of small capacity, should be placed at positions as close as possible to the AK4601. pin outputs AVDD/2. A 2.2µF capacitor should be connected between the VCOM pin and AVSS. should be kept away as far as possible from this pin in order to avoid unwanted coupling into the AK4601. (typ). The pins that are connected to AC coupling capacitors require start-up time (time constant). has large out-of-band noise such as D/A converted signals. equal or larger than absolute maximum ratings. Figure 75. Input Buffer Circuit Example at fs=48kHz (Differential Input)
[AK4601] 016000391-E-01 - 107 - 2016/12 4. Analog Output The analog output is single-ended and the output signal range is typically 0.86 x AVDD Vpp centered on VCOM. The digital input data format is two’s compliment. Positive full-scale output corresponds to 7FFFFFFFH (@32bit) input code, Negative full scale is 80000000H (@32bit) and VCOM voltage ideally is 00000000H (@32bit). The Out-of-Band noise (shaping noise) generated by the internal delta-sigma modulator is attenuated by an integrated switched capacitor filter (SCF) and a continuous time filter (CTF). 5. Connection to Digital Circuit To minimize the noise from digital circuits, the digital output of the AK4601 must be connected to CMOS or low voltage logic ICs such as 74HC and 74AC for CMOS and 74LV, 74LV-A, 74ALVC and 74AVC for low voltage logic ICs.
[AK4601] 016000391-E-01 - 108 - 2016/12 14. Package ■ Outline Dimensions 1 12 7.0 ±0.2 9.0 ±0.2 7.0 ±0.2 9.0 ±0.2 0.22 0.08 48-pin LQFP(Unit: mm) 0.10 37 24 25 36 0.09 0.20 1.40 0.05 0.13 0.13 1.70Max 0° 10° 0.10 0.30 ~ 0.75 0.5 S S M ■ Material and Lead Finish Package: Epoxy Lead frame: Copper Terminal surface treatment: Soldering (Pb free) plate
[AK4601] 016000391-E-01 - 109 - 2016/12 ■ Marking AK4601VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4601VQ 4) Asahi Kasei Logo 15. Ordering Guide ■ Ordering Guide AK4601 -40 +85C 48-pin LQFP (0.5mm pitch) AKD4601 Evaluation Board for the AK4601
[AK4601] 016000391-E-01 - 110 - 2016/12 16. Revision History Date (Y/M/D) Revision Reason Page Contents 16/03/23 00 First Edition 16/12/08 01 Error Correction 5 Figure of PDN pin I/O pin → Input pin
102 ATSPVOL: Digital Volume Transition Speed
Setting of VOL (Table 37) 0: 1/fs (default) → 4/fs (default) 1: 4/fs → 16/fs
[AK4601] 016000391-E-01 - 111 - 2016/12 IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized d istributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accur acy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications . AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMA TION IN YOUR PRODUCT DESIGN OR APPLICA TIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or seriou s public impact, including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance -related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situ ations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information c ontained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.