AK4586VQ

AK4586 AKM | Alldatasheet

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ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 1 - GENERAL DESCRIPTION The AK4586 is a single chip CODEC that includes two channels of ADC and six channels of DAC. The ADC outputs 24bit data and the DAC accepts up to 24bit input data. The ADC has the Enhanced Dual Bit architecture with wide dynamic range. The DAC introduces the new developed Advanced Multi-Bit architecture, and achieves wider dynamic range and lower outband noise. The AK4586 also has a digital audio receiver (DIR) compatible with 96kHz, 24bits. The AK4586 can automatically detect a Non-PCM bit stream. The digital audio output can be selected from the ADC output or the digital input. Control may be set directly by programmed through a separate serial interface. The AK4586 has a dynamic range of 100dB for ADC, 106dB for DAC and is well suited for digital surround for home theater and car audio. The AK4586 also has the balance volume control corresponding to the AC-3 system. The AK4586 is available in a small 44pin LQFP package which will reduce system space. *AC-3 is a trademark of Dolby Laboratories.

FEATURES

/box3 2ch 24bit ADC - 64x Oversampling - Sampling Rate up to 96kHz - Linear Phase Digital Anti-Alias Filter - Single-Ended Input - S/(N+D): 90dB - Dynamic Range, S/N: 100dB - Digital HPF for offset cancellation - Overflow flag /box3 6ch 24bit DAC - 128x Oversampling - Sampling Rate up to 96kHz - 24bit 8 times Digital Filter - Single-Ended Outputs - On-chip Switched-Capacitor Filter - S/(N+D): 90dB - Dynamic Range, S/N: 106dB - Individual channel digital volume with 256 levels and 0.5dB step - Soft mute - Zero Detect Function /box3 4 inputs 24bit DIR - Supports IEC60958 consumer mode, S/PDIF, EIAJ CP1201 consumer mode - Low jitter Analog PLL - PLL Lock Range: 32k ∼ 96kHz - Clock Source: PLL or X'tal - 4 channel Receivers input and 1 through transmission output - De-emphasis for 32kHz, 44.1kHz and 48kHz - Dedicated Detect Pins Non-PCM Bit Stream Detect, DTS-CD Bit Stream Detect, Validity Flag Detect, 96kHz Sampling Detect, Unlock & Parity Error Detect, Emphasis Detect, fs change Detect - Supports up to 24bit Audio Data Format - Audio I/F: Master or Slave Mode - 32bits Channel Status Buffer Multi-channel Audio CODEC with DIR AK4586

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 2 - - Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream - Master Clock Outputs:128fs/256fs/512fs /box3 I/F format: MSB justified, LSB justified(20bit,24bit), I2S or TDM /box3 High Jitter Tolerance /box3 TTL Level Digital I/F /box3 4-wire Serial and I2C Bus µP I/F for mode setting /box3 Extenal Master Clock Input: - 256fs, 384fs or 512fs for fs=44.1kHz to 48kHz - 128fs, 192fs or 256fs for fs=88.2kHz to 96kHz /box3 Power Supply: 4.5 to 5.5V /box3 Power Supply for output buffer: 2.7 to 5.5V /box3 Small 44pin LQFP /square6 Block Diagram ADCLIN HPF ADCRIN HPF DAC DATTLPFLOUT1 DAC DATTLPFROUT1 DAC DATTLPFLOUT2 DAC DATTLPFROUT2 DAC DATTLPFLOUT3 DAC DATTLPFROUT3 Audio I/F Input Selector Clock Recovery Clock Generator X’tal OscillatorµP I/F XTI XTO MCKO TX RX1 RX2 RX3 RX4 SDTO BICK LRCK SDTI1 SDTI2 SDTI3 CSN CCLK CDTI CDTO MCLK BICK SDOUT LRCK SDIN1 SDIN2 SDIN3 DAIF Decoder DEM

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 3 - /square6 Ordering Guide AK4586VQ -40 ∼ +85°C 44pin LQFP(0.8mm pitch) AKD4586 Evaluation Board for AK4586 /square6 Pin Layout XTO PDN XTI/EXTCLK DVDD 3 DVSS 4 TVDD TX 6 MCKO 7 LRCK 8 BICK 9 SDTO 10 SDTI1 11 RX143 I2C42 RX339 SLAVE38 RX437 PVSS36 R35 PVDD34 SDTI2 12 SDTI3 13 INT0 14 INT1 15 CAD1/CDTO 16 SCL/CCLK 18 CAD0/CSN 19 DZF2/OVF 20 AVSS 21 AVDD 22 RIN LIN ROUT1 LOUT1 ROUT2 LOUT2 ROUT3 LOUT3 DZF1 VCOM VREFH AK4586VQ Top View SDA/CDTI RX2 TST

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 4 - /square6 Compatibility with AK4527B/29 Functions AK4527B/29 AK4586 ADC S/(N+D) 92dB 90dB ADC Dynamic Range, S/N 102dB 100dB DAC channel 6ch/8ch 6ch Master mode Not available Available Parallel mode Available Not available Read operation for internal register Not available Available Chip address at 4-wire serial mode 2bit selectable fixed to “00” /square6 Compatibility with AK4112A Functions AK4112A AK4586 Power supply 2.7 ∼ 3.6V 4.5 ∼ 5.5V Rock range 22k ∼ 108kHz 32k ∼ 96kHz Master clock output 2 pins 1 pin External master clock input 256fs/512fs 256fs/384fs/512fs for Normal speed 128fs/192fs/256fs for Double speed Detect pins 4 pins 2 pins DTS-CDdetect Not available Available CRC Available Not available Parallel mode Available Not available I2C bus mode Not available Available Digital input level CMOS TTL

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 5 - PIN/FUNCTION No. Pin Name I/O Function

1 XTO O X'tal Output Pin

XTI I X'tal Input Pin 2 EXTCLK I External Master Clock Input Pin 3 DVDD - Digital Power Supply Pin, 4.5V∼5.5V

4 DVSS - Digital Ground Pin, 0V

5 TVDD - Output Buffer Power Supply Pin, 2.7V∼5.5V

6 TX O Transmit channel (through data) Output Pin

7 MCKO O Master Clock Output Pin

8 LRCK I/O Input/Output Channel Clock Pin

9 BICK I/O Audio Serial Data Clock Pin

10 SDTO O Audio Serial Data Output Pin

11 SDTI1 I DAC1 Audio Serial Data Input Pin

12 SDTI2 I DAC2 Audio Serial Data Input Pin

13 SDTI3 I DAC3 Audio Serial Data Input Pin

14 INT0 O Interrupt 0 pin

15 INT1 O Interrupt 1 pin

CDTO O Control Data Output Pin in 4-wire serial control mode 16 CAD1 I Chip Address 1 Pin in I 2C bus control mode CDTI I Control Data Input Pin in 4-wire serial control mode 17 SDA I/O Control Data Input/Output Pin in I 2C bus control mode CCLK I Control Data Clock Pin in 4-wire serial control mode 18 SCL I Control Data Clock Pin in I 2C bus control mode CSN I Chip Select Pin in 4-wire serial control mode 19 CAD0 I Chip Address 0 Pin in I 2C bus control mode DZF2 O Zero Input Detect 2 Pin (Note 1) When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”. OVF O Analog Input Overflow Detect Pin (Note 2) This pin goes to “H” if the analog input of Lch or Rch is overflows.

21 AVSS - Analog Ground Pin, 0V

22 AVDD - Analog Power Supply Pin, 4.5V∼5.5V

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 6 - No. Pin Name I/O Function

23 VREFH I Positive Voltage Reference Input Pin, AVDD

24 VCOM O Common Voltage Output Pin, AVDD/2

Large external capacitor around 2.2µF is used to reduce power-supply noise.

25 DZF1 O Zero Input Detect 1 Pin (Note 1)

When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin goes to “H”.

26 LOUT3 O DAC3 Lch Analog Output Pin

27 ROUT3 O DAC3 Rch Analog Output Pin

28 LOUT2 O DAC2 Lch Analog Output Pin

29 ROUT2 O DAC2 Rch Analog Output Pin

30 LOUT1 O DAC1 Lch Analog Output Pin

31 ROUT1 O DAC1 Rch Analog Output Pin

32 LIN I Lch Analog Input Pin

33 RIN I Rch Analog Input Pin

34 PVDD - PLL Power Supply Pin, 4.5V∼5.5V

35 R - External Resistor Pin

18kΩ +/-1% resistor to PVSS externally.

36 PVSS - PLL Ground Pin, 0V

37 RX4 I Receiver Channel 4 Pin (Internal biased pin)

38 SLAVE I Slave Mode Pin

“L”: Master mode or Slave mode, “H”: Slave mode

39 RX3 I Receiver Channel 3 Pin (Internal biased pin)

40 TST I Test Pin

This pin should be connected to DVSS.

41 RX2 I Receiver Channel 2 Pin (Internal biased pin)

42 I2C I Control Mode Select Pin

“L”: 4-wire Serial, “H”: I2C Bus

43 RX1 I Receiver Channel 1 Pin (Internal biased pin)

44 PDN I Power-Down & Reset Pin

When “L”, the AK4586 is powered-down, all output pins go to “L” and the control registers are reset to default state. If the state of CAD1-0 changes, then the AK4586 must be reset by PDN. Notes: 1. The group 1 and 2 can be selected by DZFM2-0 bits. 2. This pin becomes OVF pin if OVFE bit is set to “1”. 3. All input pins except internal biased pins should not be left floating.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 7 - ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS, PVSS=0V; Note 4) Parameter Symbol min max Units Power Supplies Analog Digital PLL Output buffer |AVSS-DVSS| (Note 5) |AVSS-PVSS| (Note 5) AVDD DVDD PVDD TVDD ∆GND1 ∆GND2 -0.3 -0.3 -0.3 -0.3 6.0 6.0 6.0 6.0 0.3 0.3 V V V V V V Input Current (any pins except for supplies) IIN - ±10 mA Analog Input Voltage VINA -0.3 AVDD+0.3 V Digital Input Voltage (XTI/EXTCLK, SDTI1-3, CDTI/SDA, CCLK/SCL, CSN/CAD0 pins) (LRCK, BICK, CDTO/CAD1 pins) (RX1-4, SLAVE, TST, I2C, PDN pins) VIND1 VIND2 VIND3 -0.3 -0.3 -0.3 DVDD+0.3 TVDD+0.3 PVDD+0.3 V V V Ambient Temperature (power applied) Ta -40 85 °C Storage Temperature Tstg -65 150 °C Notes: 4. All voltages with respect to ground. 5. AVSS, DVSS and PVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS, PVSS=0V; Note 4) Parameter Symbol min typ max Units Power Supplies (Note 6) Analog Digital PLL Output buffer AVDD DVDD PVDD TVDD 4.5 4.5 4.5 2.7 5.0 5.0 5.0 5.0 5.5 5.5 5.5 5.5 V V V V Notes: 4. All voltages with respect to ground. 6. The power up sequence between AVDD, DVDD, PVDD and TVDD is not critical. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 8 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD, TVDD=5V; AVSS, DVSS=0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement Frequency=20Hz∼20kHz at fs=48kHz, 20Hz~40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units ADC Analog Input Characteristics Resolution 24 Bits S/(N+D) (-0.5dBFS) fs=48kHz fs=96kHz dB dB DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz, A-weighted 100 100 dB dB S/N (Note 7) fs=48kHz, A-weighted fs=96kHz, A-weighted 100 100 dB dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.3 dB Gain Drift 20 - ppm/°C Input Voltage fs=48kHz AIN=0.62xVREFH fs=96kHz AIN=0.65xVREFH 2.90 3.05 3.10 3.25 3.30 3.45 Vpp Vpp Input Resistance (Note 8) 15 25 kΩ Power Supply Rejection (Note 9) 50 dB DAC Analog Output Characteristics Resolution 24 Bits S/(N+D) fs=48kHz fs=96kHz dB dB DR (-60dBFS) fs=48kHz, A-weighted fs=96kHz, A-weighted 106 106 dB dB S/N (Note 10) fs=48kHz, A-weighted fs=96kHz, A-weighted 106 106 dB dB Interchannel Isolation 90 110 dB DC Accuracy Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 - ppm/°C Output Voltage AOUT=0.6xVREFH 2.75 3.0 3.25 Vpp Load Resistance 5 kΩ Power Supply Rejection (Note 9) 50 dB Power Supplies Power Supply Current Normal Operation (PDN = “H”) (Note 11) AVDD PVDD DVDD+TVDD fs=48kHz (Note 12) fs=96kHz Power-down mode (PDN = “L”) (Note 13) 200 mA mA mA mA µA Notes: 7. S/N measured by CCIR-ARM is 96dB(@fs=48kHz). 8. Input resistance is 16kΩ typically at fs=96kHz. 9. PSR is applied to AVDD, DVDD, PVDD and TVDD with 1kHz, 50mVpp. VREFH pin is held a constant voltage. 10. S/N measured by CCIR-ARM is 102dB(@fs=48kHz). 11. C L=20pF, X'tal=24.576MHz, CM1-0= “10”, OCKS= “10”. 12. TVDD=3mA(typ). 13. In the power-down mode. RX inputs are open and all digital input pins including clock pins (MCLK, BICK, LRCK) are held DVSS.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 9 - FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; fs=48kHz) Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 14) ±0.1dB -0.2dB -3.0dB PB 0 20.0 23.0 18.9 kHz kHz kHz Stopband SB 29.4 kHz Passband Ripple PR ±0.1 dB Stopband Attenuation SA 65 dB Group Delay (Note 15) GD 17.0 1/fs Group Delay Distortion ∆GD 0 µs ADC Digital Filter (HPF): Frequency Response (Note 14) -3dB -0.1dB FR 1.0 6.5 Hz Hz DAC Digital Filter: Passband (Note 14) -0.1dB -6.0dB PB 0 24.0 21.8 kHz kHz Stopband SB 26.2 kHz Passband Ripple PR ±0.02 dB Stopband Attenuation SA 54 dB Group Delay (Note 15) GD 19.1 1/fs DAC Digital Filter + Analog Filter: Frequency Response: 0 ∼ 20.0kHz 40.0kHz (Note 16) FR FR ±0.2 ±0.3 dB dB Notes: 14. The passband and stopband frequencies scale with fs. 15. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 20/24bit data of both channels on input register to the output of analog signal. 16. fs=96kHz. DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V) Parameter Symbol min typ max Units High-Level Input Voltage (Except XTI pin) (XTI pin) Low-Level Input Voltage (Except XTI pin) (XTI pin) Input Voltage at AC Coupling (Note 17) VIH VIH VIL VIL VAC 2.2 70%DVDD 40%DVDD 0.8 30%DVDD V V V V Vpp High-Level Output Voltage (Except TX, DZF1, DZF2/OVF pins: Iout=-400µA) (TX pin: Iout=-400µA) (DZF1, DZF2/OVF pins: Iout=-400µA) Low-Level Output Voltage (Except SDA pin: Iout= 400µA) (SDA pin: Iout= 3mA) VOH VOH VOH VOL VOL TVDD-0.5 DVDD-0.5 AVDD-0.5 0.5 0.4 V V V V V Input Leakage Current Iin - - ±10 µA Notes: 17. In case of connecting capacitance to XTI pin (refer to Figure 4).

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 10 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.5∼5.5V; TVDD=2.7∼5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock 256fsn, 128fsd: Pulse Width Low Pulse Width High 384fsn, 192fsd: Pulse Width Low Pulse Width High 512fsn, 256fsd: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 11.2896 16.9344 22.5792 12.288 18.432 24.576 MHz ns ns MHz ns ns MHz ns ns MCKO output Frequency Duty (Note 18) fMCK dMCK 5.6448 24.576 MHz PLL Clock Recover Frequency fPLL 32 96 kHz LRCK Timing TDM= “0” LRCK frequency Normal Speed Mode Double Speed Mode Duty Cycle fsn fsd Duty 88.2 kHz kHz TDM= “1” (Slave mode) LRCK frequency “H” time “L” time fsn tLRH tLRL 1/256fs 1/256fs kHz ns ns TDM= “1” (Master mode) LRCK frequency “H” time (Note 19) fsn tLRH 1/8fs kHz ns Notes: 18. Except the case CLKDIV= “0” for the external clock input. C L=15pF when MCKO is above 22.5792MHz. 19. “L” time at I 2S format.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 11 - Parameter Symbol min typ max Units Audio Interface Timing (Slave mode) TDM= “0” BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 20) BICK “↑” to LRCK Edge (Note 20) LRCK to SDTO(MSB) (Note 21) BICK “↓” to SDTO SDTI1-3, DAUX Hold Time SDTI1-3, DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS 160 ns ns ns ns ns ns ns ns ns TDM= “1” BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 20) BICK “↑” to LRCK Edge (Note 20) BICK “↓” to SDTO SDTI1 Hold Time SDTI1 Setup Time tBCK tBCKL tBCKH tLRB tBLR tBSD tSDH tSDS ns ns ns ns ns ns ns ns Audio Interface Timing (Master mode) TDM= “0” BICK Frequency BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO SDTI1-3 Hold Time SDTI1-3 Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS -20 64fs Hz ns ns ns ns TDM= “1” BICK Frequency BICK Duty BICK “↓” to LRCK Edge BICK “↓” to SDTO SDTI1 Hold Time SDTI1 Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS -12 256fs Hz ns ns ns ns Notes: 20. BICK rising edge must not occur at the same time as LRCK edge. 21. MSB justified format.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 12 - Parameter Symbol min typ max Units Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 22) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP 4.7 4.0 4.7 4.0 4.7 0.25 4.0 100 1.0 0.3 kHz µs µs µs µs µs µs µs µs µs µs ns Power-down & Reset Timing PDN Pulse Width (Note 23) PDN “↑” to SDTO valid (Note 24) tPD tPDV 150 522 ns 1/fs Notes: 22. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. 23. The AK4586 can be reset by bringing PDN “L” to “H” upon power-up. 24. These cycles are the number of LRCK rising from PDN rising. 25. I 2C is a registered trademark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd I 2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD, PVDD=4.5~5.5V; TVDD=2.7~5.5V) Parameter Symbol min typ max Units Input Resistance Zin 10 kΩ Input Voltage VTH 200 mVpp Input Hysteresis VHY - 50 mV Input Sample Frequency fs 32 - 96 kHz

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 13 - /square6 Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fMCKO 50%TVDDMCKO tMCKLtMCKH dMCK = tMCKH x fMCK x 100 = tMCKL x fMCK x 100 1/fs LRCK VIH VIL tLRLtLRH Duty = tLRH x fs x 100 = tLRL x fs x 100 tBCK tBCKL VIH tBCKH BICK VIL Clock Timing (TDM= “0”) 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fs LRCK VIH VIL tLRLtLRH tBCK tBCKL VIH tBCKH BICK VIL Clock Timing (TDM= “1”)

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 14 - tLRB LRCK VIH BICK VIL tLRS SDTO 50%TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Audio Interface Timing (Slave mode, TDM= “0”) tLRB LRCK VIH BICK VIL SDTO 50%TVDD tBSD VIH VIL tBLR tSDS SDTI VIH VIL tSDH Audio Interface Timing (Slave mode, TDM= “1”) LRCK BICK SDTO tBSD tMBLR 50%TVDD 50%TVDD 50%TVDD SDTI tSDHtSDS VIH VIL Audio Interface Timing (Master Mode)

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 15 - tCCKL CSN CCLK tCDS CDTI tCDH tCSS C0 A4 tCCKH CDTO Hi-Z R/WC1 VIH VIL VIH VIL VIH VIL WRITE/READ Command Input Timing (4-wire serial mode) tCSW CSN CCLK CDTI D2 D0 tCSH CDTO Hi-Z D1D3 VIH VIL VIH VIL VIH VIL WRITE Data Input Timing (4-wire serial mode) CSN CCLK tDCD CDTO D7 D6 CDTI A1 A0 D5Hi-Z 50%TVDD VIH VIL VIH VIL VIH VIL READ Data Output Timing 1 (4-wire serial mode)

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 16 - CSN CCLK tCCZ CDTO D2 D1 CDTI D0D3 tCSW tCSH 50%TVDD VIH VIL VIH VIL VIH VIL READ Data Output Timing 2 (4-wire serial mode) tHIGH SCL SDA VIH tLOWtBUF tHD:STA tR tF tHD:DAT tSU:DAT tSU:STA Stop Start Start Stop tSU:STO VIL VIH VIL tSP I2C Bus mode Timing tPD VIL PDN tPDV SDTO 50%TVDD VIH Power-down & Reset Timing

received sync interval is incorrect. PLL is also operating and the recovered data such as C bits can be monitored.

0 ON ON PLL RX 2 1 0

1 ON ON X'tal ADC

Table 1. Clock Operation Mode Select Table 2. Master Clock Output Frequency Select (PLL mode)

Table 3. Sampling Speed Mode (x: Don’t care) Table 4. Master Clock Input Frequency Select (X’tal mode)

0 XTI x1

1 XTI x1/2

Table 5. Master Clock Output Select (X’tal mode) Figure 1. Master Clock Output Select

CS12 bit in control register. Table 6. Sampling frequency information in Consumer Mode

0 OFF ≠ 0X100

1 ON 0X100

Table 7. Pre-emphasis information in Consumer Mode

bypassed if bit 0 of the channel status byte 0 is “1”. Table 8. De-emphasis Auto Control at DEAU=“1” and PEM=“1” Table 9. De-emphasis Manual Control at DEAU=“0” and PEM=“1” The AK4586 has a power-down mode for all circuits by PDN pin or can be partially powered-down by internal register. Table 10. Reset & Power Down

bit stream driving the transmit channel (TX, Table 12). The TX output can be stopped by setting TXE bit “0”. Table 11. Recovery data select Table 12. Output data select

There are the following eight factors which INT1-0 pins go to “H”.

1. UNLOCK: “1” when the PLL goes UNLOCK state.
2. PAR: “1” when parity error or biphase coding error is detected.

Updated every sub-frame cycle. Reading this register resets itself.

1. AUTO: “1” when Non-PCM Bit Stream is detected.
2. DTSCD: “1” when DTS-CD Bit Stream is detected.
3. AUDION: “1” when the “AUDIO” bit in recovered channel status indicates “1”.
4. STC: “1” when FS1, FS0 or PEM bit changes. Reading this register resets itself.
5. V: “1” when validity flag is detected.
6. RFS96: “1” when fs=88.2kHz or more (RFS96 bit is set by XFS96 bit at x’tal mode or AFS96= “0”).

INT1-0 pins output the ORed signal among those eight factors. However, each factor can be masked by each mask bit. AUDION and V. INT1-0 pins are “L” when the PLL is OFF (Clock Operation Mode 1). Table 13. Error handling

Figure 9. INT0/1 pin timing

Figure 10. Error Handling Sequence Example

mode 3-7, the last 4LSBs are auxiliary data (see Figure 11). Mode 4, 5, 6 and 7 in SDTI input formats can be used for 16-20bit data by zeroing the unused LSBs. Figure 11. Bit configuration Table 14. Audio Data Format (TDM= “0”)

32 BICK

256 BICK

64 BICK

Figure 16. Mode 8 Timing Figure 17. Mode 11 Timing

Figure 18. Mode 12, 14 Timing

32 BICK 64 BICK

Figure 19. Mode 13, 15 Timing

also scales with sampling rate (fs). The AK4586 has overflow detect function for analog input. Overflow detect function is enable if OVFE bit is set to “1”. @fs=48kHz) after PDN = “↑”, and then overflow detection is enabled. The AK4586 has two pins for zero detect flag outputs. Channel grouping can be selected by DZFM2-0 bits (Table 16). zero after going DZF1(DZF2) “H”. Table 16. Zero detect control

be set by each ATT7-0 bits (Table 17). Table 17. Attenuation level of digital attenuator Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 18). Table 18. Transition time between set values of ATT7-0 bits

source without stopping the signal transmission. (1) The output signal is attenuated by -∞ during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input have the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB. is not zero after going DZF “H”. Figure 20. Soft mute and zero detection

of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. Figure 21. 4-wire Serial Control I/F Timing

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 39 - /square6 Mapping of Program Registers Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down & Reset 0 0 0 0 PWVRN PWADN PWDAN RSTN 01H Path Control 0 0 LOOP1 LOOP0 IPS1 IPS0 OPS1 OPS0 02H Clock Mode Control 0 CLKDIV OCKS1 OCKS0 ICKS1 ICKS0 CM1 CM0 03H Output Control 0 SMUTE TXE BCU OVFE DZFM2 DZFM1 DZFM0 04H Receiver Control XFS96 AFS96 CS12 EFH1 EFH0 DEAU DEM1 DEM0 05H I/F Format & ATT Speed 0 0 ATS1 ATS0 TDM DIF2 DIF1 DIF0 06H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 09H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0AH LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0BH ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0CH INT0 Mask MRFS0 MV0 MSTC0 MAUD0 MDTS0 MAUT0 MPAR0 MUNL0 0DH INT1 Mask MRFS1 MV1 MSTC1 MAUD1 MDTS1 MAUT1 MPAR1 MUNL1 0EH Receiver Status 0 RFS96 V STC AUDION DTSCD AUTO PAR UNLOCK 0FH Receiver Status 1 0 0 0 0 0 PEM FS1 FS0 10H Channel Status Byte 0 C7 C6 C5 C4 C3 C2 C1 C0 11H Channel Status Byte 1 C15 C14 C13 C12 C11 C10 C9 C8 12H Channel Status Byte 2 C23 C22 C21 C20 C19 C18 C17 C16 13H Channel Status Byte 3 C31 C30 C29 C28 C27 C26 C25 C24 14H Burst Preamble Pc Byte 0 PC7 DTSCD PC5 PC4 PC3 PC2 PC1 PC0 15H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 16H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 17H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 Note: For addresses from 18H to 1FH, data is not written. When PDN goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset and DZF1-2 pins go to “H”, but registers are not initialized to their default values. All data can be written to the register even if PWVRN, PWADN or PWDAN bit is “0”.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 40 - /square6 Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down & Reset 0 0 0 0 PWVRN PWADN PWDAN RSTN R/W RD RD RD RD R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 RSTN: Internal timing reset 0: Reset. DZF1-2 pins go to “H”, but registers are not initialized. 1: Normal operation PWDAN: Power-down control of DAC1-3 0: Power-down 1: Normal operation PWADN: Power-down control of ADC 0: Power-down 1: Normal operation PWVRN: Power-down control of reference voltage 0: Power-down. ADC, DAC and PLL are powered-down. 1: Normal operation Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Path Control 0 0 LOOP1 LOOP0 IPS1 IPS0 OPS1 OPS0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 OPS1-0: Output Through Data Select (Table 12) Default: “00”, RX1 IPS1-0: Input Recovery Data Select (Table 11) Default: “00”, RX1 LOOP1-0: Loopback mode enable 00: Normal (No loop back) 01: LIN → LOUT1, LOUT2, LOUT3, LOUT4 RIN → ROUT1, ROUT2, ROUT3, ROUT4 The ADC digital output (RX data in the PLL mode) is connected to the digital DAC input. In this mode, the input DAC data to SDTI1-3 is ignored. 10: SDTI1(L) → SDTI2(L), SDTI3(L) SDTI1(R) → SDTI2(R), SDTI3(R) In this mode the input DAC data to SDTI2-3 is ignored. 11: N/A LOOP1-0 should be set to “00” at TDM bit “1”.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 41 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Clock Mode Control 0 CLKDIV OCKS1 OCKS0 ICKS1 ICKS0 CM1 CM0 R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 CM1-0: Master Clock Operation Mode Select (Table 1) Default: “00”, mode 0 OCKS1-0: Master Clock Output Frequency Select at PLL mode (Table 2) Default: “00”, mode 0 ICKS1-0: Master Clock Input Frequency Select at X’tal mode (Table 4) Default: “00”, mode 0 CLKDIV: Master Clock Output Select at X’tal mode (Table 5) 0: Same frequency as crystal oscillator 1: Half frequency of crystal oscillator

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 42 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Output Control 0 SMUTE TXE BCU OVFE DZFM2 DZFM1 DZFM0 R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 1 1 1 DZFM2-0: Zero detect mode select (Table 16) Initial: “111”, disable OVFE: Overflow detection enable 0: Disable, pin#20 becomes DZF2 pin. 1: Enable, pin#20 becomes OVF pin. BCU: Block Start and C/U/V Output Mode When BCU=1, the 4 output pins change another function. DZF1 Pin → Block start signal DZF2 Pin → C bit INT1 Pin → U bit TX Pin → V bit The block signal goes high at the start of frame 0 and remains high until the end of frame 31. (B, C, U, V output timing at RX mode, master mode) B C (or U,V) LRCK C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)C(R191) 1/4fs SDTO (except I2S) L191 R191 L0 R30 R31L31 SDTO ( I2S) L191 R191 L30 L31R30L0R190 TXE: TX Output Enable 0: Disable. TX output is “L”. 1: Enable SMUTE: Soft Mute Enable (Figure 20) 0: Normal operation 1: All DAC outputs soft-muted

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 43 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Receiver Control XFS96 AFS96 CS12 EFH1 EFH0 DEAU DEM1 DEM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 0 1 1 0 1 DEM1-0: De-emphasis Control (Table 9) The setting of DEM1-0 bits is ignored at DEAU bit “1”. Default: “01”, OFF DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK (default) 10: 2048 LRCK 11: 4096 LRCK CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS1 and FS0. AFS96: Sampling Speed Mode Auto Setting Mode Enable (Table 3) 0: Disable, sampling mode is set by XFS96 bit. 1: Enable, sampling mode is automatically set by the register value of RFS96 bit at PLL mode. XFS96: ADC and DAC Sampling Speed Mode Select (X’tal Mode or AFS96= “0”, Table 3) 0: Normal speed mode 1: Double speed mode The sampling speed mode is defined by RFS96 and the setting of XFS96 is ignored at AFS96 bit “1” in the PLL mode. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H I/F Format & ATT Speed 0 0 ATS1 ATS0 TDM DIF2 DIF1 DIF0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 1 0 0 DIF2-0: Audio Data Format Control (Table 14, Table 15) Default: “100”, mode 4 TDM: TDM Format Select 0: Normal format 1: TDM format ATS1-0: Digital attenuator transition time setting (Table 18) Default: “00”, mode 0

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 44 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H LOUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H ROUT1 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H LOUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 09H ROUT2 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0AH LOUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 0BH ROUT3 Volume Control ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ATT7-0: Attenuation Level (Table 17) Default: all “0” (0dB)

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 45 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH INT0 Mask MRFS0 MV0 MSTC0 MAUD0 MDTS0 MAUT0 MPAR0 MUNL0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 0 0 MULK0: Mask Enable for UNLOCK bit (Default: 0) 0: Mask disable 1: Mask enable MPAR0: Mask Enable for PAR bit (Default: 0) 0: Mask disable 1: Mask enable MAUT0: Mask Enable for AUTO bit (Default: 1) 0: Mask disable 1: Mask enable MDTS0: Mask Enable for DTSCD bit (Default: 1) 0: Mask disable 1: Mask enable MAUD0: Mask Enable for AUDIO bit (Default: 1) 0: Mask disable 1: Mask enable MSTC0: Mask Enable for STC bit (Default: 1) 0: Mask disable 1: Mask enable MV0: Mask Enable for V bit (Default: 1) 0: Mask disable 1: Mask enable MRFS0: Mask Enable for RFS96 bit (Default: 1) 0: Mask disable 1: Mask enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH INT1 Mask MRFS1 MV1 MSTC1 MAUD1 MDTS1 MAUT1 MPAR1 MUNL1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 1 0 0 0 1 1 MULK1: Mask Enable for UNLOCK bit (Default: 1) 0: Mask disable 1: Mask enable MPAR1: Mask Enable for PAR bit (Default: 1) 0: Mask disable 1: Mask enable MAUT1: Mask Enable for AUTO bit (Default: 0) 0: Mask disable 1: Mask enable MDTS1: Mask Enable for DTSCD bit (Default: 0) 0: Mask disable 1: Mask enable MAUD1: Mask Enable for AUDIO bit (Default: 0) 0: Mask disable 1: Mask enable MSTC1: Mask Enable for STC bit (Default: 1) 0: Mask disable 1: Mask enable MV1: Mask Enable for V bit (Default: 0) 0: Mask disable 1: Mask enable MRFS1: Mask Enable for RFS96 bit (Default: 1) 0: Mask disable 1: Mask enable

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 46 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Receiver status 1 RFS96 V STC AUDION DTSCD AUTO PAR UNLOCK R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 UNLOCK: PLL Lock Status 0: Lock 1: Unlock PAR: Parity Error or Biphase Error Status 0: No error 1: Error It is “1” if parity error or biphase error is detected in the sub-frame. AUTO: Non-PCM Bit Steam Auto Detect 0: No detect 1: Detect DTSCD: DTS-CD Bit Steam Auto Detect 0: No detect 1: Detect AUDION: Audio Bit Output 0: Audio 1: Non audio This bit is made by encoding channel status bits. STC: Sampling Frequency or Pre-emphasis Information Change Detect 0: No detect 1: Detect It is “1” if FS1, FS0 or PEM bit changes. V: Validity Bit 0: Valid 1: Invalid RFS96: 96kHz Sampling Detect at Recovery Mode 0: fs=48kHz or less 1: fs=88.2kHz or more Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Receiver status 2 0 0 0 0 0 PEM FS1 FS0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 FS1-0: Sampling Frequency Bit Output This bit is made by encoding channel status bits. PEM: Pre-emphasis Bit Output 0 : O F F 1 : O N This bit is made by encoding channel status bits.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 47 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H Channel Status Byte 0 C7 C6 C5 C4 C3 C2 C1 C0 11H Channel Status Byte 1 C15 C14 C13 C12 C11 C10 C9 C8 12H Channel Status Byte 2 C23 C22 C21 C20 C19 C18 C17 C16 13H Channel Status Byte 3 C31 C30 C29 C28 C27 C26 C25 C24 R/W RD Default Not initialized C31-0: Channel Status Byte 3-0 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 14H Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 15H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 16H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 17H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1

Figure 31. Data structure in IEC60958 Table 19. Burst preamble words

Table 20. Fields of burst info Pc

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 52 - 1. Grounding and Power Supply Decoupling The AK4586 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and PVDD are usually supplied from analog supply in system. Alternatively if AVDD, DVDD and PVDD are supplied separately, the power up sequence is not critical. AVSS, DVSS and PVSS of the AK4586 must be connected to analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4586 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The voltage of VREFH sets the analog input/output range. VREFH pin is normally connected to AVDD with a 0.1µF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREFH and VCOM pins in order to avoid unwanted coupling into the AK4586. 3. Analog Inputs ADC inputs are single-ended and internally biased to VCOM. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp (typ). The ADC output data format 2’s compliment. The DC offset is removed by the internal HPF. The AK4586 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK4586 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. 4. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The input signal range scales with the supply voltage and nominally 0.6 x VREFH Vpp. The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal output is VCOM voltage for 000000H(@24bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband. DC offsets on analog outputs are eliminated by AC coupling since DAC outputs have DC offsets of a few mV.

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 53 - PACKAGE 0.15 0.17±0.050.37±0.10 10.00 1.70max 11 1 2333 44pin LQFP (Unit: mm) 10.00 12.80±0.30 0.80 12.80±0.30 0∼0.2 0°∼10° 0.60±0.20 /square6 Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate

ASAHI KASEI [AK4586] MS0097-E-01 2001/12 - 54 - MARKING AK4586VQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4586VQ 4) Asahi Kasei Logo IMPORTANT NOTICE

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