AK4533

AK4533 AKM | Alldatasheet

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Technical content

[ASAHI KASEI] <Revision 0.9a> July 00 Featues [ADC]

• 1ch mono16-bit ADC (For Microphone)
• 1st MIC Amplifier: 20dB Fixed Gain
• 2nd Amplifier: from -8dB to +27.5dB (0.5dB step)
• AGC function
• Analog Performance: - S/N: 82dBA @ fs=44.1kHz, MIC_GAIN=20dB(AGC=off, 0dB) [Sampling Frequency] Audio : from 8kHz to 44.1kHz [DAC]
• 2ch(stereo) DAC
• Single End output
• Digital Attenuator
• Analog Performance - S/N: 88dBA@fs= 44.1kHz [Touch Screen/Battery Check]
• SAR type A/D Converter: 12bit(10bit accuracy) - S/H circuit - 4-1 Multiplex (2ch :Touch Screen, 2ch : Check for the battery)
• Low Power Current: 20mA
• Low Voltage Operation - Analog, Digital: 3.0V
• Small Package: 48pin LQFP [General Description] The AK4533 is audio codec with touch screen controller. The AK4533 incorporates several functions into one-chip; the position detection of the touch screen, the measurement of battery voltage, the record of the voice, and the playback of audio data. The AK4533 has monaural A/D converter with AGC, and stereo D/A converter with digital attenuator. As codec can operate from 8kHz to 44.1kHz, the AK4533 can playback the sound like MP3 with high quality. On-chip digital attenuator with 1.5dB step can control DAC volume without the increase of CPU load. As AGC with 0.5dB step automatically controls voice input level to the appropriate level, the voice can be recorded clearly. As the AK4533 also has on-chip 20dB fixed gain preamplifier in addition to AGC, no other external preamplifier for microphone is required. The AK4533 controls the voltages which are supplied to two pairs of electrode of touch screen. As the AK4533 also has 12bit/100kHz sampling SAR type A/D converter, it is possible to detect the pressed location by two A/D conversions. 12 bit digital code is output through serial interface. The AK4533 also has 2 analog channels as the input of Touch Screen A/D converter. The main purpose is for the measurement of the battery voltage. As the AK4533 is small package, and can operate from 2.7V with low power consumption, it is suitable for mobile products, especially PDA. Audio Codec with Touch Screen ControllerAK4533

[ASAHI KASEI] <Revision 0.9a> July 00 MICIN 16bit ADC 16bit DAC Audio I/F DATT Touch Panel I/F SCLK LRCK SDI SDO LOUT ROUT TSX_TOP BTI_1 VA AGND 12bit ADC RESETB VD DGND VCOM VCOMAD +20dB AGC (IPGA) TADCK TADOUT INT TSX_BTM TSY_TOP TSY_BTM CS CDTI CCLK Audio & Panel Control Registers TADRDY MCLK PDB CDTO TADE MICOUT AIN AFILT TPVREFIN Touch Panel Control BTI_2 VREF Control PW BLOCK DIAGRAM

[ASAHI KASEI] <Revision 0.9a> July 00 „Pin Configuration 37NC TSX_TOP VA2 TSX_BTM AGND2 TSY_TOP TSY_BTM 43 INT TADRDY TADOUT TADCK NC BTI_1 TPVREFIN MICIN MICOUT AIN AFILT VCOMAD VCOM AGND1 VA1 NC BTI_2NC 2TADE 3CS 4CCLK 5CDTI 6CDTO VD SDO SCLK LRCK 11 12 DGND NC

24 ROUT

18 TST1

17 TST0

16 PDB

15 RESETB

14 MCLK

13 SDI

36 35 25262728293031323334

[ASAHI KASEI] <Revision 0.9a> July 00 PIN/FUNCTION No. Signal Name I/O Description Power Supply

7 DGND - Digital Ground

8 VD - Digital Power Supply : +3V

21 VB - Power Supply(Bulk) : +3V

26 VA1 - Analog Power Supply : +3V

27 AGND1 - Analog Ground

40 VA2 - Analog Power Supply : +3V

41 AGND2 - Analog Ground

15 RESETB I Reset Pin

The device is powered down except for VCOM when this pin is “L”. All registers are cleared and are set to default values.

16 PDB I Power down Pin

All blocks including VCOM are powered down when this pin is set to “L”. Audio CODEC

9 SDO O Audio ADC Serial Data Output

10 SCLK O Audio data Serial Output/Input Clock : 32fs

The device outputs ADC data through SDO pin at the falling edge of SCLK clock. The device latches DAC (input) data through SDI pin at the rising edge of SCLK clock.

11 LRCK O Left/Right channel Select Clock, 1fs

H: Left channel, L: Right channel When both of ADC block and DAC block go into power-down mode, this pin outputs “L”. Either of block is active, the device outputs LRCK clock.

13 SDI I Audio DAC Serial Data Input

14 MCLK I Master Clock Input

256fs or 512fs, which is selected by MSEL bit in the Control Register, master clock is input to this pin.

23 LOUT O DAC Left Channel Analog Output

Note) Load resistance must be greater than 10KΩ . Load capacitance must be less than 50pF.

24 ROUT O DAC Right channel Analog Output

Note) Load resistance must be greater than 10KΩ . Load capacitance must be less than 50pF.

28 VCOM O Analog Common Voltage Output

Reference voltage of all analog circuit block (VA/2) Connect 4.7uF and 0.1uF capacitors

29 VCOMAD O Analog Common Voltage Output for ADC

Reference voltage of ADC block Connect 4.7uF and 0.1uF capacitors

30 AFILT I Anti aliasing Filter for A/D Input

Connect 1nF capacitor.

31 AIN I Analog Input

Input inverting analog signal which is output from MICOUT pin 1uF capacitor is connected between MICOUT pin and AIN pin.

32 MICOUT O Microphone Analog Output

Output inverting analog signal with 20dB gain of MICIN signal.

33 MICIN I Microphone Analog Input

Input analog signal from microphone

[ASAHI KASEI] <Revision 0.9a> July 00 No. Signal Name I/O Description Audio & Touch Panel Control I/F

3 CS I Control Data Chip Select

When read/write Touch Screen/Audio Control Data, set CS pin to “H”. Read/Write operation requires 16 CCLK cycles. CS pin must be set to “L” once per one Read/Write operation.

4 CCLK I Audio/Touch Screen Data Control Clock Input

Clock signal used for Touch Screen/Audio control I/F.

5 CDTI I Touch Screen/Audio Control Data Input

Control data is input to CDTI pin. The device latches data at the rising edge of CCLK.

6 CDTO O Touch Screen/Audio Control Data Output

Control data is output through CDTO pin. The device outputs data at the falling edge of CCLK. Touch Screen & watch Power-supply

34 TPVREFIN I Touch Screen Reference Voltage Input

The TPVREFIN voltage is referenced as full scale of Touch Screen A/D converter(TSADC) This pin should be connected to 4.7uF and 0.1uF capacitors. Note that maximum voltage is VA.

35 BTI_1 I Battery level check Input_1

Note that maximum voltage is VA.

36 BTI_2 I Battery level check Input_2

Note that maximum voltage is VA.

38 TSX_TOP I/O Touch Screen X_ TOP plate Voltage supply

„Measurement of the position on X axis: This pin supplies the voltage to the top side of the touch screen(normal mode -> VA, reverse mode -> AGND) „ Measurement of the position on Y axis: The Input to Touch Screen A/D converter(TSADC) „Powerdown Mode : OPEN „Pen Waiting Mode: OPEN

39 TSX_BTM I/O Touch Screen X_ BOTTOM plate Voltage supply

„Measurement of the position on X axis: This pin supplies the voltage to the bottom side of the touch screen(normal mode -> AGND, reverse mode -> VA) „ Measurement of the position on Y axis: OPEN „Powerdown Mode : OPEN „ Pen Waiting Mode: This pin is connected to AGND through the resister.

42 TSY_TOP I/O Touch Screen Y_ TOP plate Voltage supply

„Measurement of the position on Y axis: This pin supplies the voltage to the top side of the touch screen(normal mode -> VA, reverse mode -> AGND) „ Measurement of the position on X axis: The Input to Touch Screen A/D converter(TSADC) „Powerdown Mode : OPEN „Pen Waiting Mode: OPEN

43 TSY_BTM I/O Touch Screen Y_ BOTTOM plate Voltage supply

„Measurement of the position on Y axis: This pin supplies the voltage to the bottom side of the touch screen(normal mode -> AGND, reverse mode -> VA) „ Measurement of the position on X axis: OPEN „Powerdown Mode : OPEN „ Pen Waiting Mode: Supplies VA.

[ASAHI KASEI] <Revision 0.9a> July 00 No. Signal Name I/O Description

2 TADE I Touch Panel A/D Data Chip Enable Pin

This pin enables the output of Touch Screen A/D converter when it goes to “H”. ADC starts tracking at the rising edge. A/D Conversion and the output require 16 TADCK clock cycles. This pin should be set to “L” once per one A/D conversion.

45 INT O Interrupt

This pin is “H” ONLY when the touch screen is pressed. In other cases, the pin is “L”.

46 TADRDY O Touch Screen A/D data Output Ready

When Touch Screen A/D converter is ready to output data, TADRDY pin goes to “H”. This pin goes back to “L” after 12 bit data is output.

47 TADOUT O Touch Screen A/D Data Output

MSB of A/D data is output at the rising edge of TADRDY is “H”. Other bits of data are output at the falling edge of TADCK clock

48 TADCK I Touch Panel ADC Clock

This clock is used for A/D conversion and for the output of data One A/D conversion needs 16 TADCK clock cycle. Miscellaneous

17 TST0 - Test pin 0

Should be Connected to DGND.

18 TST1 - Test pin 1

Should be Connected to DGND.

19 TST2 - Test pin 2

Should be Connected to DGND.

20 TST3 - Test pin 3

Should be Connected to DGND.

1 NC - Non Connection

12 NC - Non Connection

22 NC - Non Connection

25 NC - Non Connection

37 NC - Non Connection

44 NC - Non Connection

[ASAHI KASEI] <Revision 0.9a> July 00 ABSOLUTE MAXIMUM RATINGS AGND, DGND=0V Parameter Symbol Min max Units Power Supplies Analog Digital VA VD -0.3 -0.3 6.0 6.0(VA+0.3) V V Input Current (any pins except for supplies) IIN - ±10 mA Analog Input Voltage Note2) VINA -0.3 6.0(VA+0.3) V Digital Input Voltage Note2) VIND -0.3 6.0(VA+0.3) V Touch Panel Drive Current IOUTDRV 50 mA Ambient Temperature Ta -10 70 °C All voltages with respect to ground. RECOMMENDED OPERATING CONDITIONS AGND, DGND=0V Parameter Symbol min typ max Units Power Supplies Analog Digital VA VD 2.7 2.7 3.0 3.0 3.63 VA V V All voltages with respect to ground.

[ASAHI KASEI] <Revision 0.9a> July 00 ANALOG CHARACTERISTICS Ta=25°C, AVdd=DVdd=3.0V, signal=1kHz, Sampling Frequency : Fs=44.1kHz Measurement frequency=20 ∼ 20kHz unless otherwise specified Parameter min typ Max Units Mono(1ch) ADC Resolution 16 Bits S/N (A weighting) @ MIC gain=20dB, IPGA=0dB 82 dBA S/(N+D) @ MIC gain=20dB, IPGA=0dB, Ain= - 1dBFS 77 dB Input voltage Range @ MIC gain=20dB, IPGA=0dB 0.06*VA Vp-p MIC Amplifier Input Impedance 30 k: Gain(Fixed) 20 dB AGC(IPGA) Step Size 0.5 dB Gain Control Range -8 27.5 dB Stereo(2ch)DAC: Resolution 16 Bits S/N (A weighting) @fs=44.1kHz, Fin=1kHz, noise band=20kHz, 256fs_mode ( Reference ) @fs=8kHz, fin=1kHz, noise band=20kHz, 512fs_mode dBA dBA S/(N+D) @fs=44.1kHz, Fin=1kHz, noise band=20kHz, 256fs_mode 84 dB Output Voltage 0.6*VA Vp-p Voltage Reference (Audio) VCOM,VCOMAD 0.5*VA V ADC for Touch Panel Resolution 12 Bits Integral Linearity Error @100kHz @ External Rin=500Ω , FS=3V(TP mode)

1.5 LSB

Differential Linearity Error @100kHz @ External Rin=500Ω , FS=3V(TP mode) 1L S B Touch Panel Driver (ADC mode) ON- Resistance (Top side) @VA=3V, RL=300Ω ON- Resistance (Bottom side) @VA=3V, RL=300Ω ( Reference ) Drive Current @VA=3V, RL=300Ω Ω Ω mA Touch Panel Driver (Pen waiting State) Pull down Resistance for TSX_Bottom 20 kΩ TPVREFIN (VRIN) 2.5 VA V Power Supply Current (VA+VD) Total Power ON (exclude TP_Drive current) Audio ADC + GAMP +IPGA (exclude VCOM) Audio DAC (2channel) (exclude VCOM) Touch Panel ADC (exclude TP_Drive current, VCOM) VCOM (RESTB=L) Touch Panel Driver Current @VA=3V, RL=300Ω 1.2 0.37 mA mA mA mA mA mA Full Power Down (PDB=L) 3 uA

[ASAHI KASEI] <Revision 0.9a> July 00 FILTER CHARACTERISTICS Ta=25°C,AVdd=DVdd=3.0V, Signal=1kHz, fs=44.1kHz Parameter Symbol min Typ max Units ADC Digital Filter (LPF) Pass band r0.2dB PB 0 17.64 kHz Stop band SB 26.46 2795.94 kHz Stop band Attenuation SA 70 dB Absolute Delay (Note 1) 16.1 1/fs ADC Digital Filter (HPF) Frequency Response -3dB -0.5dB -0.1dB FR 6.89 19.3 45.0 Hz Hz Hz DAC Digital Filter Pass band r0.2dB PB 0 17.64 kHz Stop band SB 26.46 326.34 kHz Stop band Attenuation SA 70 dB Absolute Delay (No te 1) 14.8 1/fs DAC Digital Filter + Analog Filter Frequency Response 0 ∼ 17.64kHz FR ±1.0 dB Note 1: Absolute delay time caused by digital filter only (not including analog delta sigma, digital delta sigma, and analog post filter.) ADC DF: to the LRCK rising edge before data is output. DAC DF: from the next LRCK rising edge after both channel data is set. DC CHARACTERISTICS (Logic I/O) Ta=25°C,VA=VD=3.0V Parameter Symbol min Typ max Units “H” level input voltage VIH 0.7xVD V “L” level input voltage VIL - 0.3xVD V “H” level output voltage (@ Iout = -400uA) VOH VD-0.4 - V “L” level output voltage (@ Iout= 400uA) VOL - - 0.4 V

[ASAHI KASEI] <Revision 0.9a> July 00 SWITCHING CHARACHTERISTICS Ta= -10°C ∼ 70°C, AVdd=DVdd=2.7V ∼ 3.63V, CL=20pF Parameter Symbol min Typ max Units Audio Master Clock Timing MCLK_SEL=”L” (512fs mode) MCLK_SEL=”H” (256fs mode) Pulse Width duty fMCLK fMCLK duty_MCLK 4.096 5.6448 40 50 11.2896 11.2896 MHz MHz LRCK Frequency MCLK_SEL=”L” (fMCLK/512) MCLK_SEL=”H” (fMCLK/256) LRCK duty fs duty_LRCK 22.05 -5 0 22.05 44.1 kHz kHz Serial Interface Timing SCLK Frequency SCLK duty SDI Hold Time after “SCLK rising” SDI Setup Time for “SCLK rising” SDO(MSB) delay from “LRCK rising” SDO delay from “SCLK falling” LRCK change to “SCLK falling” fSCLK duty_SCLK tSD_H tSD_S tLR_SDO tSC_SDO tLR_SCF 100 100 -40 150 150 fs ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low CCLK Pulse Width High CDTI Hold Time after “CCLK rising” CDTI Setup Time for “CCLK rising” CS Low Level Time (for next command) “CS rising” to “CCLK rising” time “CCLK falling” to “CS falling” time CDTO delay from “CCLK falling” 16CCLK ↓ to CDTO =“L” tCCK tCCKL tCCKH tCDH tCDS tCSW tCSS tCSH tDCD tCCL 500 200 200 100 100 200 200 0(TBD) 2000 100 100 ns ns ns ns ns ns ns ns ns ns Touch Panel (A/D Converter) Conversion Rate 125 kHz TADCK frequency duty fTADCK duty_TADCK 0.1 45 50 MHz TADE “H” Level Period Setup Time for “TADCLK rising” Hold Time after “TADCLK rising” “L” Level Time for next Conversion tTADES tTADEH tTADE_LW 225 225 200 cycle ns ns ns Tracking Time tTRK 1.5 us TADOUT delay time from TADCLK ↓ tTADD 150 ns TADRDY “H” Level Period TADCK ↓ to TADRDY change tRDYD -1 2- cycle ns Others PDB Low Pulse Width RESETB Low Pulse Width Input signal Rise/fall time (VIL to VIH) (CS,CCLK,TADE,TADCK, MCLK) tPDB tRESETB 200 200 ns ns ns

[ASAHI KASEI] <Revision 0.9a> July 00 Overview The AK4533 consists of three blocks; Audio A/D Converter, Audio D/A Converter, and Touch Screen A/D Converter. These blocks operate independently. The following describes the overview of the device. (1) 1 channel 16 bit audio A/D converter: „ 64fs oversampling ∆-Σ type „ On-chip decimation LPF and digital HPF „ Audio Format: 2's complement, MSB first, serial output „ Fixed Gain Amplifier for microphone input: +20dB „ Input Programmable Gain Amplifier (IPGA) with automatic gain control (AGC) function -8dB to +20dB, 0.5dB/step „ Input signal range of ADC scales with the supply voltage: 0.6 x VA (excluding fixed gain amplifier) „ Power down control independent with DAC block and Touch panel block (2) 2 channel 16 bit audio D/A converter: „ 128fs/256fs oversampling ∆-Σ type „ 8 times interpolation digital filter „ 2nd order SCF: single-ended „ Audio format: 2's complement, MSB first, serial input „ Digital ATT: 0dB to -22.5dB, 1.5dB/step „ Output signal range of DAC scales with the supply voltage: 0.6 x VA „ Power down control independent with L channel and R channel (3) 1ch 12bit A/D converter for Touch Screen and Battery Measurement „ 12bit Resolution, Successive Approximation Resistor (SAR) type „ Two pairs of touch screen driver: X-axis and Y-axis - Measurement of X-axis position: TSY_TOP pin is automatically selected. - Measurement of Y-axis position: TSX_TOP pin is automatically selected. „ Power Down Mode - A/D converter goes to power down state - Touch Screen Driver is open state. „ Waiting State for Pen Interrupt - TSY_BTM is connected to VA, and TSY_TOP is open state - TSX_TOP is open state, and TSX_BTM is connected to AGND through internal resistor. When the touch screen is pressed, the device outputs INT signal. „ Measurement of Battery Voltage - 2ch BTI inputs - Full scale of BTI input is TPVREFIN (4) Control Registers „ 4-wire I/F: 8bit/word, 8words „ The registers are set to default value by RESETB pin ("L" level) „ This interface is used for IPGA (AGC), PD control, mode selection of Touch Screen (5) Pin Control „ PDB pin - When PDB pin is "L", all blocks in the device including VCOM buffer goes to power-down state. - Internal registers are set to default value. - ADC for Touch Screen is power-down state (Pen Interrupt function is disabled). - All digital output pins is "L". - When PDB pin goes to "H", power-down state is cleared, and the device is ready to normal operation. - VCOM buffer start to operation after exiting power-down state. - It takes time for VCOM to settle the appropriate voltage through external capacitor. (4ms@4.7uF) „ RESETB pin - All blocks in the device except for VCOM Buffer is power-down state when RESETB pin is "L". - When RESETB pin is "L", internal registers are set to default value. - ADC for Touch Screen is power-down state (Pen Interrupt function is disabled). - All digital output pin is "L", and A/T I/F is NOT available when RESETB is "L".

Figure 10. AK4533 Three Interfaces

Audio data is transported by the control of 5-wire; MCLK, SCLK, LRCK, SDO, and SDI. to "1", which select 256fs mode. LRCK are fixed to "L" level. is "L" while LRCK is "L". As A/D data is output at the falling edge of SCLK, A/D data should be latched at the rising edge of SCLK. 2's complement, 16 bit, and MSB first. Figure 11. Audio Streaming Data Timing Table 1 shows the relationship between Sampling frequency (fs) and master clock frequency. Table 1. The relationship between sampling frequency and master clock frequency

address bits, and eight control bits. Data format is MSB first. A/T interface is enabled by the CS pin = "H". In this mode, internal registers may be either written to or read from 4-wire uP interface. should be "L" once after the write cycle terminates. of 16th falling edge of CCLK. CS pin should be "L" once after the write cycle terminates. CCLK, CS, and CDTI should be "L" while the device is idle state. CDTO is "L" under idle state. Figure 12. Audio/Touch Screen Control Interface Timing

Note that MCLK should be present when a register is accessed.

00 AGC Control A G C XXXXX T H 1 T H 0 03

01 Limit/Recovery Control LSTEP1 LSTEP0 X X RSTEP1 RSTEP0 RWT1 RWT0 01

02 IPGA Control X IPGA6 IPGA5 IPGA4 IPGA3 IPGA2 IPGA1 IPGA0 10

03 Recovery Reference Level X REF6 REF5 REF4 REF3 REF2 REF1 REF0 36

04 DATT Control Mute X X X M3 M2 M1 M0 00

05 Audio Powerdown &

06 Reserve XXXXXXXX 00

07 Touch Screen Control TSPD PW X X D3 D2 D1 D0 80

Table 2. The AK4533 Register Map is "0". When AGC bit is set to "1", AGC function is activated. value is not the same as the value that was stored at the start of AGC operation. The write operation to 02h register is ignored. AGC operation automatically after the end of the period.

that is specified by LSTEP0 bit and LSTEP1 bit to suppress the signal. Recovery Counter is cleared. Reference level of Limit Zone and Recovery Zone can be changed by the combination of TH0 bit and TH1 bit as Table 3. Table 3. Setting of Limit/Recovery Zone once, the AK4533 forces to decrease IPGA value after the specified timeout passes. Table 4. Zero-Cross Timeout Table for Limit Operation. IPGA is 0x46, and if LSTEP0 and LSTEP1 are "11", IPGA is updated to 0x42.

updating of IPGA. After that, the AK4533 updates IPGA per one Recovery Time at zero-crossing point. If the signal doesn't cross the ground, the AK4533 forces to update IPGA value after the time of Table 5 passes. Table 5. Zero-Cross Timeout Table for Recovery Time IPGA is 0x42, and if RSTEP0 and RSTEP1 are "11", IPGA is set to 0x46.

[ASAHI KASEI] <Revision 0.9a> July 00 Addr = 02h IPGA6-0: IPGA Control When AGC bit is set to "0", IPGA value can be changed by the write operation to this register via A/T I/F directly. When AGC bit is set to "1", The write to IPGA register is ignored. The AK4533 outputs updated value when the read operation is processed. IPGA6-0 DATA (HEX) GAIN (dB) STEP 47 27.5 46 27.0 45 26.5 44 26.0 43 25.5 42 25.0 Default 10 0.0 : : 0.5dB 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8 Addr = 03h REF6-0: Recovery Reference Level This value specifies the upper reference level of Recovery Operation when AGC is activated. IPGA value is forced to set the same value as Recovery Reference Level when IPGA tries to exceed Recovery Reference Level under Recovery Operation. Therefore, IPGA is not greater than Recovery Reference Level. Write the appropriate value when AGC bit is set to "0". Must NOT change this value while AGC is active. REF6-0 DATA (HEX) Reference Level (dB) STEP 47 27.5 46 27.0 45 26.5 default 36 19.0 : : 0.5dB 10 0.0 06 -5.0 05 -5.5 04 -6.0 03 -6.5 02 -7.0 01 -7.5 00 -8

[ASAHI KASEI] <Revision 0.9a> July 00 MCLK Control Master Clock frequency for audio codec is input to MCLK pin. If sampling frequency is equal to or less than 22.05kHz, MSEL bit should be set to "0", requiring 512fs clock as MCLK pin. If sampling frequency is more than 22.05kHz, MSEL bit should be "1", requiring 256fs clock as MCLK pin. When MSEL bit is changed, MSEL bit must be written with all "1" of ADPD bit, DALPD bit and DARPD bit (power-down state). In addition to this, master clock, MCLK should be stopped. MSEL: Selection of 256/512fs “0”: 512fs Default “1”: 256fs Power-down Control ADPD, DALPD, and DARPD can control power-down state of ADC and DAC. The AK4533 can power down Left channel of DAC and Right channel DAC independently. ADPD: A/D Converter Power-down Enable (0: Disable 1: Enable) The write "1" to ADPD bit enables IPGA block and ADC to power down, and 00h - 03h registers are reset to default value. The AK4533 ignores the write operation to 00h -03h registers. The read operation is possible (The AK4533 outputs default value) The write "0" to ADPD bit enables normal operation of ADC block. The period (516Ts@ MSEL="1", 260Ts@ MSEL="0" is required until VREFAD is stable. The write to the registers is possible in this initial period, but AGC function is disabled for this period. The AK4533 initiates AGC operation automatically after the end of the period. DALPD: Left Channel D/A Converter Power-down Enable (0: Disable 1: Enable) The write "1" to DALPD bit enables Left Channel D/A converter to power down. DALPD bit is set to "0", Left Channel of D/A converter goes to normal state. DARPD: Right Channel D/A Converter Power-down Enable (0: Disable 1: Enable) The write "1" to DARPD bit enables Right Channel D/A converter to power down. DARPD bit is set to "0", Right Channel of D/A converter goes to normal state.

from abnormal operation of internal dynamic logic. Clock should be stopped after power-down state. power-down mode. In order to activate ADC and/or DAC, write DALPD bit, DARPD bit and/or ADPD bit to "0" through A/T I/F. Note that MCLK must be present when ADC and/or DAC is under normal operation. MCLK can be stopped after RESETB = "L" or all of ADPD, DALPD, and DARPD are set to "1". Figure 14. Power-up Timing (1)

[ASAHI KASEI] <Revision 0.9a> July 00 Parameter Symbol min Typ max Units Audio from Power stable to PDBÇ tPDD 0 Note1) ms from PDB Ç to RESETBÇ from RESETBÈ to PDBÈ tRSTD 0 Note 2)

0 Note 2)

4 Note 3) ms

from MCLK input to 16CCLKÈ from 16CCLKÈ to LRCKÇ tMCLK tMCLK Initialize Time Note 4) A/D (MSEL=”L”) A/D (MSEL=”H”) D/A tIAD tIAD tIDA 260 516 Ts Ts Ts Power Down from 16CCLKÈ to LRCK stop (”L”) from 16CCLKÈ to SCLK Stop (”L”) from 16CCLKÈ to MCLK stop t4 0 ns ns tMCLK tMCLK= 1/fMCLK Ts=1/fs Note 1) VA, VD pins and PDB pins can be powered at the same time. However, PDB should NOT be powered before VA and VD. Otherwise, the device may be damaged, and the device may be destroyed at worst case. Note 2) PDB pin and RESETB can be set to "H" at the same time. But note that the pop noise occurs at the transition of PDB. Keeping PDB pin high is suggested for preventing pop noise while the device is powered. Power management can be controlled by RESETB pin. Note 3) The time in which VCOM settles to 95% of VDD with 4.7 µF and 0.1 µF capacitors. Note 4) ADC initialization cycle, which takes 516@ MSEL="H", or 260Ts@TSEL-"L", starts after exiting ADC's power-down mode. In this cycle, the write to the register is possible, but the device disables AGC function. The device enables AGC automatically after this initialization cycle completes. DAC initialization cycle is 2Ts.

Table 7. Touch Screen Control Register measure the x-axis spot as No.1 configuration or No.2 configuration in Table 8. AGND_R TSX_BTM is connected to AGND through internal resistor. Table 8. The relationship between input/output channel and D3:D0 bits

[ASAHI KASEI] <Revision 0.9a> July 00 TSPD Power-down Control of Touch Screen If TSPD is set to "1", Touch Screen block including ADC goes to power-down mode regardless of D3,D2,D1,and D0 bits. TSPD=”1” Power Down TSPD=”0” Normal Operation PW Waiting State for Interrupt If PW bit is set to "1", the AK4533 goes to waiting state which can notify whether the touch screen is pressed or not. If the touch screen is pressed under this state, INT signal goes to "H", and goes to "L" when the pen is released. INT pin is "L" while the screen is not pressed. If PW bit is set to "0", INT pin is "L" regardless of pressing or releasing. PW= “1” Interrupt Enable PW= “0” Interrupt Disable

Figure 19. Control Sequence of Touch Screen

screen is being touched. INT signal can notify to the external circuit that the screen is touched. Pen Interrupt. And TSX_BTM is connected to AGND through the internal resistor, Ro. "L" because this terminal is connected to AGND through Ro. touched, INT goes "H", and returned "L" when the pen is released. Figure 20. Waiting for Pen Interrupt

The voltage that is divided by the appropriate registers is input to BTI_1 pin or BTI_2 pin in order to measure battery voltage . TPVREFIN is referred to as full scale. If the impedance of input signal is high, enough tracking time is required to charge the internal capacitors through BTI_1 or B IT_2. And if the input impedance of TPVREFIN is high, clock frequency of TADCK must be low. k Ω . In this case, tracking times should be at least 50µs. If the input impedance is 30 k Ω , tracking time should be at least 100 µs. about 7.5k Ω . In this case, the clock frequency of TADCK should be 160kHz or less. conversion time can be ignored, high input impedance may be used. interrupt while the battery measurement. Figure 21. Block Diagram of Battery Measurement

Figure 22. The relationship between BIT_1/2 input impedance and tracking time

[ASAHI KASEI] [AK4533] <Rev. 0.8> - 37 - March 00 Package 1 12 48 13 7.0 9.0 ± 0.2 7.0 9.0 ± 0.2 0.19 ± 0.05 48pin LQFP(Unit:mm) 0.10 37 24 2536 0.17 ± 0.05 1.4TYP 0.10 ± 0.07 1.70Max 0° ∼ 10° 0.10 M 0.5 ± 0.2 0.5

[ASAHI KASEI] [AK4533] <Rev. 0.8> - 38 - March 00 Marking AK4533VQ XXXXXXX J A P A N 1) Pin #1 indication 2) Date Code: XXXXXXX (7 digits) 3) Marking Code: AK4533VQ 4) Country of Origin 5) Asahi Kasei Logo

[ASAHI KASEI] [AK4533] <Rev. 0.8> - 39 - March 00 IMPORTANT NOTICE

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