AK4524VF

AK4524_04 AKM | Alldatasheet

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ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 1 - GENERAL DESCRIPTION The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF (switched capacitor filter) techniques. The AK4524 has an input PGA and is well-suited MD, DVTR system and musical instruments.

FEATURES

• 24bit 2ch ADC - 64x Oversampling - Single-End Inputs - S/(N+D): 90dB - Dynamic Range, S/N: 100dB - Digital HPF for offset cancellation - Input PGA with +18dB gain & 0.5dB step - Input DATT with -72dB att - I/F format: MSB justified or I
• 24bit 2ch DAC - 128x Oversampling - 24bit 8 times Digital Filter Ripple: ±0.005dB, Attenuation: 75dB - S C F - Differential Outputs - S/(N+D): 94dB - Dynamic Range, S/N: 110dB - De-emphasis for 32kHz, 44.1kHz, 48kHz sampling - Output DATT with -72dB att - Soft Mute - I/F format: MSB justified, LSB justified or I
• High Jitter Tolerance
• 3-wire Serial Interface for Volume Control
• Master Clock - X’tal Oscillating Circuit - 256fs/384fs/512fs/768fs/1024fs
• Master Mode/Slave Mode
• 5V operation
• 3V Power Supply Pin for 3V I/F
• Small 28pin VSOP package 24Bit 96kHz Audio CODEC AK4524

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 2 - „ Block Diagram AINL AINR VCOM AOUTL+ AOUTL- AOUTR- AOUTR+ VREF VA AGND CS CCLK CDTI CIF CLKO XTO XTI XTALE SDTI SDTO BICK LRCK DGND VT VD ADC DAC HPF DATT DATT SMUTE Audio I/F Controller Control Register I/F Clock Gen. & Divider PD M/ S Block Diagram

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 3 - „ Ordering Guide AK4524VF −20 ∼ +85°C 28pin VSOP (0.65mm pitch) AKD4524 Evaluation Board „ Pin Layout (Internal pull down) TEST VCOM AINR AINL VREF AGND VA XTO XTI XTALE LRCK BICK SDTO SDTI CDTI CCLK CS CIF CLKO VT VD DGND AOUTL- AOUTL+ AOUTR- AOUTR+ PD M/ S 14 15 AK4524 Top View

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 4 - PIN/FUNCTION No. Pin Name I/O Function

1 VCOM O Common Voltage Output Pin, VA/2

Bias voltage of ADC inputs and DAC outputs.

2 AINR I Rch Analog Input Pin

3 AINL I Lch Analog Input Pin

4 VREF I

Voltage Reference Input Pin, VA Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered VA.

5 AGND - Analog Ground Pin

6 VA - Analog Power Supply Pin, 4.75 ∼ 5.25V

7 TEST I Test Pin (Internal pull-down pin)

8 XTO O X’tal Output Pin

9 XTI I X’tal/Master Clock Input Pin

10 XTALE I X’tal Osc Enable Pin

“H”: Enable, “L”: Disable

11 LRCK I/O Input/Output Channel Clock Pin

12 BICK I/O Audio Serial Data Clock Pin

13 SDTO O Audio Serial Data Output Pin

14 SDTI I Audio Serial Data Input Pin

15 CDTI I Control Data Input Pin

16 CCLK I Control Data Clock Pin

17 CS I Chip Select Pin

18 CIF I Control Data I/F Format Pin

“H”: CS falling trigger, “L”: CS rising trigger

19 PD I Power-Down Mode Pin

“H”: Power up, “L”: Power down, reset and initialize the control register.

20 M/ S I Master/Slave Mode Pin

“H”: Master mode, “L”: Slave mode

21 CLKO O Master Clock Output Pin

22 VT - Output Buffer Power Supply Pin, 2.7 ∼ 5.25V 23 VD - Digital Power Supply Pin, 4.75 ∼ 5.25V

24 DGND - Digital Ground Pin

25 AOUTL − O Lch Negative Analog Output Pin

26 AOUTL+ O Lch Positive Analog Output Pin

27 AOUTR − O Rch Negative Analog Output Pin

28 AOUTR+ O Rch Positive Analog Output Pin

Note: All input pins except pull-down pins should not be left floating.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 5 - ABSOLUTE MAXIMUM RATINGS (AGND, DGND=0V; Note 1) Parameter Symbol min max Units Power Supplies: Analog Digital Output Buffer VD−VA VA VD VT VDA −0.3 −0.3 −0.3 6.0 6.0 6.0 0.3 V V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage VINA −0.3 VA+0.3 V Digital Input Voltage VIND −0.3 VA+0.3 V Ambient Temperature (powered applied) Ta −20 85 °C Storage Temperature Tstg −65 150 °C Note: 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AGND, DGND=0V; Note 1) Parameter Symbol min typ max Units Power Supplies (Note 2) Analog Digital Output Buffer VA VD VT 4.75 4.75 2.7 5.0 5.0 3.0 5.25 VA VD V V V Voltage Reference VREF 3.0 - VA V Note: 1. All voltages with respect to ground. 2. VA and VD should be powered at the same time or VA should be powered earlier than VD. The power up sequence between VA and VT, or VD and VT is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 6 - ANALOG CHARACTERISTICS (Ta=25°C; VA, VD, VT=5.0V; AGND=DGND=0V; VREF=VA; fs=44.1kHz; Signal Frequency=1kHz; 24bit Data; Measurement frequency = 10Hz ∼ 20kHz at fs=44.1kHz, 10Hz ∼ 40kHz at fs=96kHz; unless otherwise specified) Parameter min typ max Units Input PGA Characteristics: Input Voltage (Note 3) 2.7 2.9 3.1 Vpp Input Resistance 5 10 15 k Ω Step Size 0.2 0.5 0.8 dB Gain Control Range 0 18 dB ADC Analog Input Characteristics: IPGA=0dB Resolution 24 Bits S/(N+D) (−0.5dBFS) fs=44.1kHz fs=96kHz dB dB DR (−60dBFS) fs=44.1kHz, A-weighted fs=96kHz 100 dB dB S/N fs=44.1kHz, A-weighted fs=96kHz 100 dB dB Interchannel Isolation 90 105 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 - ppm/ °C Power Supply Rejection (Note 4) 50 - dB DAC Analog Output Characteristics: Resolution 24 Bits S/(N+D) (0dBFS) fs=44.1kHz fs=96kHz dB dB DR (−60dBFS) fs=44.1kHz, A-weighted fs=96kHz 104 110 104 dB dB S/N fs=44.1kHz, A-weighted fs=96kHz 104 110 104 dB dB Interchannel Isolation 100 110 dB Interchannel Gain Mismatch 0.2 0.5 dB Gain Drift 20 - ppm/ °C Output Voltage (Note 5) 5.0 5.4 5.8 Vpp Load Resistance (In case of AC load) 1 k Ω Output Current (In case of AC load) 1.5 mA Load Capacitance 25 pF Note: 3. Full scale (0dB) of the input voltage at PGA=0dB. This voltage is proportional to VREF. Vin=0.58 x VREF. 4. PSR is applied to VA, VD, VT with 1kHz, 50mVpp. VREF pin is held a constant voltage. 5. Full scale (0dB) of the output voltage when summing the differential outputs, AOUT+/ − by unity gain. This voltage is proportional to VREF. Vout=1.08 x VREF x Gain.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 7 - Parameter min typ max Units Power Supplies Power Supply Current Normal Operation ( PD = “H”) VA VD+VT (fs=44.1kHz) (fs=96kHz) Power-down mode ( PD = “L”) (Note 6) VA VD+VT 100 100 mA mA mA µA µA Note: 6. XTALE=“L” and all digital input pins are held VD or DGND. FILTER CHARACTERISTICS Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 7) −0.005dB −0.02dB −0.06dB −6.0dB PB 20.02 20.20 22.05 19.76 kHz kHz kHz kHz Stopband SB 24.34 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 8) GD 31 1/fs Group Delay Distortion ∆GD 0 µs ADC Digital Filter (HPF): Frequency Response (Note 7) −3dB −0.5dB −0.1dB FR 0.9 2.7 6.0 Hz Hz Hz DAC Digital Filter: Passband (Note 7) −0.01dB −6.0dB PB 22.05 20.0 kHz kHz Stopband SB 24.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 75 dB Group Delay (Note 8) GD 30 1/fs DAC Digital Filter + SCF: Frequency Response: 0 ∼ 20.0kHz ∼ 40kHz (Note 9) FR ±0.2 ±0.3 dB dB The reference frequency of these responses is 1kHz. 8. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to setting the 24bit data of both channels to the output register for ADC. For DAC, this time is from setting the 24bit data of both channels on input register to the output of analog signal. 9. fs=96kHz.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 8 - DIGITAL CHARACTERISTICS Parameter Symbol min typ Max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V High-Level Output Voltage (Iout=−100µA) (Note 10) Low-Level Output Voltage (Iout=100µA) VOH VOL 2.7 / VT−0.5 0.5 V V Input Leakage Current Iin - - ±10 µA Note: 10. Min value is lower voltage of 2.7V or VT−0.5V. SWITCHING CHARACTERISTICS (Ta=25°C; VA, VD=4.75 ∼ 5.25V, VT=2.7 ∼ 5.25V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency 11.2896 24.576 MHz External Clock Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 49.152 MHz ns ns CLKO Output (X’tal mode) Frequency Duty Cycle fMCK dMCK 11.2896 24.576 MHz LRCK Frequency Normal Speed Mode (DFS0=“0”, DFS1=“0”) Double Speed Mode (DFS0=“1”, DFS1=“0”) Quad Speed Mode (DFS0=“0”, DFS1=“1”) fsn fsd fsq 128 192 kHz kHz kHz Duty Cycle Slave mode Master mode Audio Interface Timing Slave mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I2S mode) BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tSDH tSDS ns ns ns ns ns ns ns ns ns Master mode BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO SDTI Hold Time SDTI Setup Time fBCK dBCK tMBLR tBSD tSDH tSDS -20 -20 64fs Hz ns ns ns ns Note 11. BICK rising edge must not occur at the same time as LRCK edge.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 9 - Parameter Symbol min typ max Units Control Interface Timing CIF=“0” CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CS “H” Time CS “L” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSW tCSS tCSH 200 150 150 150 ns ns ns ns ns ns ns ns ns CIF=“1” CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CS “H” Time CS “L” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSW tCSS tCSH 200 150 150 150 ns ns ns ns ns ns ns ns ns Reset Timing PD Pulse Width (Note 12) RSTAD “↑” to SDTO valid (Note 13) tPD tPDV 150 516 ns 1/fs Note: 12. The AK4524 can be reset by bringing PD “L”. 13. These cycles are the number of LRCK rising from RSTAD bit.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 10 - „ Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL 1/fs LRCK VIH VIL tBCK tBCKL VIH tBCKH BICK VIL tL 50%VT tH CLKO dMCK=tH/(tH+tL) or tL/(tH+tL) Clock Timing LRCK BICK SDTO SDTI tBLR tLRB tLRS tBSD tSDS tSDH VIH VIL VIH VIL 50%VT VIH VIL Audio Interface Timing (Slave mode)

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 11 - LRCK BICK SDTO SDTI tMBLR tBSD tSDS tSDH 50%VT VIH VIL 50%VT 50%VT Audio Interface Timing (Master mode) CS(CIF=H) CS(CIF=L) CCLK CDTI VIH VIL tCSS tCCKL tCCKH tCDS tCDH C1 C0 R/W A4 VIH VIL VIH VIL VIH VIL WRITE Command Input Timing CS(CIF=H) CS(CIF=L) CCLK CDTI tCSW tCSH VIH VIL D3 D2 D1 D0 VIH VIL VIH VIL VIH VIL WRITE Data Input Timing tPD VILPD Power Down & Reset Timing

CLKO output is not used externally, it should be disabled. When using a crystal oscillator, external loading capacitors (between XTI/XTO and DGND) are required. Table 1. Sampling Speed Table 2. Master Clock Frequency Select

Table 3. Master clock frequency

• X’tal mode operates from 11.2896MHz to 24.576MHz.
• The frequency over 24.576MHz supports only external clock mode.

the frequency of BICK is fixed to 64fs. Table 4. Audio data format Figure 1. Mode 0 Timing

the same register address. When MSB of the register is “1”, the IPGA changes and the IATT changes at MSB “0”. enabled by ZCEI in the control register. values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise. Table 5. IPGA+ADC S/N Table 6. LRCK cycles for timeout period also scales with sampling rate (fs). transition between ATT values has 8032 levels and is done by soft changes. Therefore, there is not any switching noise.

Table 7. De-emphasis control (DFS0=DFS1=“0”) Soft mute function is independent to output volume and cascade connected between both functions. Figure 6. Soft Mute (1) The output signal is attenuated by −∞ during 1024 LRCK cycles (1024/fs). (2) Analog output corresponding to digital input has the group delay (GD). (3) If the soft mute is cancelled within 1024 LRCK cycles, the attenuation is discontinued and returned to 0dB.

also controlled by the registers (PWAD, PWDA).

• INITA: Initializing period of ADC analog section (516/fs).
• PD: Power down state. The contents of all registers are hold.
• XXH: The current value in ATT register.
• FI: Fade in. After exiting power down and reset state, ATT value fades in.
• AOUT: Some pop noise may occur at “*”.

Figure 7. Reset & Power down sequence

operation. When a crystal oscillator is used, XTALE pin is set to “H”. XTALE pin should be “L” at external clock mode. Table 8. Clock operation at slave mode (M/ S = L) Table 9. Clock operation at master mode (M/ S = H)

Chip address (2bits, C0/1) Read/Write (1bit), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). registers to their default values. Figure 8. Control I/F Timing

• READ command is not supported.

Note: For addresses from 08H to 1FH, data is not written. = “L” resets the registers to their default values.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 20 - „ Control Register Setup Sequence When PD pin goes “L” to “H” upon power-up etc., the AK4524 should operate by the next sequence. In this case, all control registers are set to initial values and the AK4524 is in the reset state. (1) Set the clock mode and the audio data interface mode. (2) Cancel the reset state by setting RSTAD or RSTDA to “1”. Refer to Reset Contorl Register (01H). (3) ADC outputs and DAC outputs should be muted externally until cancelling each reset state. In master mode, there is a possibility the frequency and duty of LRCK and BICK outputs become an abnormal state. The clock mode should be changed after setting RSTAD and RSTDA to “0”. At that time, ADC outputs and DAC outputs should be muted externally. In master mode, there is a possibility the frequency and duty of LRCK and BICK outputs become an abnormal state. „ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control 0 0 0 0 0 PWVR PWAD PWDA RESET 0 0 0 0 0 1 1 1 PWDA: DAC power down 0: Power down 1: Power up Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The analog outputs should be muted externally as some pop noise may occur when entering to and exiting from this mode. PWAD: ADC power down 0: Power down 1: Power up Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The IPGAs also go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting the power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADCs output “0” during first 516 LRCK cycles. PWVR: Vref power down 0: Power down 1: Power up All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and PWVR goes “1”, only VREF section can be powered up.

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 21 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Reset Control 0 0 0 0 0 0 RSTAD RSTDA RESET 0 0 0 0 0 0 0 0 RSTDA: DAC reset 0 : R e s e t 1: Normal Operation The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The analog outputs should be muted externally as some pop noise may occur when entering to and exiting from this mode. RSTDA: ADC reset 0 : R e s e t 1: Normal Operation The internal timing is reset by “0” and then SDTO goes “L” immediately. The IPGAs also go “00H”. But the contents of all register are not initialized and enabled to write to the register. After exiting the power down mode, the IPGAs fade in the setting value of the control register (04H & 05H). At that time, ADCs output “0” during first 516 LRCK cycles. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Clock and Format Control DIF2 DI F1 DIF0 CMODE CKS1 CKS0 DFS1 DFS0 RESET 0 1 0 0 0 0 0 0 DFS1-0: Sampling Speed Control (see Table 2) Initial: Normal speed CMODE, CKS1-0: Master Clock Frequency Select (see Table 1) Initial: 256fs DIF2-0: Audio data interface modes (see Table 4) 000: Mode 0 001: Mode 1 010: Mode 2 011: Mode 3 100: Mode 4 Initial: 24bit MSB justified for both ADC and DAC

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 22 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Deem and Volume Control SMUTE 0 0 ZCEI ZTM1 ZTM0 DEM1 DEM0 RESET 0 0 0 1 1 0 0 1 DEM1-0: De-emphasis response (see Table 7) 00: 44.1kHz 0 1 : O F F 10: 48kHz 11: 32kHz Initial: OFF ZTM1-0: Zero crossing time out period select (see Table 6) Initial: 1024fs ZCEI: ADC IPGA Zero crossing enable 0: Input PGA gain changes occur immediately 1: Input PGA gain changes occur only on zero-crossing or after timeout. Initial: 1 (Enable) SMUTE: DAC Input Soft Mute control 0: Normal operation 1: DAC outputs soft-muted The soft mute is independent of the output ATT and performed digitally. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Lch IPGA Control IPGL7 IPGL6 IP GL5 IPGL4 IPGL3 IPGL2 IPGL1 IPGL0 05H Rch IPGA Control IPGR7 IPGR6 IPGR5 IPGR4 IPGR3 IPGR2 IPGR1 IPGR0 RESET 0 1 1 1 1 1 1 1 IPGL/R7-0: ADC Input Gain Level Refer to Table 10 Initial: 7FH (0dB) Digital ATT with 128 levels operates when writing data of less than 7FH. This ATT is a linear ATT with 8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. The transition between ATT values has 8032 levels and is done by soft changes. For example, when ATT changes from 127 to 126, the internal ATT value decreases from 8031 to 7775 one by one every fs cycles. It takes 8031 cycles (182ms@fs=44.1kHz) from 127 to 0 (Mute). The IPGAs are set to “00H” when PD pin goes “L”. After returning to “H”, the IPGAs fade in the initial value, “7FH” by 8031 cycles. The IPGAs are set to “00H” when PWAD goes “0”. After returning to “1”, the IPGAs fade in the current value. But the ADCs output “0” during first 516 cycles. The IPAGs are set to “00H” when RSTAD goes “0”. After returning to “1”, the IPGAs fade in the current value. But the ADCs output “0” during first 516 cycles.

Table 10. IPGA code table

The AK4524 includes digital ATT with 128 levels equivalent to ADC’s. value, “7FH” by 8031 cycles. Figure 9. ATT characteristics

Table 11. OATT code table

Figure 11. Typical Connection Diagram (EXT clock mode)

1. Grounding and Power Supply Decoupling

from analog supply in system. Alternatively if VA and VD are supplied separately, the power up sequence is taken care. as near to the AK4524 as possible, with the small value ceramic capacitor being the nearest. avoid unwanted coupling into the AK4524.

no input signal. The DC offset including ADC own DC offset removed by the internal HPF. 64fs. The AK4524 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. for 7FFFFFH(@24bit) and a negative full scale for 800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit). the example of external op-amp circuit summing the differential outputs. Figure 12. External 2nd order LPF Example (using single supply op-amp)

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 30 - PACKAGE 1.0 0.1 ±0.1 0-10 ° Detail A Seating Plane NOTE: Dimension "*" does not include mold flash. | 0.10 A 1 14 1528 28pin VSOP (Unit: mm ) *5.6±0.2 7.6±0.2 0.5±0.2 +0.1 0.675 „ Package & Lead frame material Package molding compound: Epoxy L e a d f r a m e m a t e r i a l : C u Lead frame surface treatment: Solder plate

ASAHI KASEI [AK4524] M0050-E-03 2004/01 - 31 - MARKING AKM AK4524VF XXXBYYYYC XXXBYYYYC: Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.
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• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.
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