AK4468 AKM | Alldatasheet
Document overview
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Technical content
Features
(1) Dynamic Range, S/N: 117 dB (2) THD+N: -107 dB (3) Differential Voltage Output: 5.6 Vpp (4) 256x Over Sampling (5) Sampling Rate: 8 kHz–768 kHz (6) 32 Bit 8x Digital Filter - Ripple: ±0.0032 dB, Attenuation: 80 dB (Sharp Roll-Off Filter Setting) - Six Types of High Quality Sound Filter Option ・Sharp Roll-off ・Slow Roll-off ・Short Delay Sharp Roll-off, (GD = 5.8/fs) ・Short Delay Slow Roll-off, (GD = 4.8/fs) ・Super Slow Roll-off ・Low Dispersion Short Delay Filter (7) High Tolerance to Clock Jitter (8) Low Distortion/ Low Noise High Performance Differential Amplifier Output (9) DSD64, DSD128, DSD256, DSD512 Input Support (10) Daisy Chain (11) Digital De-emphasis for 32 kHz, 44.1 kHz and 48 kHz sampling (12) Soft Mute (13) Digital Attenuator (0 dB– -127 dB, 0.5 dB step + mute) (14) Audio I/F Format: - MSB justified - LSB justified - I2S - DSD - TDM (15) PCM/DSD Automatic Switching Function (16) 3-wire Serial and I2C μP I/F (17) Supports Pin Control Mode 117dB 768kHz 32 -bit 8ch Premium DAC AK4468
[AK4468] 019001349-E-01 2019/06 - 2 - (18) Master Clock: - fs = 7.2 kHz–32 kHz: 256 fs, 384 fs, 512 fs, 768 fs, 1152 fs - fs = 32 kHz–54 kHz: 256 fs, 384 fs, 512 fs, 768 fs - fs = 54 kHz–108 kHz: 256 fs, 384 fs - fs = 108 kHz–216 kHz: 128 fs, 192 fs - fs = 216 kHz–388 kHz: 32 fs, 48 fs, 64 fs, 96 fs - fs = 388 kHz–776 kHz: 16 fs, 32 fs, 48 fs, 64 fs (19) Digital Input Level: CMOS (20) Power Supply: by Internal LDO (LDOE pin = “H”): TVDD = 3.0–3.6 V, AVDD = 3.0–5.5 V by external supply (LDOE pin = “L”): TVDD = 1.7–3.6 V, AVDD = 3.0–5.5 V, VDD18 = 1.7–1.98 V (21) Operational Temperature: -40 to 105 C (when the Exposed Pad is connected to AVSS) (22) Package: 48-pin QFN
[AK4468] 019001349-E-01 2019/06 - 3 - Table of Contents
Figure 1. AK4468 Block Diagram
[AK4468] 019001349-E-01 2019/06 - 5 - Functions Block Function PCM Data Interface Execute serial/parallel conversion of SDTI input data by synchronizing with LRCK and BICK. DSD Data Interface 1-bit data that is input from DSDL1/2/3/4 and DSDR1/2/3/4 pins is received by synchronizing with DCLK. DSD Filter FIR filter that reduces high frequency noise of DSD input data PCM / DSD Automatic Mode Switching Switch PCM/DSD modes by detecting PCM or DSD mode according to the input signal. DATT, Soft Mute Apply DATT and Soft Mute process to input data. ΔΣ Modulator Output multi-bit data to SCF. This block consists of a third-order digital delta-sigma modulator. De-emphasis & Interpolator A digital filter that applies De-emphasis process to input data and executes over sampling. SCF A primary switched capacitor filter that converts a multi-bit output of ΔΣ modulator to an analog signal. Control Register Keep register settings for each mode. Control registers are accessed in 3- wire (CSN, CCLK, CDTI) or I2C-Bus (SCL, SDA) control mode. Clock Divider Divide Master Clock In PCM mode, master clock is divided automatically by fs rate auto detection function. In DSD mode, the master clock frequency is set by DCKS bit. MCLK Stop Detection Detects when the master clock input is absent. Bias, Vref Generate SCF reference voltage from the reference voltage (VREFH1/2/3/4, VREFL1/2/3/4) that are externally supplied. LDO Generate power for internal digital circuit (1.8 V typ.).
[AK4468] 019001349-E-01 2019/06 - 6 - Pin Configurations and Functions Pin Configurations AOUTR4P AOUTL4N VREFH4 VREFL4 AOUTR4N LDOE MCLK
3 LRCK/DSDL1
4 SDTI1/DSDR1
5 SDTI2/DSDL2
6 SDTI3/DSDR2/TDMO1
7 SDTI4/DSDL3/TDMO2
8 DSDR3
CAD0_I2C/CSN/ DIF I2C PS/CAD0_SPI AOUTL1N AOUTL1P AOUTR3N VREFL3 VREFH3 AOUTL3N AVSS AOUTR2P SDA/CDTI/TDM0 BICK/DCLK AOUTR3P AOUTL4P AOUTL3P AVDD VREFL1 DVSS TVDD VDD18
9 DSDL4
10 DSDR4
11 DZF /SMUTE
48 PDN
21 VREFH1
12 CAD1/DCHAIN
(Top View) AK4468 Input Output I/O Power The exposed pad On the back bottom surface: Note 1 Note 1. The Exposed Pad on the bottom surface of the package must be open or connected to AVSS. Do not connect this pin to other signal lines.
[AK4468] 019001349-E-01 2019/06 - 7 - Functions No . Pin Name I/O Function Power Down State
1 MCLK I External Master Clock Input Pin Hi-Z
2 BICK I Audio Serial Data Clock Pin in PCM mode Hi-Z DCLK I DSD Clock Pin in DSD mode
3 LRCK I Input Channel Clock Pin in PCM mode Hi-Z DSDL1 I Audio Serial Data Input in DSD mode
4 SDTI1 I Audio Serial Data Input in PCM mode Hi-Z DSDR1 I Audio Serial Data Input in DSD mode
5 SDTI2 I Audio Serial Data Input in PCM mode Hi-Z DSDL2 I Audio Serial Data Input in DSD mode
SDTI3 I Audio Serial Data Input in PCM mode Pull-Down to DVSS (100 kΩ) DSDR2 I Audio Serial Data Input in DSD mode TDMO1 O Audio Serial Data Output in Daisy Chain mode SDTI4 I Audio Serial Data Input in PCM mode Pull-Down to DVSS (100 kΩ) DSDL3 I Audio Serial Data Input in DSD mode TDMO2 O Audio Serial Data Output in Daisy Chain mode
8 DSDR3 I Audio Serial Data Input in DSD mode Hi-Z
9 DSDL4 I Audio Serial Data Input in DSD mode Hi-Z
10 DSDR4 I Audio Serial Data Input in DSD mode Hi-Z
DZF O Zero Input Detect in Register control mode Pull-Down to DVSS (100 kΩ) SMUTE I Soft Mute Pin in Pin control mode. When this pin is changed to “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. 12 CAD1 I Chip Address 1 Pin in Register control mode Hi-Z DCHAIN I Daisy Chain Mode select pin in Pin control mode. SDA I/O Control Data Pin in I2C-Bus Register control mode Hi-Z CDTI I Control Data Input Pin in 3-wire serial Register control mode TDM0 I TDM Mode select pin in Pin control mode. SCL I Control Data Clock Pin in I2C-Bus Register control mode Hi-Z CCLK I Control Data Clock Pin in 3-wire serial Register control mode TDM1 I TDM Mode select pin in Pin control mode. CAD0_I2C I Chip Address 0 Pin in I2C-Bus Register control mode Hi-Z CSN I Chip Select Pin in 3-wire serial Register control mode DIF I Audio Data Format Select in Pin control mode. “L”: 32-bit MSB, “H”: 32-bit I2S PS I Control Mode Select Pin (I2C pin = “H”) “L”: I2C-Bus Register control mode, “H”: Pin control mode. Hi-Z CAD0_SPI I Chip Address 0 Pin (I2C pin = “L”) In 3-wire serial Register control mode
17 I2C I
“L”: 3-wire serial Register control mode “H”: I2C-Bus Register control mode or Pin control mode. Hi-Z
18 AOUTL1P O Lch Positive Analog Output 1 Pin Hi-Z
19 AOUTL1N O Lch Negative Analog Output 1 Pin Hi-Z
20 VREFL1 I Negative Reference Voltage Input 1 Pin Hi-Z
21 VREFH1 I Positive Reference Voltage Input 1 Pin Hi-Z
22 AOUTR1N O Rch Negative Analog Output 1 Pin Hi-Z
23 AOUTR1P O Rch Positive Analog Output 1 Pin Hi-Z
24 AOUTL2P O Lch Positive Analog Output 2 Pin Hi-Z
[AK4468] 019001349-E-01 2019/06 - 8 - No. Pin Name I/O Function Power Down State
25 AOUTL2N O Lch Negative Analog Output 2 Pin Hi-Z
26 VREFL2 I Negative Reference Voltage Input 2 Pin Hi-Z
27 VREFH2 I Positive Reference Voltage Input 2 Pin Hi-Z
28 AOUTR2N O Rch Negative Analog Output 2 Pin Hi-Z
29 AOUTR2P O Rch Positive Analog Output 2 Pin Hi-Z
30 AVSS - Ground Pin -
31 AVDD - Analog Power Supply Pin, 3.0–5.5 V -
32 AOUTL3P O Lch Positive Analog Output 3 Pin Hi-Z
33 AOUTL3N O Lch Negative Analog Output 3 Pin Hi-Z
34 VREFH3 I Positive Reference Voltage Input 3 Pin Hi-Z
35 VREFL3 I Negative Reference Voltage Input 3 Pin Hi-Z
36 AOUTR3N O Rch Negative Analog Output 3 Pin Hi-Z
37 AOUTR3P O Rch Positive Analog Output 3 Pin Hi-Z
38 AOUTL4P O Lch Positive Analog Output 4 Pin Hi-Z
39 AOUTL4N O Lch Negative Analog Output 4 Pin Hi-Z
40 VREFH4 I Positive Reference Voltage Input 4 Pin Hi-Z
41 VREFL4 I Negative Reference Voltage Input 4 Pin Hi-Z
42 AOUTR4N O Rch Negative Analog Output 4 Pin Hi-Z
43 AOUTR4P O Rch Positive Analog Output 4 Pin Hi-Z
44 LDOE I Internal LDO Enable Pin. “L”: Disable, “H”: Enable Hi-Z 45 TVDD - Digital Power Supply Pin, 3.0–3.6 V -
46 DVSS - Ground Pin -
47 VDD18 O
LDO Output Pin (LDOE pin = “H”) This pin should be connected to DVSS with 1.0 µF (±50 %). This pin is prohibited from connecting with other devices. Pull-down to DVSS (500 Ω) - 1.8 V Power Input Pin (LDOE pin = “L”) Hi-Z
48 PDN I
Power-Up, Power-Down Pin When at “L”, the AK4468 is in power-down state. The AK4468 must always be in power-down state upon power on. Hi-Z (PDN = “L”) - Exposed Pad - The Exposed Pad on the bottom surface of the package must be open or connected to AVSS. Do not connect this pin to other signal lines. Note 2. All input pins except internal pull-up/down pins must not be left floating. Note 3. The AK4468 must be powered down by the PDN pin when changing the PS pin and the I2C pin settings. Note 4. DSD mode is selectable only in Register Control Mode. Daisy Chain Mode is selectable both Pin Control Mode and Register Control Mode.
[AK4468] 019001349-E-01 2019/06 - 9 - Handling of Unused Pin 5.3.1. Pin Control Mode (PCM Mode only) Classification Pin Name Setting Analog AOUTL1P/N, AOUTR1P/N AOUTL2P/N, AOUTR2P/N AOUTL3P/N, AOUTR3P/N AOUTL4P/N, AOUTR4P/N Open VREFH1/2/3/4 Connect to AVDD or AVSS VREFL1/2/3/4 Connect to AVSS Digital SDTI1/2/3/4, DSDR3/4, DSDL4 Connect to DVSS TDMO2 Open 5.3.2. Register Control Mode 5.3.2.1. PCM mode Classification Pin Name Setting Analog AOUTL1P/N, AOUTR1P/N AOUTL2P/N, AOUTR2P/N AOUTL3P/N, AOUTR3P/N AOUTL4P/N, AOUTR4P/N Open VREFH1/2/3/4 Connect to AVDD or AVSS VREFL1/2/3/4 Connect to AVSS Digital DZF Open SDTI1/2/3/4, DSDR3/4, DSDL4 Connect to DVSS TDMO2 Open 5.3.2.2. DSD mode Classification Pin Name Setting Analog AOUTL1P/N, AOUTR1P/N AOUTL2P/N, AOUTR2P/N AOUTL3P/N, AOUTR3P/N AOUTL4P/N, AOUTR4P/N Open VREFH1/2/3/4 Connect to AVDD or AVSS VREFL1/2/3/4 Connect to AVSS Digital DZF Open DSDL1/2/3/4, DSDR1/2/3/4 Connect to DVSS 5.3.3. Pull-down pin List Classification Pin Name Internal connection pull-down pin (Typ = 100 kΩ) SDTI3/4, SMUTE DVSS
[AK4468] 019001349-E-01 2019/06 - 10 - Absolute Maximum Ratings (AVSS = DVSS = 0 V; Note 5) Parameter Symbol Min. Max. Unit Power Supplies Analog AVDD 0.3 6.0 V Digital I/O TVDD 0.3 4.0 V Digital Core VDD18 0.3 2.5 V |AVSS DVSS| (Note 6) GND - 0.3 V Reference Voltage (Note 7) High VREF VREFH 1/2/3/4 AVSS0.3 AVDD+0.3 or 6.0 V Low VREF VREFL 1/2/3/4 AVSS0.3 AVSS+0.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Digital Input Voltage (Note 8) VIND 0.3 TVDD+0.3 or 4.0 V Ambient Temperature (Power applied) Exposed Pad: Connected to AVSS Ta 40 105 °C Exposed Pad: Open Ta 40 85 °C Storage Temperature Tstg 65 150 °C Note 5. All voltages are with respect to ground. Note 6. AVSS and DVSS must be connected to the same analog ground plane. Note 7. Maximum input voltage of VREFH1/2/3/4 pins is lower value between (AVDD+0.3) V and 6.0 V. Note 8. Maximum input voltage of digital input pins is lower value between (TVDD+0.3) V and 4.0 V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Recommended Operating Conditions (AVSS = DVSS = 0 V; Note 5) Parameter Symbol Min. Typ. Max. Unit Power Supplies (LDOE pin = “L”; Note 9) Analog AVDD 3.0 5.0 5.5 V Digital I/O TVDD VDD18 1.8 3.6 V Digital Core VDD18 1.7 1.8 1.98 V (LDOE pin = “H”; Note 10) Analog AVDD 3.0 5.0 5.5 V Digital I/O TVDD 3.0 3.3 3.6 V Reference Voltage (Note 11) High VREF VREFH 1/2/3/4 AVDD0.5 - AVDD V Low VREF VREFL 1/2/3/4 - AVSS - V Note 9. When the LDOE pin = “L”, VDD18 must be supplied at the same time as or after TVDD. The power up sequence between AVDD and TVDD or AVDD and VDD18 is not critical. Note 10. When the LDOE pin = “H”, the internal LDO supplies 1.8 V (typ). The power up sequence between AVDD and TVDD is not critical. Note 11. VREFH1/2/3/4 must be input at the same time as or after AVDD.
[AK4468] 019001349-E-01 2019/06 - 11 -
Electrical Characteristics
8.1.1. PCM Mode (AVDD = 5.0 V) (Ta = 25 C; LDOE pin = “H”, TVDD = 3.3 V, AVDD = 5.0 V; AVSS = DVSS = 0 V; VREFH1/2/3/4 = 5.0 V, VREFL1/2/3/4 = 0 V; fs = 44.1 kHz; BICK = 64 fs; Signal Frequency = 1 kHz; 32-bit Input Data; RL 1.4 kΩ; measurement bandwidth = 20 Hz–20 kHz; External Circuit: (Figure 76); unless otherwise specified.) Parameter Min. Typ. Max. Unit Resolution - - 32 bit Dynamic Characteristics (Note 12) THD+N fs = 44.1 kHz BW = 20 kHz 0 dBFS - -107 -100 dB 60 dBFS - -54 - dB fs = 96 kHz BW = 40 kHz 0 dBFS - -104 - dB 60 dBFS - -50 - dB fs = 192/384/768 kHz BW = 40 kHz BW = 80 kHz 0 dBFS - -104 - dB 60 dBFS - -50 - dB 60 dBFS - -46 - dB Dynamic Range (60 dBFS with A-weighted) (Note 13) - 117 - dB S/N (A-weighted) 112 117 - dB Interchannel Isolation (1 kHz) 100 110 - dB DC Accuracy Interchannel Gain Mismatch - 0 0.3 dB Gain Drift (Note 14) - 20 - ppm/°C Differential Output Voltage (Note 15) 5.3 5.6 5.9 Vpp Load Resistance (Note 16) 1.4 - - k Load Capacitance (Note 17) - - 30 pF Power Supplies Power Supply Current Normal operation (PDN pin = “H”) (LDOE pin = “L”, VDD18 = 1.8 V) AVDD - 43 59 mA TVDD - 1 1.2 mA VDD18 (fs = 44.1 kHz) - 8 13 mA VDD18 (fs = 96 kHz) - 13 20 mA VDD18 (fs = 192 kHz) - 20 31 mA VDD18 (fs = 384 kHz) - 7 - mA VDD18 (fs = 768 kHz) - 10 - mA (LDOE pin = “H”) AVDD - 43 59 mA TVDD (fs = 44.1 kHz) - 9 15 mA TVDD (fs = 96 kHz) - 14 22 mA TVDD (fs = 192 kHz) - 21 33 mA TVDD (fs = 384 kHz) - 8 - mA TVDD (fs = 768 kHz) - 11 - mA Power down (PDN pin = “L”) (Note 18) AVDD+TVDD - 1 400 A VREF Supplies VREF Supply Current (VREFH1+VREFH2+VREFH3+VREFH4) Normal operation (PDN pin = “H”) - 0.5 0.9 mA Note 12. Measured by Audio Precision APx555, averaging mode.
[AK4468] 019001349-E-01 2019/06 - 12 - Note 13. When using the circuit shown in Figure 76. 100 dB at 16-bit data. Note 14. The voltage of (VREFH1/2/3/4 - VREFL1/2/3/4) is held at 5 V. Note 15. The output voltage scale with the voltage of (VREFH1/2/3/4 - VREFL1/2/3/4). DAC1: AOUTL1/R1 (typ.@0dB) = (AOUTL1P/R1P) (AOUTL1N/R1N) = 1.12Vpp (VREFH1 VREFL1) DAC2: AOUTL2/R2 (typ.@0dB) = (AOUTL2P/R2P) (AOUTL2N/R2N) = 1.12Vpp (VREFH2 VREFL2) DAC3: AOUTL3/R3 (typ.@0dB) = (AOUTL3P/R3P) (AOUTL3N/R3N) = 1.12Vpp (VREFH3 VREFL3) DAC4: AOUTL4/R4 (typ.@0dB) = (AOUTL4P/R4P) (AOUTL4N/R4N) = 1.12Vpp (VREFH4 VREFL4) Note 16. The load resistance value is without a DC cut capacitor, and is with respect to ground. The AC load is 1.0 k (min) with a DC cut capacitor. Note 17. Load Capacitance value is with respect to ground. Note 18. All other digital input pins including clock pins, (MCLK, BICK and LRCK), are held to DVSS.
[AK4468] 019001349-E-01 2019/06 - 13 - 8.1.2. PCM Mode (AVDD = 3.3 V) (Ta = 25 C; LDOE pin = “H”, TVDD = 3.3 V, AVDD = 3.3 V; AVSS = DVSS = 0 V; VREFH1/2/3/4 = 3.3 V, VREFL1/2/3/4 = 0 V; fs = 44.1 kHz; BICK = 64 fs; Signal Frequency = 1 kHz; 32-bit Input Data; RL 1.4 kΩ; measurement bandwidth = 20 Hz–20 kHz; External Circuit (Figure 76); unless otherwise specified.) Parameter Min. Typ. Max. Unit Resolution - - 32 bit Dynamic Characteristics (Note 12) THD+N fs = 44.1 kHz BW = 20 kHz 0 dBFS - -100 -93 dB 60 dBFS - -50 - dB fs = 96 kHz BW = 40 kHz 0 dBFS - -99 - dB 60 dBFS - -46 - dB fs = 192/384/768 kHz BW = 40 kHz BW = 80 kHz 0 dBFS - -99 - dB 60 dBFS - -46 - dB 60 dBFS - -42 - dB Dynamic Range (60 dBFS with A-weighted) (Note 13) - 113 - dB S/N (A-weighted) 108 113 - dB Interchannel Isolation (1 kHz) 100 110 - dB DC Accuracy Interchannel Gain Mismatch - 0 0.3 dB Gain Drift (Note 19) - 20 - ppm/°C Differential Output Voltage (Note 15) 3.32 3.7 4.08 Vpp Load Resistance (Note 16) 1.4 - - k Load Capacitance (Note 17) - - 30 pF Power Supplies Power Supply Current Normal operation (PDN pin = “H”) (LDOE pin = “L”, VDD18 = 1.8 V) AVDD - 35 49 mA TVDD - 1 1.2 mA VDD18 (fs = 44.1 kHz) - 8 13 mA VDD18 (fs = 96 kHz) - 13 20 mA VDD18 (fs = 192 kHz) - 20 31 mA VDD18 (fs = 384 kHz) - 7 - mA VDD18 (fs = 768 kHz) - 10 - mA (LDOE pin = “H”) AVDD - 35 49 mA TVDD (fs = 44.1 kHz) - 9 15 mA TVDD (fs = 96 kHz) - 14 22 mA TVDD (fs = 192 kHz) - 21 33 mA TVDD (fs = 384 kHz) - 8 - mA TVDD (fs = 768 kHz) - 11 - mA Power down (PDN pin = “L”) (Note 18) AVDD+TVDD 400 VREF Supplies VREF Supply Current (VREFH1+VREFH2+VREFH3+VREFH4) Normal operation (PDN pin = “H”) - 0.4 0.9 mA Note 19. The voltage of (VREFH1/2/3/4 - VREFL1/2/3/4) is held at 3.3 V.
[AK4468] 019001349-E-01 2019/06 - 14 - 8.1.3. DSD mode (Ta = 25C: LDOE pin = “H”, TVDD = 3.3 V, AVDD = 5.0 V: AVSS = DVSS = 0 V: VREFH1/2/3/4 = 5.0 V, VREFL1/2/3/4 = 0 V: fs = 44.1 kHz: Signal Frequency = 1 kHz: RL 1.4 kΩ: measurement bandwidth = 20 Hz–20 kHz: External Circuit: (Figure 76): unless otherwise specified.) Parameter Min Typ Max Unit Dynamic Characteristics THD+N DSD data stream： DSD64 0dB (Note 20) - -107 - dB DSD data stream： DSD128 0dB (Note 20) - -107 - dB DSD data stream： DSD256 0dB (Note 20) - -107 - dB DSD data stream： DSD512 0dB (Note 20) - -107 - dB S/N (A-weighted, Normal path) DSD data stream： DSD64 Digital “0” (Note 21) - 116 - dB DSD data stream： DSD128 Digital “0” (Note 21) - 116 - dB DSD data stream： DSD256 Digital “0” (Note 21) - 116 - dB DSD data stream： DSD512 Digital “0” (Note 21) - 116 - dB DC Accuracy Differential Output Voltage (Normal path) (Note 22) - 5.0 - Vpp Differential Output Voltage (Volume Bypass) (Note 22) - 5.0 - Vpp Note 20. The output level is assumed as 0 dB when a 1 kHz 25%–75% duty sine wave is input. Click noise may occur if the input signal exceeds 0 dB. Note 21. Digital “0” is a “01101001” digital zero code pattern. Note 22. The analog output voltage at 25%–75% input signal duty is calculated by the following equation: DAC1: AOUTL1/R1 (typ.@0dB) = (AOUTL1P/R1P) (AOUTL1N/R1N) = 1.0Vpp (VREFH1 VREFL1) DAC2: AOUTL2/R2 (typ.@0dB) = (AOUTL2P/R2P) (AOUTL2N/R2N) = 1.0Vpp (VREFH2 VREFL2) DAC3: AOUTL3/R3 (typ.@0dB) = (AOUTL3P/R3P) (AOUTL3N/R3N) = 1.0Vpp (VREFH3 VREFL3) DAC4: AOUTL4/R4 (typ.@0dB) = (AOUTL4P/R4P) (AOUTL4N/R4N) = 1.0Vpp (VREFH4 VREFL4)
[AK4468] 019001349-E-01 2019/06 - 15 - DAC Digital -Filter Characteristics (PCM Mode) 8.2.1. Sharp Roll-Off Filter Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; DEM[1:0] bits = “01”(OFF), ADPE bit = “0”, SYNCE bit = “1”, SLOW bit = “0”, SD bit = “0”, SSLOW bit = “0”) ・fs = 44.1 kHz (Normal Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 20.0 kHz Pass band (Note 24) PB 0 - 20.0 kHz Stop band (Note 24) SB 24.1 - - kHz Pass band Ripple (Note 25) PR - - ±0.0032 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 26.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–20.0 kHz - -0.2 - 0.1 dB ・fs = 96 kHz (Double Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 43.5 kHz Pass band (Note 24) PB 0 - 43.5 kHz Stop band (Note 24) SB 52.5 - - kHz Pass band Ripple (Note 25) PR - - ±0.0032 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 26.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–40.0 kHz - -0.6 - 0.1 dB ・fs = 192 kHz (Quad Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 87.0 kHz Pass band (Note 24) PB 0 - 87.0 kHz Stop band (Note 24) SB 105 - - kHz Pass band Ripple (Note 25) PR - - ±0.0032 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 26.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–80.0 kHz - -2.0 - 0.1 dB Note 23. Frequency response refers to the output level of 1 kHz. Stopband attenuation band ranges from SB to fs. Note 24. The passband and stopband frequencies scale with fs. For example, PB = 0.454 fs(@0.05 dB), SB = 0.546 fs. Note 25. This value is the gain ripple in pass band width. Note 26. The calculating delay time which occurred by digital filtering. This value is from setting the 16/20/24/32-bit data of both channels to the output of analog signal.
[AK4468] 019001349-E-01 2019/06 - 17 - 8.2.2. Slow Roll-Off Filter Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; DEM[1:0] bits = “01”(OFF), ADPE bit = “0”, SYNCE bit = “1”, SLOW bit = “1”, SD bit = “0”, SSLOW bit = “0”) ・fs = 44.1 kHz (Normal Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 8.1 kHz Pass band (Note 27) PB 0 - 8.1 kHz Stop band (Note 27) SB 39.2 - - kHz Pass band Ripple (Note 25) PR - - ±0.043 dB Stop band Attenuation (Note 23) SA 73 - - dB Group Delay (Note 26) GD - 6.3 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–20.0 kHz - -5.0 - +0.1 dB ・fs = 96 kHz (Double Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 17.7 kHz Pass band (Note 27) PB 0 - 17.7 kHz Stop band (Note 27) SB 85.3 - - kHz Pass band Ripple (Note 25) PR - - ±0.043 dB Stop band Attenuation (Note 23) SA 73 - - dB Group Delay (Note 26) GD - 6.3 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–40.0 kHz - -5.0 - +0.1 dB ・fs = 192 kHz (Quad Speed Mode ) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 35.5 kHz Pass band (Note 27) PB 0 - 35.5 kHz Stop band (Note 27) SB 171 - - kHz Pass band Ripple (Note 25) PR - - ±0.043 dB Stop band Attenuation (Note 23) SA 73 - - dB Group Delay (Note 26) GD - 6.3 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–80.0 kHz - -5.0 - +0.1 dB Note 27. The passband and stopband frequencies scale with fs. For example, PB = 0.184 fs(@0.05 dB), SB = 0.888 fs.
[AK4468] 019001349-E-01 2019/06 - 19 - 8.2.3. Short Delay Sharp Roll-Off Filter Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; DEM[1:0] bits = “01”(OFF), ADPE bit = “0”, SYNCE bit = “1”, SLOW bit = “0”, SD bit = “1”, SSLOW bit = “0”) ・fs = 44.1 kHz (Normal Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 20.0 kHz Pass band (Note 28) PB 0 - 20.0 kHz Stop band (Note 28) SB 24.1 - - kHz Pass band Ripple (Note 25) PR - - 0.0031 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 5.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–20.0 kHz - -0.2 - +0.1 dB ・fs = 96 kHz (Double Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 43.5 kHz Pass band (Note 28) PB 0 - 43.5 kHz Stop band (Note 28) SB 52.5 - - kHz Pass band Ripple (Note 25) PR - - 0.0031 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 5.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–40.0 kHz - -0.6 - +0.1 dB ・fs = 192 kHz (Quad Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 87.0 kHz Pass band (Note 28) PB 0 - 87.0 kHz Stop band (Note 28) SB 105 - - kHz Pass band Ripple (Note 25) PR - - 0.0031 dB Stop band Attenuation (Note 23) SA 80 - - dB Group Delay (Note 26) GD - 5.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–80.0 kHz - -2.0 - +0.1 dB Note 28. The passband and stopband frequencies scale with fs. For example, PB = 0.453 fs(@0.05 dB), SB = 0.547 fs.
[AK4468] 019001349-E-01 2019/06 - 21 - 8.2.4. Short Delay Slow Roll-Off Filter Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; DEM[1:0] bits = “01”(OFF), ADPE bit = “0”, SYNCE bit = “1”, SLOW bit = “1”, SD bit = “1”, SSLOW bit = “0”) ・fs = 44.1 kHz (Normal Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 11.1 kHz Pass band (Note 29) PB 0 - 11.1 kHz Stop band (Note 29) SB 38.1 - - kHz Pass band Ripple (Note 25) PR - 0.05 dB Stop band Attenuation (Note 23) SA 82 - - dB Group Delay (Note 26) GD - 4.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–20.0 kHz - -5.0 - +0.1 dB ・fs = 96 kHz (Double Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 24.2 kHz Pass band (Note 29) PB 0 - 24.2 kHz Stop band (Note 29) SB 83 - - kHz Pass band Ripple (Note 25) PR - 0.05 dB Stop band Attenuation (Note 23) SA 82 - - dB Group Delay (Note 26) GD - 4.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–40.0 kHz - -5.0 - +0.1 dB ・fs = 192 kHz (Quad Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.05 dB - 0 - 48.4 kHz Pass band (Note 29) PB 0 - 48.4 kHz Stop band (Note 29) SB 165.9 - kHz Pass band Ripple (Note 25) PR - 0.05 dB Stop band Attenuation (Note 23) SA 82 - - dB Group Delay (Note 26) GD - 4.8 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–80.0 kHz - -5.0 - +0.1 dB Note 29. The passband and stopband frequencies scale with fs. For example, PB = 0.252 fs(@0.05 dB), SB = 0.864 fs.
[AK4468] 019001349-E-01 2019/06 - 23 - 8.2.5. Low-dispersion Short Delay Filter Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; DEM[1:0] bits = “01”(OFF), ADPE bit = “0”, SYNCE bit = “1”, SLOW bit = “0”, SD bit = “1”, SSLOW bit = “1”) ・fs = 44.1 kHz (Normal Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.1 dB - 0 - 19.2 kHz Pass band (Note 30) PB 0 - 19.2 kHz Stop band (Note 30) SB 25.1 - - kHz Pass band Ripple (Note 25) PR - - 0.04 dB Stop band Attenuation (Note 23) SA 62.0 - - dB Group Delay (Note 26) GD - 10.5 - 1/fs Group Delay Distortion ΔGD - 0.12 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–20.0 kHz - -0.2 - +0.1 dB ・fs = 96 kHz (Double Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.1 dB - 0 - 41.8 kHz Pass band (Note 30) PB 0 - 41.8 kHz Stop band (Note 30) SB 54.6 - - kHz Pass band Ripple (Note 25) PR - - 0.04 dB Stop band Attenuation (Note 23) SA 62 - - dB Group Delay (Note 26) GD - 10.5 - 1/fs Group Delay Distortion ΔGD - 0.12 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–40.0 kHz - -0.6 - +0.1 dB ・fs = 192 kHz (Quad Speed Mode) Parameter Symbol Min. Typ. Max. Unit Digital Filter Frequency Response (Note 23) 0.1 dB - 0 - 83.6 kHz Pass band (Note 30) PB 0 - 83.6 kHz Stop band (Note 30) SB 109.3 - - kHz Pass band Ripple (Note 25) PR - - 0.04 dB Stop band Attenuation (Note 23) SA 62 - - dB Group Delay (Note 26) GD - 10.5 - 1/fs Group Delay Distortion ΔGD - 0.12 - 1/fs Digital Filter + SCF (Note 23) Frequency Response: 0–80.0 kHz - -2.0 - +0.1 dB Note 30. The passband and stopband frequencies scale with fs. For example, PB = 0.435 fs(@0.1 dB), SB = 0.569 fs.
[AK4468] 019001349-E-01 2019/06 - 25 - DAC Digital -Filter Characteristics (DSD mode) 8.3.1. DSDD bit = “0”, DSDF bit = “0” Parameter Min. Typ. Max. Unit DSD Filter Frequency Response (Note 32) DSDSEL[1:0] bits “00” 20 kHz 50 kHz 100 kHz -0.8 -5.5 -19.9 dB “01” 40 kHz 100 kHz 200 kHz -0.8 -5.5 -19.9 dB “10” 80 kHz 200 kHz 400 kHz -0.8 -5.5 -19.9 dB “11” 160 kHz 400 kHz 800 kHz -0.8 -5.5 -19.9 dB 8.3.2. DSDD bit = “0”, DSDF bit = “1” Parameter Min. Typ. Max. Unit DSD Filter Frequency Response (Note 32) DSDSEL[1:0] bits “00” 20 kHz 50 kHz 100 kHz -0.2 -6.3 -23.7 dB “01” 40 kHz 100 kHz 200 kHz -0.2 -6.3 -23.7 dB “10” 80 kHz 200 kHz 400 kHz -0.2 -6.3 -23.7 dB “11” 160 kHz 400 kHz 800 kHz -0.8 -6.3 -23.7 dB 8.3.3. DSDD bit = “1” Parameter Min. Typ. Max. Unit DSD Filter Frequency Response (Note 32) DSDSEL[1:0] bits “00” 20 kHz 100 kHz 200 kHz -0.2 -6.3 -23.7 dB “01” 40 kHz 200 kHz 400 kHz -0.2 -6.3 -23.7 dB “10” 80 kHz 400 kHz 800 kHz -0.2 -6.3 -23.7 dB “11” 160 kHz 500 kHz
1 MHz
-0.05 -0.5 -1.8 dB Note 31. Do not input the signal which exceeds 25%–75% duty range. Note 32. Frequency response refers to the output level of 1 kHz.
[AK4468] 019001349-E-01 2019/06 - 26 - DC Characteristics Parameter Symbol Min. Typ. Max. Unit TVDD = 1.7–3.0 V High-Level Input Voltage VIH 80%TVDD - - V Low-Level Input Voltage VIL - - 20%TVDD V TVDD = 3.0–3.6 V High-Level Input Voltage VIH 70%TVDD - - V Low-Level Input Voltage VIL - - 30%TVDD V High-Level Output Voltage (TDMO0/1, DZF pins: Iout = -100 µA) VOH TVDD0.3 - - V Low-Level Output Voltage (except SDA pin: Iout = 100 µA) VOL - - 0.3 V (SDA pin, 2.0 V TVDD 3.6 V: Iout = 3 mA) VOL - - 0.4 V (SDA pin, 1.7 V TVDD 2.0 V: Iout = 3 mA) VOL - - 20%TVDD V Input Leakage Current (Note 33) Iin - - ±10 A Note 33. #6 SDTI3 pin, #7 SDTI4 pin, and #11 SMUTE pin have internal pull-down resistors. The resistance is 100 kΩ (Typ). Therefore, the SDTI3 pin, SDTI4 pin and SMUTE pin are not included in this value.
[AK4468] 019001349-E-01 2019/06 - 27 - Switching Characteristics (Ta = -40–105 °C; AVDD = 3.0–5.5 V, TVDD = 1.7–3.6 V; CL = 20 pF) Parameter Symbol Min. Typ. Max. Unit Master Clock Timing (Note 34) Frequency fCLK 1.8432 49.6640 MHz Duty Cycle dCLK 40 60 % Pulse Width tCLKH 9.05 ns tCLKL 9.05 ns LRCK Clock Timing Normal Mode (TDM[1:0] = “00”) Normal Speed Mode fsn 7.2 54 kHz Double Speed Mode fsd 54 108 kHz Quad Speed Mode fsq 108 216 kHz Oct Speed Mode fso 216 388 kHz Hex Speed Mode fsh 388 776 kHz Duty Cycle Duty 45 55 % TDM128 Mode (TDM[1:0] = “01”) Normal Speed Mode fsn 7.2 54 kHz Double Speed Mode fsd 54 108 kHz Quad Speed Mode fsq 108 216 kHz High time tLRH 1/128fs ns Low time tLRL 1/128fs ns TDM256 Mode (TDM[1:0] = “10”) Normal Speed Mode High time fsn 7.2 54 kHz Double Speed Mode fsd 54 108 kHz High time tLRH 1/256fs ns Low time tLRL 1/256fs ns TDM512 Mode (TDM[1:0] = “11”) Normal Speed Mode fsn 7.2 54 kHz High time tLRH 1/512fs ns Low time tLRL 1/512fs ns Note 34. The MCLK frequency must be changed while the AK4468 is in power down state or reset state by setting the PDN pin = “L”or RSTN bit = “0”.
[AK4468] 019001349-E-01 2019/06 - 28 - Parameter Symbol Min. Typ. Max. Unit PCM Audio Interface Timing Normal Mode (TDM[1:0] = “00”) BICK Period Normal Speed Mode tBCK 1/256fsn ns Double Speed Mode tBCK 1/128fsd ns Quad Speed Mode tBCK 1/64fsq ns Oct Speed Mode tBCK 1/64fso ns Hex Speed Mode tBCK 1/64fsh ns BICK Pulse Width Low tBCKL 9 ns BICK Pulse Width High tBCKH 9 ns BICK “” to LRCK Edge (Note 35) tBLR 5 ns LRCK Edge to BICK “” (Note 35) tLRB 5 ns SDTI1/2/3/4 Hold Time tSDH 5 ns SDTI1/2/3/4 Setup Time tSDS 5 ns TDM128 Mode (TDM[1:0] = “01”) BICK Period Normal Speed Mode tBCK 1/128fsn ns Double Speed Mode tBCK 1/128fsd ns Quad Speed Mode tBCK 1/128fsq ns BICK Pulse Width Low tBCKL 14 ns BICK Pulse Width High tBCKH 14 ns BICK “” to LRCK Edge (Note 35) tBLR 14 ns LRCK Edge to BICK “” (Note 35) tLRB 14 ns SDTI1/2 Hold Time tSDH 5 ns SDTI1/2 Setup Time tSDS 5 ns TDM256 Mode (TDM[1:0] = “10”) BICK Period Normal Speed Mode tBCK 1/256fsn ns Double Speed Mode tBCK 1/256fsd ns BICK Pulse Width Low tBCKL 14 ns BICK Pulse Width High tBCKH 14 ns BICK “” to LRCK Edge (Note 35) tBLR 14 ns LRCK Edge to BICK “” (Note 35) tLRB 14 ns TDMO1/2 Setup time BICK “” tBSS 5 ns TDMO1/2 Hold time BICK “” tBSH 5 ns SDTI1/2 Hold Time tSDH 5 ns SDTI1/2 Setup Time tSDS 5 ns TDM512 Mode (TDM[1:0] = “11”) BICK Period Normal Speed Mode tBCK 1/512fsn ns BICK Pulse Width Low tBCKL 14 ns BICK Pulse Width High tBCKH 14 ns BICK “” to LRCK Edge (Note 35) tBLR 14 ns LRCK Edge to BICK “” (Note 35) tLRB 14 ns TDMO1 Setup time BICK “” tBSS 5 ns TDMO1 Hold time BICK “” tBSH 5 ns SDTI1 Hold Time tSDH 5 ns SDTI1 Setup Time tSDS 5 ns Note 35. It is defined so that LRCK edges do not occur at the same timing of a rising edge of BICK.
[AK4468] 019001349-E-01 2019/06 - 29 - Parameter Symbol Min. Typ. Max. Unit DSD Audio Interface Timing Sampling Frequency fs 30 48 kHz (DSD64 Mode, DSDSEL[1:0] bits= “00”) DCLK Period tDCK 1/64fs ns DCLK Pulse Width Low tDCKL 144 ns DCLK Pulse Width High tDCKH 144 ns DCLK Edge to DSDL/R (Note 36) tDDD 20 20 ns (DSD128 Mode, DSDSEL[1:0] bits = “01”) DCLK Period tDCK 1/128fs ns DCLK Pulse Width Low tDCKL 72 ns DCLK Pulse Width High tDCKH 72 ns DCLK Edge to DSDL/R (Note 36) tDDD 10 10 ns (DSD256 Mode, DSDSEL[1:0] bits = “10”) DCLK Period tDCK 1/256fs ns DCLK Pulse Width Low tDCKL 36 ns DCLK Pulse Width High tDCKH 36 ns DCLK Edge to DSDL/R (Note 36) tDDD 5 5 ns (DSD512 Mode, DSDSEL[1:0] bits = “11”) DCLK Period tDCK 1/512fs ns DCLK Pulse Width Low tDCKL 18 ns DCLK Pulse Width High tDCKH 18 ns DSDL/R Setup Time tDDS 5 ns DSDL/R Hold Time tDDH 5 ns Note 36. DSD data transmitting device must meet this time. “tDDD” is defined from DCLK “↓” until DSDL/R edge when DCKB bit = “0” (default), “tDDD” is defined from DCLK “↑” until DSDL/R edge when DCKB bit = “1”. If the audio data format is in phase modulation mode, “tDDD” is defined from DCLK edge “↓” or “↑” until DSDL/R edge regardless of DCKB bit setting.
[AK4468] 019001349-E-01 2019/06 - 30 - Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-wire Serial Control Mode): CCLK Period tCCK 200 ns CCLK Pulse Width Low tCCKL 80 ns Pulse Width High tCCKH 80 ns CDTI Setup Time tCDS 40 ns CDTI Hold Time tCDH 40 ns CSN “H” Time tCSW 150 ns CSN “” to CCLK “” tCSS 50 ns CCLK “” to CSN “” tCSH 50 ns Control Interface Timing (I2C-Bus Control Mode): SCL Clock Frequency fSCL 400 kHz Bus Free Time Between Transmissions tBUF 1.3 μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 μs Clock Low Time tLOW 1.3 μs Clock High Time tHIGH 0.6 μs Setup Time for Repeated Start Condition tSU:STA 0.6 μs SDA Hold Time from SCL Falling (Note 37) tHD:DAT 0 μs SDA Setup Time from SCL Rising tSU:DAT 0.1 μs Rise Time of Both SDA and SCL Lines tR 0.3 μs Fall Time of Both SDA and SCL Lines tF 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 μs Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Capacitive load on bus Cb 400 pF Power down & Reset Timing PDN Accept Pulse Width tAPD 150 ns PDN Reject Pulse Width tRPD 30 ns Note 37. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 38. I2C-Bus is a trademark of NXP B.V.
Table 2 shows available functions of each control mode. Table 1. Pin/Register Control Mode Select (x: do not care) Table 2. Function List @Pin/Register Control Mode
[AK4468] 019001349-E-01 2019/06 - 36 - D/A Conversion Mode The AK4468 is able to convert either PCM or DSD data to an analog signal. In PCM mode, clocks and PCM data can be input from the BICK, LRCK and SDTI1/2/3/4 pins. In DSD mode, clocks and DSD data can be input from the DCLK, DSDL1/2/3/4 and DSDR1/2/3/4 pins. The AK4468 only supports PCM mode in Pin Control Mode. Table 3 shows available functions in PCM/DSD mode. Table 3 Function List of PCM/DSD mode @Register Control Mode (Y: Available, N/A: Not available) Function Default State Addr Bit PCM DSD PCM/DSD Mode Select PCM mode 02H DP Y Y System Clock Setting @DSD Mode 512fs 02H DCKS N/A Y Digital Filter Select @DSD Mode 39kHz filter 09H DSDF N/A Y Digital Filter Select @PCM Mode Short-delay sharp roll-off filter 01,02,05 H SD SLOW SSLOW Y N/A System Clock Setting Mode Select Manual Setting Mode 00H ACKS Y N/A De-emphasis Response OFF 01,0A,0E H DEM1/2/3/4[1:0] Y N/A Path Select @ DSD Mode Normal Path 06H DSDD N/A Y Audio Data Interface Format @ PCM Mode 32bit MSB 00H DIF[2:0] Y N/A TDM Interface Format Normal Mode 0AH TDM[1:0] Y N/A Daisy Chain Disable 0BH DCHAIN Y N/A Attenuation Level 0dB 03-04H 0F-14H ATTL1/2/3/4[7:0] ATTR1/2/3/4[7:0] Y Y Data Zero Detection Enable Disable 07-08H L1/2/3/4 R1/2/3/4 Y Y Mono/Stereo Mode Select Stereo 02,0DH MONO1/2/3/4 Y Y Data Invert Mode Select OFF 05,0CH INVL1/2/3/4 INVR1/2/3/4 Y Y The data selection of L channel and R channel R channel 02,05,0D H SELLR 1/2/3/4 Y Y DSD Mute Function @ Full-scale Detected Disable 06H DDM N/A Y Soft Mute Enable Normal Operation 01H SMUTE Y Y RSTN Reset 00H RSTN Y Y Clock Synchronization Function Enable 07H SYNCE Y N/A Automatic Mode Switching (PCM/DSD mode) Disable 15H ADPE Y Y
Table 4. PCM/DSD Mode Control @Register Control Mode (x: do not care)
0 PCM BICK LRCK SDTI1 SDTI2 SDTI3 SDTI4 Not
1 DSD DCLK DSDL
completely reset internally when the conversion mode is changed to PCM from DSD mode. Figure 20. D/A Mode Switching Timing (from PCM to DSD) Figure 21. D/A Mode Switching Timing (from DSD to PCM)
the interpolator, the ΔΣ modulator and SCF. frequency settings (Table 5). In Pin Control Mode, it will be in Auto Setting Mode forcibly. Table 5. System Clock Setting Mode @Register Control Mode
0 Manual setting Mode (default)
1 Auto setting Mode
operation, and the analog output becomes Hi-z state (Table 35). floating state until MCLK, BICK and LRCK are supplied.
Table 6. Sampling Speed (Manual Setting Mode)
001 Double Speed Mode 54 kHz–108 kHz
010 Quad Speed Mode 108 kHz–216 kHz
011 Quad Speed Mode 108 kHz–216 kHz
100 Oct Speed Mode 216 kHz–388 kHz
101 Hex Speed Mode 388 kHz–776 kHz
110 Oct Speed Mode 216 kHz–388 kHz
111 Hex Speed Mode 388 kHz–776 kHz
Table 7. System Clock Example (Manual Setting Mode) (N/A: Not available) Table 8. System Clock Example (Manual Setting Mode) (N/A: Not available)
Sampling Speed Mode (Table 9). Therefore, sampling speed setting by DFS[2:0] bits is not necessary. (Table 10, Table 11). In Pin Control Mode, the AK4468 will be in Auto Setting Mode forcibly. Table 9. Sampling Speed (Auto Setting Mode) Table 10. System Clock Example (Auto Setting Mode) (N/A: Not available) Table 11. System Clock Example (Auto Setting Mode) (N/A: Not available) When MCLK = 256fs/384fs, Auto Setting Mode supports sampling rates of 8 kHz–96 kHz (Table 11). one half comparing with when MCLK = 512fs/768fs (Table 12).
Table 12. Relationship between Dynamic Range, S/N and MCLK Frequency (fs = 44.1 kHz) the AK4468 is in standby state until MCLK and DCLK are input. Table 13. System Clock (DSD mode, fs = 32 kHz, 44.1 kHz, 48 kHz) data sampling speed is selected by DSDSEL[1:0] bits (Table 14). Table 14. DSD Data Stream Select Table 15. DSD Playback Path Select
0 Normal Path (default)
1 Volume Bypass
Four data modes, such as Normal Mode, TDM128, TDM256, and TDM512 Modes, are available. setting RSTN bit when the format setting is changed during operation. 2's compliment format and is read on the rising edge of BICK. is read on the rising edge of BICK. format and is read on the rising edge of BICK. Table 16. Audio Interface Format (@Pin Control Mode)
6 L L L 32-bit MSB justified H/L 64fs Figure 27 (default)
7 L L H 32-bit I2S compatible L/H 64fs Figure 28
13 L H H 32-bit I2S compatible L/H 128fs Figure 30
19 H L H 32-bit I2S compatible L/H 256fs Figure 33
25 H H H 32-bit I2S compatible L/H 512fs Figure 36
Note 39. The number of cycles of BICK must be the same as the bit length of setting format or more.
[AK4468] 019001349-E-01 2019/06 - 43 - 9.4.1.2. Input Data Format (Register Control Mode) Normal Mode (TDM[1:0] bits = “00”) 8ch Data is shifted in via the SDTI1/2/3/4 pins using BICK and LRCK inputs. Eight data formats are supported and selected by the DIF[2:0] bits as shown in Table 17. In all formats the serial data is MSB first, 2's compliment format and is read on the rising edge of BICK. Mode 2 can be used for 16-bit and 20-bit and Mode 6 can be used for 16-bit, 20-bit and 24-bit MSB justified formats by zeroing the unused TDM128 Mode (TDM[1:0] bits = “01”) 8ch Data is shifted in via the SDTI1/2 pins using BICK and LRCK inputs. Input data to the SDTI3/4 pins will be ignored. BICK is fixed to 128fs. Six data formats are supported and selected by DIF[2:0] bits, as shown in Table 17. In all formats the serial data is MSB first, 2's compliment format and is read on the rising edge of BICK. Refer to 9.4.1.3 Data Slot Selection Function for options to route data to DAC outputs. TDM256 Mode (TDM[1:0] bits = “10”) 16ch Data is shifted in via the SDTI1/2 pins using BICK and LRCK inputs. Input data to the SDTI3/4 pins will be ignored. BICK is fixed to 256fs. Six data formats are supported and selected by the DIF[2:0] bits, as shown in Table 17. In all formats the serial data is MSB first, 2's compliment format and is read options to route data to DAC outputs. TDM512 Mode (TDM[1:0] bits = “11”) 16ch Data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Input data to the SDTI2/3/4 pins will be ignored. BICK is fixed to 512fs. Six data formats are supported and selected by the DIF[2:0] bits, as shown in Table 17. In all formats the serial data is MSB first, 2's compliment format and is read on to route data to DAC outputs.
Table 17. Audio Interface Format (@Register Control Mode) (N/A: Not available)
000 N/A N/A N/A N/A
001 N/A N/A N/A N/A
Note 40. The number of cycles of BICK must be the same as the bit length of setting format or more.
Figure 28. Mode 7 Timing
128 BICK
32 BICK
32 BICK 32 BICK 32 BICK
Figure 29. Mode 8/11/12 Timing
32 BICK 32 BICK 32 BICK 32 BICK
Figure 30. Mode 9/13 Timing
Figure 31. Mode 10 Timing
256 BICK
Figure 32. Mode 14/17/18 Timing Figure 33. Mode 15/19 Timing Figure 34. Mode 16 Timing
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 35. Mode 20/23/24 Timing Figure 36. Mode 21/25 Timing Figure 37. Mode 22 Timing
Figure 41. DAC output data can be selected by SDS[2:0] bits (Register Control Mode only), as shown in Figure 38. Data Slot in Normal Mode Figure 39. Data Slot in TDM128 Mode Figure 40. Data Slot in TDM256 Mode
512 BICK
Figure 41. Data Slot in TDM512 Mode
Table 18. Data Select (x: Do not care)
000 L1 R1 L2 R2 L3 R3 L4 R4
001 L2 R2 L3 R3 L4 R4 L5 R5
010 L3 R3 L4 R4 L5 R5 L6 R6
011 L4 R4 L5 R5 L6 R6 L7 R7
100 L5 R5 L6 R6 L7 R7 L8 R8
101 L6 R6 L7 R7 L8 R8 L1 R1
110 L7 R7 L8 R8 L1 R1 L2 R2
111 L8 R8 L1 R1 L2 R2 L3 R3
ignored in Daisy Chain mode.
0 Disable Input (SDTI3) Input (SDTI4) (default)
1 Enable Output (TDMO1) Output (TDMO2)
the first AK4468’s SDTI1 pin. At TDM512 mode, TDMO2 outputs "L". the DAC of the second AK4468, and the second AK4468 outputs the data from TDMO1 by shifting 8ch. both first AK4468 and the second AK4468 must be the same. Figure 42. Daisy Chain (TDM512 Mode) Figure 43. Daisy Chain (TDM512 Mode)
to the first AK4468’s SDTI1/2 pin. of DAC. DIF[2:0] bits setting of both first AK4468 and the second AK4468 must be the same. Figure 44. Daisy Chain (TDM256 Mode) Figure 45. Daisy Chain (TDM256 Mode)
AK4468 for sound color selection of music playback. Normal, Double and Quad Speed Mode (Table 21). Table 20. Digital Filter Setting Table by Control Mode (@PCM mode) Table 21. Digital Filter Setting Table by Control Register (@PCM mode) (x: do not care) 44.1 kHz. The cutoff frequency tracks the sampling frequency (fs). Table 22. Digital Filter Setting Table (@DSD mode) (x: do not care)
data mode is switched between PCM and DSD modes. Table 23. De-emphasis Control (Register Control Mode)
01 OFF (default)
Table 24. Attenuation Level of Digital Attenuator (Table 25). Register setting values will be kept even switching the PCM and DSD modes. Table 25. Attenuation Transition Time Setting changed within 10/fs after releasing reset.
shows output signal settings of the DZF pin. Table 26. Output Select for DZF Pin
0 Zero Detection Flag (“H” when detect zero) (default)
1 Zero Detection Flag (“L” when detect zero)
0 DSD Full-scale Detection Flag
1 DSD Full-scale Detection Flag
continuously “0” for a detection time shown in Table 27. Table 27. Zero Detection Time Zero detection flag is cleared if any of data of the selected channel is no longer “0”. detection flag will be cleared in 4/fs–5/fs by releasing reset (RSTN bit = “1”). of zero detection flag (Table 26). case, the DZF pin outputs “H” if DZFB bit = “0” and outputs “L” if DZFB bit = “1”.
releasing full-scale detection state is according to the setting of ATS[1:0] bits (Table 25). detection state is released. signal becomes full-scale from the state there is an input signal and vice versa. Table 28. DSD Full-scale Detection Time Setting Table 29. Relationship between Output Signal Transition Time and DSDD bit (DDM bit = “1”)
0 Normal Path Rapidly As ATS[1:0] bits (default)
1 Volume Bypass Rapidly
signal of DSD full-scale detection of all power-on channels (PWx bit = “1”) is output from the DZF pin.
INVR1/2/3/4 bits (Table 30). These functions are available on all audio formats. Table 30. Output Select for DAC1/2/3/4 (Register Control Mode)
[AK4468] 019001349-E-01 2019/06 - 62 - MONO3 bit SELLR3 bit INVL3 bit INVR3 bit (AOUTL3N, AOUTL3P pins) (AOUTR3N, AOUTR3P pins) 0 0 0 0 L3ch in R3ch in 1 0 L3ch in Invert R3ch in 0 1 L3ch in R3ch in Invert 1 1 L3ch in Invert R3ch in Invert 0 1 0 0 R3ch in L3ch in 1 0 R3ch in Invert L3ch in 0 1 R3ch in L3ch in Invert 1 1 R3ch in Invert L3ch in Invert 1 0 0 0 L3ch in L3ch in 1 0 L3ch in Invert L3ch in 0 1 L3ch in L3ch in Invert 1 1 L3ch in Invert L3ch in Invert 1 1 0 0 R3ch in R3ch in 1 0 R3ch in Invert R3ch in 0 1 R3ch in R3ch in Invert 1 1 R3ch in Invert R3ch in Invert MONO4 bit SELLR4 bit INVL4 bit INVR4 bit (AOUTL4N, AOUTL4P pins) (AOUTR4N, AOUTR4P pins) 0 0 0 0 L4ch in R4ch in 1 0 L4ch in Invert R4ch in 0 1 L4ch in R4ch in Invert 1 1 L4ch in Invert R4ch in Invert 0 1 0 0 R4ch in L4ch in 1 0 R4ch in Invert L4ch in 0 1 R4ch in L4ch in Invert 1 1 R4ch in Invert L4ch in Invert 1 0 0 0 L4ch in L4ch in 1 0 L4ch in Invert L4ch in 0 1 L4ch in L4ch in Invert 1 1 L4ch in Invert L4ch in Invert 1 1 0 0 R4ch in R4ch in 1 0 R4ch in Invert R4ch in 0 1 R4ch in R4ch in Invert 1 1 R4ch in Invert R4ch in Invert
ignored when ADPE bit is “1”. ADPE bit must be set while PW bit or RSTN bit = “0”. set while PW bit or RSTN bit = “0”. receiving data (DCKB bit = “1”). AK4468 keeps previous mode instead of executing mode detection if any condition is not satisfied.
- Input data of all channels are zero for a period set by ADPT[1:0] bits (Table 31).
- Output data of all channels are zero for a period set by ADPT[1:0] bits because of attenuation (Table
- Input data of all channels are full-scale for a period set by DDMT bit in DSD mode (Table 28).
Table 31. Time Until Mode Detection after Input Data Becomes Zero
code continuously to the LRCK/DSDL1 pin to transition to DSD mode from PCM mode (Table 32). mode from DSD mode (Table 32). Refer to Figure 52 and Figure 53 for the operation sequence. The AK4468 keeps previous mode instead of executing mode detection if any condition is not satisfied. Table 32. Input Signal when Switching PCM/DSD Modes maintained if the input clock to the BICK/DCLK pin (#2) is stopped.
(5) When data mode is changed, the AK4468 executes internal reset for 3–4/fs automatically. “0”. In this case, delay time depends on DDMT bit setting. maintained if the input clock to the BICK/DCLK pin (#2) is stopped. Figure 52. Changing to DSD mode after Power-up in PCM mode
mode. Mode detection is executed even when there is no MCLK input. “0”. In this case, delay time depends on DDMT bit setting. (7) When data mode is changed, the AK4468 executes internal reset for 3–4/fs automatically. maintained if the input clock to the BICK/DCLK pin (#2) is stopped. Figure 53. Changing to PCM Mode after Power-up in DSD Mode
changing the signal source without stopping the signal transmission. setting value is “FFH” and ATS[1:0] bits = “00”. “L” if the input data is not zero. discontinued and returned to ATT level by the same cycle. Figure 54. Soft Mute Function
from the recommended capacitor value. It takes 2 ms (max.) to power-up the internal LDO. Table 33. LDO Select Mode (x: Do not care) LDO OFF: Supply 1.7–1.98 V to VDD18. from the error detection status. Table 34. LDO Error Detection
1 LDO Overvoltage
exceeds overvoltage threshold.
2 LDO Overcurrent
output exceeds overcurrent threshold.
The timing example when not using the internal LDO (LDOE pin = “L”) is shown in Figure 56. should be input after AVDD is powered up or at the same time. more than 150 ns after AVDD, TVDD and VDD18 are powered up. “H”, and the internal circuit will start operation. (4) Click noise occurs on an edge of PDN signal. This noise is output even if “0” data is input. (5) Mute the analog output externally if click noise (4) adversely affect system performance. stopped before AVDD is powered down or at the same time. (7) Analog outputs are floating (Hi-Z) in power down state. (8) Do not input clocks (MCLK, BICK and LRCK) until after TVDD is turned on. Figure 56. Power-up/down Sequence Example (Pin Control Mode, LDOE pin = “L”)
and RSTN bit(Table 35, Table 36). Table 35. Power Down, Standby and Reset Function (×: do not care) Table 36. Power Down, Standby and Reset function (detail)
0 Hi-Z Hi-Z Hi-Z Hi-Z
1 Signal output Hi-Z Hi-Z Hi-Z
1 Hi-Z Signal output Hi-Z Hi-Z
0 Hi-Z (VREFH2+VR
1 Hi-Z Hi-Z Signal output Hi-Z
0 Hi-Z Hi-Z (VREFH3+VR
1 Hi-Z Hi-Z Hi-Z Signal output
0 Hi-Z Hi-Z Hi-Z (VREFH4+VR
1 Signal output Signal output Signal output Signal output
detection function is disabled when MCLK is stopped. 1 μs (min.) during operation. (2) The analog output goes to floating state (Hi-Z) in standby state. (3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply. the PDN pin is not necessary. Figure 59. Standby Sequence by MCLK
floating state (Hi-Z). Figure 60 shows standby sequence by PW1/2/3/4 bits. (3) The analog output is floating (Hi-Z) state when PW1/2/3/4 bits = “0”. (5) The zero detection function is enable when the AK4468 is in standby state (PW1/2/3/4 bits = “0”). (6) It takes 2–3/fs until standby state is released when writing “1” to PW1/2/3/4 bits. Figure 60. Standby Sequence by PW1/2/3/4 bits (Register Control Mode)
(3) Mute the analog output externally if click noise (2) adversely affect system performance. (4) The analog output is (VREFH1/2/3/4+VREFL1/2/3/4)/2 V when RSTN bit = “0”. and goes “L” 1/fs after a rising edge of internal RSTN bit. Figure 61. Reset Timing Example (Register Control Mode)
device can be kept within 4/256 fs when using multiple AK4468’s. output becomes (VREFH1/2/3/4+VREFL1/2/3/4)/2 V. synchronizing sequence by RSTN bit. (1) When all channels data are “0” for 8192 times continuously, the synchronize function is enabled. synchronize function is enabled. (3) Input data of ΔΣ Modulator is fixed to “0” forcibly for 8 to 10/fs when internal counter is reset. input. Mute the analog output externally if this click noise affects the system performance. (5) Refer to “9.7 Digital Attenuation” for ATT transition time. reset even if the synchronize function is valid. Figure 62. Synchronization Sequence by Continuous “0” Data Input for 8192 Times
If RSTN bit is set to “0”, digital circuit is reset in 3–4/fs and the synchronization function becomes valid. to have a no-input period longer than the group delay before writing “0” to RSTN bit. become invalid after the internal RSTN is changed when changing RSTN bit to “1”. internal RSTN signal of the LSI is changed. (4) Input data of ΔΣ Modulator is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset. this click noise affects the system performance. Figure 63. Synchronization Sequence by RSTN bit (Register Control Mode)
“”. The clock speed of CCLK is 5 MHz (max). register values are not initialized. Figure 64. Control I/F Timing (1) The AK4468 does not support read commands in 3-wire serial control mode. (2) When the PDN pin = “L”, writing into control registers is prohibited.
[AK4468] 019001349-E-01 2019/06 - 83 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 default 00H Control 1 ACKS 0 0 0 DIF[2] DIF[1] DIF[0] RSTN 0CH 01H Control 2 0 0 SD DFS[1] DFS[0] DEM1[1] DEM1[0] SMUTE 22H 02H Control 3 DP ADP DCKS DCKB MONO1 DZFB SELLR1 SLOW 00H 03H L1ch ATT ATTL1[7] ATTL1[6] ATTL1[5] ATTL1[4] ATTL1[3] ATTL1[2] ATTL1[1] ATTL1[0] FFH 04H R1ch ATT ATTR1[7] ATTR1[6] ATTR1[5] ATTR1[4] ATTR1[3] ATTR1[2] ATTR1[1] ATTR1[0] FFH 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 DFS[2] SSLOW 00H 06H DSD1 DDM DML1 DMR1 DDMOE 0 DDMT DSDD DSDSEL[0] 00H 07H Control 5 L3 R3 L4 R4 0 0 1 SYNCE 03H 08H Control 6 L1 R1 L2 R2 0 0 0 0 00H 09H DSD2 DML2 DMR2 DML3 DMR3 DML4 DMR4 DSDF DSDSEL[1] 00H 0AH Control 7 TDM[1] TDM[0] SDS[1] SDS[2] PW2 PW1 DEM2[1] DEM2[0] 0DH 0BH Control 8 ATS[1] ATS[0] 0 SDS[0] PW4 PW3 DCHAIN 0 0CH 0CH Control 9 INVL4 INVR4 INVL3 INVR3 0 0 0 0 00H 0DH Control 10 MONO4 MONO3 MONO2 0 SELLR4 SELLR3 0 0 00H 0EH Control 11 DEM4[1] DEM4[0] DEM3[1] DEM3[0] 0 0 0 0 50H 0FH L2ch ATT ATTL2[7] ATTL2[6] ATTL2[5] ATTL2[4] ATTL2[3] ATTL2[2] ATTL2[1] ATTL2[0] FFH 10H R2ch ATT ATTR2[7] ATTR2[6] ATTR2[5] ATTR2[4] ATTR2[3] ATTR2[2] ATTR2[1] ATTR2[0] FFH 11H L3ch ATT ATTL3[7] ATTL3[6] ATTL3[5] ATTL3[4] ATTL3[3] ATTL3[2] ATTL3[1] ATTL3[0] FFH 12H R3ch ATT ATTR3[7] ATTR3[6] ATTR3[5] ATTR3[4] ATTR3[3] ATTR3[2] ATTR3[1] ATTR3[0] FFH 13H L4ch ATT ATTL4[7] ATTL4[6] ATTL4[5] ATTL4[4] ATTL4[3] ATTL4[2] ATTL4[1] ATTL4[0] FFH 14H R4ch ATT ATTR4[7] ATTR4[6] ATTR4[5] ATTR4[4] ATTR4[3] ATTR4[2] ATTR4[1] ATTR4[0] FFH 15H Control 12 ADPE ADPT[1] ADPT[0] 0 0 0 0 0 00H Notes: (1) In 3-wire serial control mode, the AK4468 does not support read commands. (2) The AK4468 supports read command in I2C-Bus control mode. (3) If the address exceeds “15H”, the address counter will “roll over” to “00H” and the next write/read address will be “00H” by automatic increment function in I2C-Bus control mode. (4) Bits indicated as 0 in each address must contain a “0” value. Malfunctions may occur if writing “1” to these bits. (5) Writing data to addresses after 15H is forbidden. Malfunctions may also occur by this action. (6) When the PDN pin goes to “L”, the registers are initialized to their default values. (7) When RSTN bit is set to “0”, the digital block except control registers and clock divider is reset, and the registers are not initialized to their default values.
[AK4468] 019001349-E-01 2019/06 - 84 - Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 0 DIF[2] DIF[1] DIF[0] RSTN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. (default) 1: Normal Operation DIF[2:0]: Audio Data Interface Modes Select (Table 17) The default value is “110” (Mode6: 32-bit MSB justified). ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM mode only). (Table 5, Table 6, Table 9) 0: Disable: Manual Setting Mode (default) 1: Enable: Auto Setting Mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 0 0 SD DFS[1] DFS[0] DEM1[1] DEM1[0] SMUTE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal Operation (default) 1: DAC Outputs Soft-muted. DEM1[1:0]: DAC1 De-emphasis Filter Control (Table 23) The default value is “01” (OFF). DFS[2:0]: Sampling Speed Control (Table 6) The default value is “000” (Normal Speed). Click noise occurs when DFS[2:0] bits are changed. See also Addr. 05H. SD: Short Delay Filter Enable (Table 21) 0: Traditional Filter (SSLOW = “0”) Super Slow Roll-off Filter (SSLOW = “1”) 1: Short delay Filter (SSLOW = “0”, default) Low Dispersion Filter (SSLOW = “1”)
[AK4468] 019001349-E-01 2019/06 - 85 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Control 3 DP ADP DCKS DCKB MONO1 DZFB SELLR1 SLOW R/W R/W R R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SLOW: Slow Roll-off Filter Enable (Table 21) 0: Slow Roll-off Filter Disable (default) 1: Slow Roll-off Filter SELLR1: DAC1 Data Selection of L channel and R channel (Table 30) DZFB: Inverting Enable of DZF (Table 26) 0: DZF pin goes “H” at Zero Detection (default) 1: DZF pin goes “L” at Zero Detection MONO1: DAC1 MONO/Stereo Mode Select (Table 30) 0: Stereo Mode (default) 1: Mono Mode DCKB: Polarity of DCLK (DSD Mode Only) 0: DSD data is output from DCLK falling edge. (default) 1: DSD data is output from DCLK rising edge. DCKS: Master Clock Frequency Select at DSD Mode (DSD mode only) 0: 512fs (default) 1: 768fs ADP: Read Back Register for Internal Operation Mode. This bit is valid when ADPE bit = “1”. It is invalid when ADPE bit = “0” and readouts “0” when read. 0: PCM Mode 1: DSD Mode DP: DSD/PCM Mode Select 0: PCM Mode (default) 1: DSD Mode *When DP bit is changed, the AK4468 should be reset by RSTN bit. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H L1ch ATT ATTL1[7] ATTL1[6] ATTL1[5] ATTL1[4] ATTL1[3] ATTL1[2] ATTL1[1] ATTL1[0] 04H R1ch ATT ATTR1[7] ATTR1[6] ATTR1[5] ATTR1[4] ATTR1[3] ATTR1[2] ATTR1[1] ATTR1[0] R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 ATTL1[7:0]: DAC1 L-channel Attenuation Level Setting (Table 24) ATTR1[7:0]: DAC1 R-channel Attenuation Level Setting (Table 24)
[AK4468] 019001349-E-01 2019/06 - 86 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 DFS[2] SSLOW R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SSLOW: Super Slow Roll-off (Digital filter bypass mode) or Low Dispersion Filter Enable (Table 21) 0: Disable (default) 1: Enable (see also SD) DFS[2:0]: Sampling Speed Control (Table 6) The default value is “000” (Normal Speed). Click noise occurs when DFS[2:0] bits are changed. See also Addr. 01H. SELLR2: DAC2 Data Selection of L-channel and R-channel (Table 30) INVR2: DAC2 AOUTR2 Output Phase Inverting Mode 0: Disable (default) 1: Enable INVL2: DAC2 AOUTL2 Output Phase Inverting Mode 0: Disable (default) 1: Enable INVR1: DAC1 AOUTR1 Output Phase Inverting Mode 0: Disable (default) 1: Enable INVL1: DAC1 AOUTL1 Output Phase Inverting Mode 0: Disable (default) 1: Enable
[AK4468] 019001349-E-01 2019/06 - 87 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H DSD1 DDM DML1 DMR1 DDMOE 0 DDMT DSDD DSDSEL[0] R/W R/W R R R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 DSDSEL[1:0]: DSD Sampling Speed Control (Table 14). See also Addr. 09H. DSDD: DSD Playback Path Control 0: Normal Path (default) 1: Volume Bypass DDMT: DSD Signal Full-scale Detection Time Setting (Table 28) DDMOE: Output Setting of the DMR/L Pins for DSD Full-scale Detection (Table 26) DML1/R1: This register outputs detection flag when a full-scale signal is detected at DSDL1/R1 channel. DDM: DSD Data Mute The AK4468 has an internal mute function that mutes the output when DSD input data becomes all “1” or all “0” for 2048 samples (1/fs) continuously. DDM bit controls this function. 0: Disable (default) 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Control 5 L3 R3 L4 R4 0 0 1 SYNCE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 1 SYNCE: SYNC Mode Enable 0: SYNC Mode Disable 1: SYNC Mode Enable (default) L3/4, R3/4: Zero Detection Flag Enable Bit for the DZF pin 0: Disable (default) 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Control 6 L1 R1 L2 R2 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 L1/2, R1/2: Zero Detection Flag Enable Bit for the DZF pin 0: Disable (default) 1: Enable
[AK4468] 019001349-E-01 2019/06 - 88 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H DSD2 DML2 DMR2 DML3 DMR3 DML4 DMR4 DSDF DSDSEL[1] R/W R R R R R R R/W R/W Default 0 0 0 0 0 0 0 0 DSDSEL[1:0]: DSD Sampling Speed Control (Table 14). See also Addr. 06H. DSDF: Cut-off Frequency of DSD Filter Control (Table 22) DML2/3/4, DMR2/3/4: This register outputs detection flag when a full-scale signal is detected at DSDL2/3/4 pins and DSDR2/3/4 pins. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Control7 TDM[1] TDM[0] SDS[1] SDS[2] PW2 PW1 DEM2[1] DEM2[0] R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 1 DEM2[1:0]: DAC2 De-emphasis Filter Control (Table 23) The default value is “01” (OFF). PW1: DAC1 Power Control (Table 36) PW2: DAC2 Power Control (Table 36) SDS[2:0]: Output Data Slot Selection of Each Channel (Table 18) The default value is “000”. See also Addr. 0BH. TDM[1:0]: TDM Mode Select 00: Normal (default) 01: TDM128 10: TDM256 11: TDM512
[AK4468] 019001349-E-01 2019/06 - 89 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH Control 8 ATS[1] ATS[0] 0 SDS[0] PW4 PW3 DCHAIN 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 DCHAIN: Daisy Chain Mode Enable 0: Daisy Chain Mode Disable (default) 1: Daisy Chain Mode Enable PW3: DAC3 Power Control (Table 36) PW4: DAC4 Power Control (Table 36) SDS[2:0]: Output Data Slot Selection for Each Channel (Table 18) The default value is “000”. See also Addr. 0AH. ATS[1:0]: Transition time between set values of ATTL/R[7:0] bits (Table 25) The default value is “00”. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH Control 9 INVL4 INVR4 INVL3 INVR3 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 INVR3: DAC3 AOUTR3 Output Phase Inverting Mode INVL3: DAC3 AOUTL3 Output Phase Inverting Mode INVR4: DAC3 AOUTR4 Output Phase Inverting Mode INVL4: DAC3 AOUTL4 Output Phase Inverting Mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Control 10 MONO4 MONO3 MONO2 0 SELLR4 SELLR3 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SELLR3: DAC3 Data Selection of L-channel and R-channel (Table 30) SELLR4: DAC4 Data Selection of L-channel and R-channel (Table 30) MONO2: DAC2 MONO/Stereo Mode Select (Table 30) 0: Stereo Mode (default) 1: Mono Mode MONO3: DAC3 MONO/Stereo Mode Select (Table 30) 0: Stereo Mode (default) 1: Mono Mode MONO4: DAC4 MONO/Stereo Mode Select (Table 30) 0: Stereo Mode (default) 1: Mono Mode
[AK4468] 019001349-E-01 2019/06 - 90 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Control 11 DEM4[1] DEM4[0] DEM3[1] DEM3[0] 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 1 0 0 0 0 DEM3[1:0]: DAC3 De-emphasis Filter Control (Table 23) DEM4[1:0]: DAC4 De-emphasis Filter Control (Table 23) The default value is “01” (OFF). Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH L2ch ATT ATTL2[7] ATTL2[6] ATTL2[5] ATTL2[4] ATTL2[3] ATTL2[2] ATTL2[1] ATTL2[0] 10H R2ch ATT ATTR2[7] ATTR2[6] ATTR2[5] ATTR2[4] ATTR2[3] ATTR2[2] ATTR2[1] ATTR2[0] 11H L3ch ATT ATTL3[7] ATTL3[6] ATTL3[5] ATTL3[4] ATTL3[3] ATTL3[2] ATTL3[1] ATTL3[0] 12H R3ch ATT ATTR3[7] ATTR3[6] ATTR3[5] ATTR3[4] ATTR3[3] ATTR3[2] ATTR3[1] ATTR3[0] 13H L4ch ATT ATTL4[7] ATTL4[6] ATTL4[5] ATTL4[4] ATTL4[3] ATTL4[2] ATTL4[1] ATTL4[0] 14H R4ch ATT ATTR4[7] ATTR4[6] ATTR4[5] ATTR4[4] ATTR4[3] ATTR4[2] ATTR4[1] ATTR4[0] R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 ATTL2/3/4[7:0]: DAC2/3/4 L-channel Attenuation Level Setting (Table 24) ATTR2/3/4[7:0]: DAC2/3/4 R-channel Attenuation Level Setting (Table 24) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 15H Control 12 ADPE ADPT[1] ADPT[0] 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 ADPT[1:0]: Time until PCM/DSD mode detection when input data becomes zero (Table 31) ADPE: PCM/DSD Automatic Mode Switching Function Enable Bit 0: Disable (default) 1: Enable
10.1.1. Register Control Mode, LDO Disable.
35 VREFL3
34 VREFH3
33 AOUTL3N
32 AOUTL3P
31 AVDD
30 AVSS
29 AOUTR2P
27 VREFH2
26 VREFL2
25 AOUTL2N
24 AOUTL2P
36 AOUTR3N
regulators, etc. maintained. possibility that THD+N characteristic degrades because of high-frequency noise of MCLK. (5) All digital input pins except pull-down/pull-up pins should not be allowed to float. Figure 74. Typical Connection Diagram
regulators, etc. maintained. possibility that THD+N characteristic degrades because of high-frequency noise of MCLK. (5) All digital input pins except pull-down/pull-up pins should not be allowed to float. Figure 75. Typical Connection Diagram
[AK4468] 019001349-E-01 2019/06 - 93 - Grounding and Power Supply Decoupling To minimize coupling of digital noise, decoupling capacitors should be connected to AVDD, TVDD and VDD18. AVDD is supplied from analog supply in system, and TVDD and VDD18 are supplied from digital supply in system. Power line of AVDD should be distributed separately, from the point with low impedance of regulators or other parts. When not using the LDO (LDOE pin = “L”), TVDD must be powered up before or at the same time of VDD18. AVSS and DVSS must be connected to the same analog ground plane. Decoupling capacitors for high frequency should be placed as near as possible to the AK4468. Reference Voltage The VREFH1/2/3/4 pin is normally connected to 5.0 V reference voltage, and the VREFL1/2/3/4 pin is normally connected to the analog ground. Connect a 0.1 µF ceramic and a 100 µF electrolytic capacitors between VREFH1/2/3/4 and VREFL1/2/3/4. Especially the ceramic capacitors should be connected as near as possible to the pin. The potential difference between VREFH1/2/3/4 and VREFL1/2/3/4 set the full-scale of the analog output range. Therefore, the VREFH1/2/3/4 and VREFL1/2/3/4 pins should avoid noises from other power supplies. When it is difficult to obtain expected analog characteristics because of noises from other power supplies, connect the VREFH1/2/3/4 pin to the analog 5.0 V via a 10 Ω resistor, and the VREFL1/2/3/4 pin to the analog ground via a 10 Ω resistor. In addition, connect a 220 µF electrolytic capacitor between VREFH1/2/3/4 and VREFL1/2/3/4. A low pass filter of fc = 36 Hz will be composed with the 220 µF capacitor and the 10 Ω resistor. It removes differential noise between VREFH1/2/3/4 and VREFL1/2/3/4. All digital signals, especially clocks, should be kept away from the VREFH1/2/3/4 and VREFL1/2/3/4 pins in order to avoid unwanted coupling into the AK4468.
Figure 78. External LPF Circuit Example 3 (fc = 174 kHz (Typ), Q = 0.5 (Typ)) Table 39. Frequency Response of External LPF Circuit Example 3
[AK4468] 019001349-E-01 2019/06 - 96 - Package Outline Dimensions Material & Lead Finish Package molding compound: Epoxy Lead frame material: EFTEC-64T Pin surface treatment: Solder (Pb free) plate
[AK4468] 019001349-E-01 2019/06 - 97 - Marking AK4468VN XXXXXXX AKM 1) Pin #1 indication 2) AKM Logo 3) Marking Code: AK4468VN 4) Date Code: XXXXXXX (7 digits) Ordering Guide AK4468VN -40–105 °C 48-pin QFN AKD4468 Evaluation Board for AK4468
[AK4468] 019001349-E-01 2019/06 - 98 -
Revision History
Date (Y/M/D) Revision Reason Page Contents 19/03/08 00 First Edition 19/06/25 01 Error Correction Low VREF [max] AVDD+0.3 or 6.0 V →[max] AVSS+0.3 V Error Correction 15,17,19, 21,23 DEM[2:0] bits → DEM[1:0] bits
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