AK4440 AKM | Alldatasheet
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[AK4440] AK4440 192kHz 24-Bit 8ch DAC with 2Vrms Output GENERAL DESCRIPTION The AK4440 is a 5V 24-bit 8ch DAC with an integrated 2Vrms output buffer. A charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output. Using AKM’s multi bit modulator architecture, the AK4440 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4440 integrates a combination of switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio applications, such as DVD/BD, AV receiver, Home theater systems and set-top boxes. The AK4440 is offered in a space saving 30pin VSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24Bit 8 times FIR Digital Filter with Slow roll-off option Switched-Capacitor Filter with High Tolerance to Clock Jitter Single Ended 2Vrms Output Buffer Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz Soft mute Control I/F: 3-wire Serial and I2C Bus Audio I/F format: MSB justified, LSB justified (16bit, 20bit, 24bit), I2S, TDM Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs or 192fs (Quad Speed Mode) THD+N: -93dB Dynamic Range: 105dB Automatic Power-on Reset Circuit Power Supply: +4.5 to +5.5V Ta = -20 to 85°C Small Package: 30 pin VSOP (9.7mm x 7.6mm) MS1088-E-01 2011/03 - 1 -
[AK4440] Charge VSS2 1μ 1μ Pump CN CP VEE SCF DACLOUT1 SCF DACROUT1 SCF DACLOUT2 SCF DACROUT2 SCF DACLOUT3 SCF DACROUT3 Audio I/F Control Register AK4440 MCLK LRCK BICK 3-wire or I2C SDTI1 SDTI2 SDTI3 PCM SCF DACLOUT4 SCF DACROUT4 SDTI4 LPF LPF LPF LPF LPF LPF LPF LPF VDD VSS1 AVDD Block Diagram MS1088-E-01 2011/03 - 2 -
[AK4440] ■ Ordering Guide AK4440EF -20 ∼ +85°C 30pin VSOP AKD4440 Evaluation Board for AK4440 ■ Pin Layout
1 MCLK
9 SDTI2
- 3 -
[AK4440] PIN/FUNCTION No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI1 I DAC1 Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 TEST O TEST pin. This pin should be open. SMUTE I Soft Mute Pin in parallel mode “H”: Enable, “L”: Disable CSN I Chip Select Pin in serial 3-wire mode CAD0 I Chip Address Pin in serial I2C mode ACKS I Auto Setting Mode Pin in parallel mode “L”: Manual Setting Mode, “H”: Auto Setting Mode CCLK I Control Data Clock Pin in serial 3-wire mode SCL Control Data Clock Pin in serial I2C mode DIF0 I Audio Data Interface Format Pin in parallel mode CDTI I Control Data Input Pin in serial 3-wire mode SDA I/O Control Data Pin in serial I2C mode
9 SDTI2 I DAC2 Audio Serial Data Input Pin
10 SDTI3 I DAC3 Audio Serial Data Input Pin
11 SDTI4 I DAC4 Audio Serial Data Input Pin
12 TDM0B I TDM I/F Format Mode in parallel control mode
“L”: TDM256 mode, “H”: Normal mode
13 DEM0 I De-emphasis Filter Enable Pin in parallel mode
I2C I Control Mode Select Pin in serial mode “L”: 3-wire Serial, “H”: I2C Bus DEM1 I De-emphasis Filter Enable Pin in parallel mode
15 P/S I Parallel/Serial Select Pin (Internal pull-up pin, typ 100k Ω)
“L”: Serial control mode, “H”: Parallel control mode 16 AVDD - DAC Analog Power Supply Pin: 4.5V∼5.5V
17 VSS1 - Ground Pin
18 ROUT4 O DAC4 Rch Analog Output Pin
19 LOUT4 O DAC4 Lch Analog Output Pin
20 ROUT3 O DAC3 Rch Analog Output Pin
21 LOUT3 O DAC3 Lch Analog Output Pin
22 ROUT2 O DAC2 Rch Analog Output Pin
23 LOUT2 O DAC2 Lch Analog Output Pin
24 ROUT1 O DAC1 Rch Analog Output Pin
25 LOUT1 O DAC1 Lch Analog Output Pin
26 VEE O Negative Voltage Output Pin
Connect to VSS2 with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used.
27 CN I Negative Charge Pump Capacitor Terminal Pin
Connect to CP with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used.
28 CP I Positive Charge Pump Capacitor Terminal Pin
Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. MS1088-E-01 2011/03 - 4 -
[AK4440] PIN/FUNCTION (Continued) No. Pin Name I/O Function
29 VSS2 - Ground Pin
30 VDD - Charge Pump and DAC Digital Power Supply Pin: 4.5V∼5.5V Note: All input pins except for the P/S pin should not be left floating. ■ Handling of Unused Pin The following tables illustrate recommended states for open pins: Classification Pin Name Setting Analog LOUT4-1, ROUT4-1 Leave open. SDTI4-1 Connect to VSS2. Digital DEM0, TDM0B (Serial control mode) Connect to VDD or VSS2. TEST Leave open. ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 1) Parameter Symbol min max Units Power Supply VDD AVDD -0.3 -0.3 +6.0 +6.0 V V Input Current (any pins except supplies) IIN - ±10 mA Input Voltage VIND -0.3 VDD+0.3 V Ambient Operating Temperature Ta -20 85 °C Storage Temperature Tstg -65 150 °C Note 1. All voltages with respect to ground. Note 2. VSS1 and VSS2 must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 1) Parameter Symbol min typ max Units Power Supply VDD AVDD +4.5 +5.0 VDD +5.5 V Note 3. VDD and AVDD are the same voltage. *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1088-E-01 2011/03 - 5 -
[AK4440] ANALOG CHARACTERISTICS (Ta=25°C; VDD=AVDD = +5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data; Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) fs=44.1kHz, BW=20kHz -93 -84 dB fs=96kHz, BW=40kHz -92 - dB THD+N (0dBFS) fs=192kHz, BW=40kHz -92 - dB Dynamic Range (-60dBFS with A-weighted, Note 5) 98 105 dB S/N (A-weighted, Note 6) 98 105 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy DC Offset (at output pin) -60 0 +60 mV Gain Drift 100 ppm/°C Output Voltage (Note 7) 1.97 2.12 2.27 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 9) Power Supply Current: (Note 9) Normal Operation (fs≤96kHz) Normal Operation (fs=192kHz) Power-Down Mode (Note 10) 110 120 100 mA mA μA Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual. Note 5. 98dB for 16bit input data Note 6. S/N does not depend on input data size. Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of AVDD, AOUT (typ.@0dB) = 2.12Vrms × VDD/5. Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load. Note 9. The current into VDD and AVDD. Note 10. The P/S pin is tied to VDD and the all other digital inputs including clock pins (MCLK, BICK and LRCK) are tied to VSS2. MS1088-E-01 2011/03 - 6 -
[AK4440] SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD=AVDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min typ max Units Digital filter P a s s b a n d ±0.05dB ( Note 11) - 6 . 0 d B PB 0 22.05 20.0 kHz kHz S t o p b a n d ( Note 11) SB 24.1 kHz Passband Ripple PR ± 0.02 dB Stopband Attenuation SA 54 dB G r o u p D e l a y ( Note 12) GD - 19.3 - 1/fs Digital Filter + SCF + LPF Frequency Response 20.0kHz 40.0kHz 80.0kHz Fs=44.1kHz Fs=96kHz Fs=192kHz FR FR FR ±0.05 ±0.05 ±0.05 dB dB dB Note 11. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. Note 12. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data of both channels to input register to the output of analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD=AVDD = 4.5~5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units Digital Filter P a s s b a n d ±0.04dB ( Note 13) - 3 . 0 d B PB 18.2 8.1 kHz kHz S t o p b a n d ( Note 13) SB 39.2 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA 72 dB G r o u p D e l a y ( Note 12) GD - 19.3 - 1/fs Digital Filter + SCF + LPF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz FR FR FR +0.1/-4.3 +0.1/-3.3 +0.1/-3.7 dB dB dB Note 13. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs. DC CHARACTERISTICS (Ta = 25°C; VDD=AVDD = 4.5 ∼ 5.5V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V Low-Level Output Voltage D I F 0 / C D T I / S D A ( I o u t = 3 m A ) VOL 0.4 V V I n p u t L e a k a g e C u r r e n t (Note 14) Iin - - ± 10 μA Note 14. The current of the P/S pin is not included. The P/S pin has an internal pull-up resistor (typ.100kΩ). MS1088-E-01 2011/03 - 7 -
[AK4440] SWITCHING CHARACTERISTICS (Ta = 25°C; VDD=AVDD= +4.5 ∼ +5.5V; CL = 20pF) Parameter Symbol min typ max Units Master Clock Frequency D u t y C y c l e fCLK dCLK 2.048 36.864 MHz LRCK Frequency Normal Mode (TDM0= “0”, TDM1= “0”) Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 120 192 kHz kHz kHz TDM256 mode (TDM0= “1”, TDM1= “0”) Normal Speed Mode High time Low time fsn tLRH tLRL 1/256fs 1/256fs kHz ns ns TDM128 mode (TDM0= “1”, TDM1= “1”) Normal Speed Mode Double Speed Mode High time Low time fsn fsd tLRH tLRL 1/128fs 1/128fs kHz kHz ns ns Audio Interface Timing B I C K P e r i o d B I C K P u l s e W i d t h L o w P u l s e W i d t h H i g h B I C K “ ↑” t o L R C K E d g e (Note 15) L R C K E d g e t o B I C K “↑” ( Note 15) S D T I H o l d T i m e S D T I S e t u p T i m e tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS ns ns ns ns ns ns ns Control Interface Timing (3-wire Serial control mode): C C L K P e r i o d C C L K P u l s e W i d t h L o w P u l s e W i d t h H i g h C D T I S e t u p T i m e C D T I H o l d T i m e C S N H i g h T i m e tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling ( Note 16) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 0.3 0.3 400 kHz μs μs μs μs μs μs μs μs μs μs ns pF Note 15. BICK rising edge must not occur at the same time as LRCK edge. Note 16. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 17. I2C-bus is a trademark of NXP B.V. MS1088-E-01 2011/03 - 8 -
(Table 6), it is not necessary to set DFS1-0 bits. not support 128fs and 192fs of double speed mode. Table 1. Sampling Speed (Manual Setting Mode) Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode) (N/A: Not available)
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode) Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode) Table 5. Sampling Speed (Auto Setting Mode) Table 6. System Clock Example (Auto Setting Mode)
SDTI1-2 pins are latched on the rising edge of BICK.
2 H L 24-bit MSB Justified H/L ≥48fs Figure 8Normal 3 H H 24-bit I2S Compatible L/H ≥48fs Figure 9
5 L L 24-bit MSB Justified ↑ 256fs Figure 10TDM256 6 L H 24-bit I2S Compatible 256fs Figure 11↓
Table 7. Audio Data Formats (Parallel control mode) Table 8. Audio Data Formats (Serial control mode) (N/A: Not available)
Figure 9. Mode 3 Timing
256 BICK
32 BICK
Figure 10. Mode 5 Timing Figure 11. Mode 6 Timing Figure 12. Mode 7 Timing
128 BICK
Figure 13. Mode 8 Timing Figure 14. Mode 9 Timing Figure 15. Mode 10 Timing
is effective for changing the signal source without stopping the signal transmission. Normal Speed Mode: 1024 LRCK cycles (1024/fs). Double Speed Mode: 2048 LRCK cycles (2048/fs). Quad Speed Mode: 4096 LRCK cycles (4096/fs). (2) The analog output corresponding to a specific digital input has group delay, GD. Figure 18. Soft Mute Function
up. The AK4440 is in power-down mode until LRCK are input. after power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec. (2) Register writings are valid after 10ms (max). (3) When internal reset is released, approximately 20us after a MCLK input, the internal analog circuit is powered-up. Figure 19. System Reset Diagram
typ). When the MCLK, LRCK and BICK are restarted, the AK4440 returns to normal operation mode. (1) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK or BICK is stopped). inputting the “0” data during this period. (4) The analog output corresponding to a specific digital input has group delay (GD). (5) No audible click noise occurs under normal conditions. Figure 20. Reset Timing Example
mode, the chip address is determined by the state of the CAD0 pin. In 3-wire mode, the chip address is fixed to “11”. Writing “0” to the RSTN bit resets the internal timing circuit, but the registers are not initialized.
- The AK4440 does not support read commands.
- When the state of the P/S pin is changed, the AK4440 should be reset by the RSTB bit = “0”.
- In serial control mode, the setting of parallel pins is invalid.
Figure 21. Control I/F Timing
[AK4440] ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 0 RSTN 01H Control 2 RRST 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE 02H Power Down Control 0 0 0 0 PW4 PW3 PW2 PW1 03H DEM Control 0 0 0 0 DEMA DEMB DEMC DEMD Note: For addresses from 04H to 1FH, data must not be written. Do not write the registers within 10msec after the power supplies are fed. All data can be written to the registers even if PW1-4 and RSTN bits are “0”. When RSTN bit goes to “0”, only inte rnal timing is reset, and the register s are not initialized to their default values. ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS TDM1 TDM0 DIF2 DIF1 DIF0 0 RSTN Default 1 0 0 0 1 0 0 1 RSTN: Internal timing reset 0: Reset. Any registers are not initialized. 1: Normal operation DIF2-0: Audio data interface modes (Table 8) Default: “010” TDM0-1: TDM Mode Select Mode TDM1 TDM0 BICK SDTI Sampling Speed Normal 0 0 32fs∼ 1-4 Normal, Double, Quad Speed TDM256 0 1 256fs fixed 1 Normal Speed TDM128 1 1 128fs fixed 1-2 Normal, Double Speed ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0 bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 RRST 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE Default 0 0 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft-muted DEM1-0: De-emphasis Response (Table 9, Table 10) Default: “01”, OFF DFS1-0: Sampling speed control (Table 1) 00: Normal speed 01: Double speed MS1088-E-01 2011/03 - 24 -
[AK4440] 10: Quad speed When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter RRST: All registers are initialized. 0: Normal Operation 1: Reset. All registers are initialized. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Power Down Control 0 0 0 0 PW4 PW3 PW2 PW1 Default 0 0 0 0 1 1 1 1 PW4-1: Power-down control (0: Power-down, 1: Power-up) PW1: Power down control of DAC1 PW2: Power down control of DAC2 PW3: Power down control of DAC3 PW4: Power down control of DAC4 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H DEM Control 0 0 0 0 DEMA DEMB DEMC DEMD Default 0 0 0 0 0 0 0 0 DEMA-D: De-emphasis Enable bit of DAC1/2/3/4 0: Disable 1: Enable MS1088-E-01 2011/03 - 25 -
Figure 30. Typical Connection Diagram (3-wire Serial Control Mode) positive pole of the capacitor should be connected to CP pin and VSS2 pin.
- All input pins except for the P/S pin should not be left floating.
- Grounding and Power Supply Decoupling
VDD and AVDD are supplied from the analog supply and should be separated from the system digital supply. sequence between VDD and AVDD is not critical. can reduce noise beyond the audio passband. data). The ideal output is 0V (VSS) voltage for 000000H (@24bit data). The DC offset is ±60mV or less. Figure 31. External 1st order LPF Circuit Example1
[AK4440] PACKAGE Detail A NOTE: Dimension "*" does not include mold flash. 0.22 ±0.1 0.65 *9.7 ±0.1 1.5MAX A 1 15 1630 30pin VSOP (Unit: mm) 5.6±0.1 7.6±0.2 0.45±0.2 -0.05 +0.10 0.3 0.150.12 M 0.08 1.2±0.10 0.10 +0.10 -0.05 ■ Package & Lead frame material Package molding compound: Epoxy, Halogen (bromine and chlorine) free Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate RoHS Compliance *All integrated circuits form Asahi Kasei Microdevices Corporation (AKM) assembled in “lead-free” packages are fully compliant with RoHS. MS1088-E-01 2011/03 - 29 -
[AK4440] MARKING AKM AK4440EF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents 09/10/15 00 First Edition 11/03/01 01 Error Correction 28 1. Grounding and Power Supply Decoupling The description was changed. MS1088-E-01 2011/03 - 30 -
[AK4440] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these product s, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, ap plication circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. You are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to cust oms and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM pr oducts, who distributes, di sposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and a ll responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1088-E-01 2011/03 - 31 -