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[AK4438] 016001925-E-00 2016/03 - 1 - 1. General Description The AK4438 is an 8-channel 32-bit DAC which corresponds to digital audio systems. An internal circuit includes newly developed 32 -bit Digital Filter achieving short group delay and high quality sound. It corresponds to a 768kHz PCM input at maximum, suitable for play backing high resolution audio sources that are becoming widespread in network audios, USB -DACs and Car Audio Systems. In addition, “OSR-Doubler” technology is newly adopted, making the AK44 38 capable of supporting wide range signals and achieving low out -of-band noise while realizing low power consumption. Moreover, the AK4438 has five types of 32-bit digital filters, realizing simple and flexible sound making in wide range of applications. Application: AV Receivers, CD/SACD Players, Network Audio s, USB DACs, USB Headphones, Sound Plate/Bars, Car Audios, Automotive External Amplifiers, Measuring Instruments and Control Systems. 2. Features 1. 8ch 32bit DAC - 256 x Over sampling - 32-bit High Quality Sound Short Delay Digital Filter - Single-ended Output, Smoothing Filter - THD+N: 91dB - DR, S/N: 108dB - Channel Independent Digital Volume Control (0dB～-127dB, 0.5dB Step, Mute) - Soft Mute - De-emphasis Filter (supporting 32kHz, 44.1kHz and 48kHz) - I/F Format: MSB justified, LSB justified, I2S, TDM - Zero Detection 2. Sampling Frequency - Normal Speed Mode: 8kHz to 48kHz - Double Speed Mode: 48kHz to 96kHz - Quad Speed Mode: 96kHz to 192kHz - Oct Speed Mode: 384kHz - Hex Speed Mode: 768kHz 3. Master Clock 256fs, 384fs or 512fs, 768fs (Normal Speed Mode: fs=8kHz 48kHz) 256fs, 384fs (Double Speed Mode: fs=48kHz 96kHz) 128fs, 192fs (Quad Speed Mode: fs=96kHz 192kHz) 64fs, 96fs (Oct Speed Mode: fs=384kHz) 32fs, 48fs (Hex Speed Mode: fs=768kHz) 4. P Interface: 3-wire Serial/ I2C bus (Ver 1.0, 400kHz mode) 5. Power Supply - Analog Supply: AVDD = 3.0 3.6V - In/Output Buffer: TVDD = 1.7 3.6V - Integrated LDO for Digital Power Supply 8. Power Consumption: 31mA (fs=48kHz) 9. Operating Temperature: Ta = - 40 105℃ 10. Package: 32-pin QFN(0.5mm pitch) 108dB 768kHz 32bit 8-Channel Audio DAC AK4438
[AK4438] 016001925-E-00 2016/03 - 2 - 3. Table of Contents
- Block Diagram and Functions
Figure 1. Block Diagram
- Pin Configurations and Functions
29 I2C
30 TVDD
Figure 2. Pin Configurations
[AK4438] 016001925-E-00 2016/03 - 5 - ■ Pin Functions No. Pin Name I/O PD state Function
1 MCLK I Hi-z External Master Clock Input Pin
2 BICK I Hi-z Audio Serial Data Clock Pin
3 LRCK I Hi-z Input Channel Clock Pin
4 SDTI1 I Hi-z Audio Serial Data Input
5 SDTI2 I Hi-z Audio Serial Data Input
6 SDTI3 I Hi-z Audio Serial Data Input
7 SDTI4 I Hi-z Audio Serial Data Input
8 DZF O 50kΩ
Zero Input Detect in I2C Bus or 3-wire serial control mode
9 PDN I Hi-z
Power-Down & Reset Pin. When “L”, the AK4438 is powered-down and the control registers are reset to default state.
10 SMUTE I Hi-z
Soft Mute Pin in Parallel control mode. When this pin is changed to “H”, soft mute cycle is initiated. When returning “L”, the output mute releases. CAD1 I Chip Address 1 Pin in I2C Bus or 3-wire serial control mode SDA I/O Hi-z Control Data Input Pin in I2C Bus serial control mode CDTI I Control Data Input Pin in 3-wire serial control mode TDM0 I TDM Mode select pin in Parallel control mode. SCL I Hi-z Control Data Clock Pin in I2C Bus serial control mode CCLK I Control Data Clock Pin in 3-wire serial control mode TDM1 I TDM Mode select pin in Parallel control mode. CAD0_I2C I Hi-z Chip Address 0 Pin in I2C Bus serial control mode CSN I Chip Select Pin in 3-wire serial control mode DIF I Audio Data Format Select in Parallel control mode. “L”: 32bit MSB, “H”: 32bit I2S
14 PS I Hi-z
(I2C pin = “H”) Control Mode Select Pin “L”: I2C Bus serial control mode, “H”: Parallel control mode. CAD0_SPI I (I2C pin = “L”) Chip Address 0 Pin in 3-wire serial control mode
15 AOUTL1 O Hi-z Lch Analog Output Pin
16 AOUTR1 O Hi-z Rch Analog Output Pin
17 AOUTL2 O Hi-z Lch Analog Output Pin
18 AOUTR2 O Hi-z Rch Analog Output Pin
19 VREFH - Hi-z Positive Voltage Reference Input Pin, AVDD
20 VREFL - Hi-z Negative Voltage Reference Input Pin, VSS2
21 VCOM O 500Ω
Common Voltage Output Pin, AVDDx1/2 Large external capacitor around 2.2µF is used to reduce power-supply noise.
22 VSS2 - - Analog Ground Pin
23 AVDD - - Analog Power Supply Pin, 3.0V3.6V
24 AOUTL3 O Hi-z Lch Analog Output Pin
25 AOUTR3 O Hi-z Rch Analog Output Pin
26 AOUTL4 O Hi-z Lch Analog Output Pin
27 AOUTR4 O Hi-z Rch Analog Output Pin
28 TEST - 25kΩ
This pin must be connected to VSS1.
29 I2C I Hi-z
“L”: 3-wire serial control mode “H”: I2C Bus serial control mode or Parallel control mode. 30 TVDD - - Digital Power Supply Pin, 1.7V3.6V
31 VSS1 - - Digital Ground Pin
32 LDOO O 580Ω
LDO Output Pin. This pin must be connected to ground with 2.2uF ±50%. Note 1. All digital input pins must not be allowed to float.
[AK4438] 016001925-E-00 2016/03 - 6 - ■ Handling of Unused Pin Unused I/O pins must be connected appropriately. Classification Pin Name Setting Analog AOUTL1-4, AOUTR1-4 Open Digital DZF Open SDTI1-4 Connect to VSS1
[AK4438] 016001925-E-00 2016/03 - 7 - 6. Absolute Maximum Ratings (VSS1=VSS2=0V; Note 2) Parameter Symbol Min. Max. Unit Power Supplies Analog Digital Difference (VSS1 ~ 2) AVDD TVDD ΔGND -0.3 -0.3 -0.3 4.3 4.3 0.3 V V V Input Current (any pins except for supplies) IIN - 10 mA Digital Input Voltage VIND -0.3 TVDD+0.3 V Ambient Temperature (power applied) Ta -40 105 C Storage Temperature Tstg -65 150 C Note 2. All voltages with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane. Note 3. The maximum Digital input voltage is smaller value between (LVDD+0.3)V and 4.3V. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 7. Recommended Operation Conditions (VSS1=VSS2=0V; Note 2) Parameter Symbol Min. Typ. Max. Unit Power Supplies Analog Digital AVDD TVDD 3.0 1.7 3.3 3.3 3.6 3.6 V V Voltage Reference (Note 5) “H” voltage reference “L” voltage reference VREFH VREFL AVDD0.5 VSS2 AVDD V V Note 4. The power up sequence between AVDD and TVDD is not critical. Note 5. The VREFL pin must be connected to VSS2. Note 6. Do not turn off the power supply of the AK4438 with the power supply of the peripheral device turned on. When using the I2C interface, pull-up resistors of SDA and SCL pins should be connected to TVDD or less voltage. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
[AK4438] 016001925-E-00 2016/03 - 8 - 8. Electrical Characteristics (Ta=25C; AVDD =TVDD=3.3V; VSS1=VSS2 =0V; VREFH=AVDD; fs=48kHz; BICK=64fs; Signal Frequency=1kHz; 32bit Data; Measurement Frequency=20Hz20kHz at 48kHz, 20Hz~40kHz at fs=96kHz, 20Hz~40kHz at fs=192kHz, unless otherwise specified.) Parameter Min. Typ. Max. Unit DAC Analog Output Characteristics Resolution 32 bit Output Voltage (Note 7) 2.55 2.83 3.11 Vpp S/(N+D) (0dBFS) fs=48kHz 80 91 dB fs=96kHz - 89 dB fs=192kHz - 89 dB Dynamic Range (-60dBFS) fs=48kHz (A-weighted) 104 108 dB fs=96kHz - 101 dB fs=192kHz - 101 dB S/N fs=48kHz (A-weighted) 104 108 dB fs=96kHz - 101 dB fs=192kHz - 101 dB Interchannel Isolation 90 110 dB Interchannel Gain Mismatch 0 0.7 dB Load Resistance (Note 8) 10 k Load Capacitance 30 pF Power Supply Rejection (Note 9) - 50 - dB Note 7. Full-scale output voltage. The output voltage is always proportional to AVDD (AVDD x 0.86). Note 8. AC Load Note 9. This is a value when applying a 1kHz 50mVpp sine wave to AVDD. Parameter Min. Typ. Max. Unit Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD fs=48kHz, 96kHz, 192kHz TVDD fs=48kHz TVDD fs=96kHz TVDD fs=192kHz Power-down mode (PDN pin = “L”) (Note 10) AVDD+TVDD 3.4 4.9 8.0 4.5 6.4 10.4 200 mA mA mA mA µA Note 10. Quiescent Current. All digital input pins including clock pins are fixed to VSS.
[AK4438] 016001925-E-00 2016/03 - 9 - 9. Filter Characteristics (fs=48kHz) (Ta= -40 +105C; AVDD =3.0 3.6V, TVDD=1.7 3.6V; DEM=OFF) ■ Sharp Roll-Off Filter (SD bit = “0”, SLOW bit = “0”) fs=44.1kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 20.0 kHz 3.0dB PB 21.5 kHz Passband Ripple (Note 12) PR -0.0032 0.0032 dB Stopband (Note 11) SB 24.1 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 26.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -0.26 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 43.5 kHz 3.0dB PB 46.8 kHz Passband Ripple (Note 12) PR -0.0032 0.0032 dB Stopband (Note 11) SB 52.5 0 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 26.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -0.53 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 87.0 kHz 3.0dB PB 93.6 kHz Passband Ripple (Note 12) PR -0.0032 0.0032 dB Stopband (Note 11) SB 105 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 26.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -1.9 0.1 dB Note 11. The pass band and stop band frequencies scale with fs. For example, PB=0.4535×fs, SB=0.546×fs. Note 12. It is the pass band gain amplitude of the double over sampling filter at the first step of the Interpolator. Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24/32bit data of both channels to input register to the output of analog signal. Note 14. The output level is assumed as 0dB when inputting a 1kHz 0dB sine wave. *Digital filter characteristics are based on simulation results.
[AK4438] 016001925-E-00 2016/03 - 10 - ■ Slow Roll-Off Filter (SD bit = “0”, SLOW bit = “1”) fs=44.1kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 15) 0.05dB PB 0 8.1 kHz 3.0dB PB 18.2 kHz Passband Rippl e (Note 12) PR -0.043 0.0032 dB Stopband (Note 15) SB 39.2 kHz Stopband Attenuation (Note 14) SA 73 dB Group Delay (Note 13) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.06 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 15) 0.05dB PB 0 17.7 kHz 3.0dB PB 39.5 kHz Passband Ripple (Note 12) PR -0.043 0.043 dB Stopband (Note 15) SB 85.3 kHz Stopband Attenuation (Note 14) SA 73 dB Group Delay (Note 13) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.23 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 15) 0.05dB PB 0 35.5 kHz 3.0dB PB 79.0 kHz Passband Ripple (Note 12) PR -0.043 0.043 dB Stopband (Note 15) SB 171 kHz Stopband Attenuation (Note 14) SA 73 dB Group Delay (Note 13) GD - 6.3 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.90 0.1 dB Note 15. The pass band and stop band frequencies scale with fs. For example, PB=0.185×fs, SB=0.888×fs.
[AK4438] 016001925-E-00 2016/03 - 11 - ■ Short Delay Sharp Roll-Off Filter (SD bit = “1”, SLOW bit = “0”) fs=44.1kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 20.0 kHz 3.0dB PB 21.5 kHz Passband Ripple (Note 12) PR -0.0031 0.0031 dB Stopband (Note 11) SB 24.1 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 5.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -0.26 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 43.5 kHz 3.0dB PB 46.8 kHz Passband Ripple (Note 12) PR -0.0031 0.0031 dB Stopband (Note 11) SB 52.5 0 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 5.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -0.53 0.1 dB fs=192kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 11) 0.05dB PB 0 87.0 kHz 3.0dB PB 93.6 kHz Passband Ripple (Note 12) PR -0.0031 0.0031 dB Stopband (Note 11) SB 105 kHz Stopband Attenuation (Note 14) SA 80 dB Group Delay (Note 13) GD - 5.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -1.9 0.1 dB
[AK4438] 016001925-E-00 2016/03 - 12 - ■ Short Delay Slow Roll-Off Filter (SD bit = “1”, SLOW bit = “1”) fs=44.1kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 16) 0.05dB PB 0 11.1 kHz 3.0dB PB 19.4 kHz Passband Ripple (Note 12) PR -0.05 0.05 dB Stopband (Note 16) SB 38.1 kHz Stopband Attenuation (Note 14) SA 82 dB Group Delay (Note 13) GD - 4.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.06 0.1 dB fs=96kHz Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 16) 0.05dB PB 0 24.2 kHz 3.0dB PB 42.1 kHz Passband Ripple (Note 12) PR -0.05 0.05 dB Stopband (Note 16) SB 83.0 kHz Stopband Attenuation (Note 14) SA 82 dB Group Delay (Note 13) GD - 4.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.23 0.1 dB fs=192kH Parameter Symbol Min. Typ. Max. Unit Digital Filter Passband (Note 16) 0.05dB PB 0 48.4 kHz 3.0dB PB 84.3 kHz Passband Ripple (Note 12) PR -0.05 0.05 dB Stopband (Note 16) SB 165.9 kHz Stopband Attenuation (Note 14) SA 82 dB Group Delay (Note 13) GD - 4.8 - 1/fs Digital Filter + SCF + SMF (Note 14) Frequency Response : 0 20.0kHz -5.90 0.1 dB Note 16. The pass band and stop band frequencies scale with fs. For example, PB=0.252×fs, SB=0.864×fs.
[AK4438] 016001925-E-00 2016/03 - 13 - 10. DC Characteristics (Ta= -40 +105C; AVDD =3.0 3.6V, TVDD=1.7 3.6V) Parameter Symbol Min. Typ. Max. Unit TVDD=1.7V 3.0V High-Level Input Voltage Low-Level Input Voltage VIH1 VIL1 80%TVDD 20%TVDD V V TVDD=3.0V 3.6V High-Level Input Voltage Low-Level Input Voltage VIH2 VIL2 70%TVDD 30%TVDD V V High-Level Output Voltage (DZF pins: Iout= -100µA) Low-Level Output Voltage (DZF pin : Iout= 100µA) (SDA pin, 2.0V TVDD 3.6V: Iout= 3mA) (SDA pin, 1.7V TVDD 2.0V: Iout= 3mA) VOH VOL1 VOL2 VOL3 TVDD0.5 0.5 0.4 20%TVDD V V V V Input Leakage Current Iin - - 10 A
[AK4438] 016001925-E-00 2016/03 - 14 - 11. Switching Characteristics Parameter Symbol Min. Typ. Max. Unit Master Clock Timing External Clock 256fsn: Pulse Width Low Pulse Width High 384fsn: Pulse Width Low Pulse Width High 512fsn, 256fsd, 128fsq, 64fso, 32fsh: Pulse Width Low Pulse Width High 768fsn, 384fsd, 192fsq, 96fso, 48fsh: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH fCLK tCLKL tCLKH 2.048 3.072 4.096 6.144 12.288 18.432 24.576 36.864 MHz ns ns MHz ns ns MHz ns ns MHz ns ns LRCK Timing (Slave mode) Stereo mode (TDM1-0 bits = “00”) Normal Speed Mode Double Speed Mode Quad Speed Mode Oct speed mode Hex speed mode Duty Cycle fsn fsd fsq fso fsh Duty 384 768 192 kHz kHz kHz kHz kHz TDM128 mode (TDM1-0 bits = “01”) LRCK frequency “H” time “L” time fsn fsd fsq tLRH tLRL 1/128fs 1/128fs 192 kHz kHz kHz ns ns TDM256 mode (TDM1-0 bits = “10”) LRCK frequency “H” time “L” time fsn fsd tLRH tLRL 1/256fs 1/256fs kHz kHz ns ns TDM512 mode (TDM1-0 bits = “11”) LRCK frequency “H” time “L” time fsn tLRH tLRL 1/512fs 1/512fs kHz ns ns
[AK4438] 016001925-E-00 2016/03 - 15 - Parameter Symbol Min. Typ. Max. Unit Audio Interface Timing Stereo mode (TDM1-0 bits = “00”) BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode Oct Speed Mode Hex Speed Mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCK tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/256fsn 1/128fsd 1/64fsq 1/64fso 1/64fsh ns ns ns ns ns ns ns ns ns TDM128 mode (TDM1-0 bits = “01”) BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/128fsd 1/128fsq ns ns ns ns ns ns ns ns ns TDM256 mode (TDM1-0 bits = “10”) BICK Period Normal Speed Mode Double Speed Mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/256fsn 1/256fsd ns ns ns ns ns ns ns ns TDM512 mode (TDM1-0 bits = “11”) BICK Period Normal Speed Mode BICK Pulse Width Low BICK Pulse Width High LRCK Edge to BICK “” (Note 17) BICK “” to LRCK Edge (Note 17) SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/512fsn ns ns ns ns ns ns ns Note 17. BICK rising edge must not occur at the same time as LRCK edge.
[AK4438] 016001925-E-00 2016/03 - 16 - Parameter Symbol Min. Typ. Max. Unit Control Interface Timing (3-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 18) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Pulse Width of Spike Noise Suppressed by Input Filter Capacitive load on bus fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tSP Cb 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 1.0 0.3 400 kHz ns pF Power-down & Reset Timing PDN Pulse Width (Note 19) PDN Reject Pulse Width tAPD tRPD 800 ns ns Note 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Note 19. The AK4438 can be reset by setting the PDN pin to “L” upon power-up. The PDN pin must held “L” for more than 800ns for a certain reset. The AK4438 is not reset by the “L” pulse less than 50ns. Note 20. I2C-bus is a trademark of NXP B.V.
[AK4438] 016001925-E-00 2016/03 - 21 - 12. Functional Descriptions ■ System Clock The external clocks which are required to operate the AK4438 are MCLK, LRCK and BICK. MCLK should be synchronized with LRCK and BICK but the phase is not critical. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit= “0”: Default), the sampling speed is set by DFS2-0 bit (Table 1). The frequency of MCLK at each sampling speed is set automatically (Table 2, Table 3). In Auto Setting Mode (ACKS bit= “1”), as MCLK frequency is detected automatically (Table 4) and the internal master clock attains the appropriate frequency (Table 5), so it is not necessary to set DFS2-0 bits. After exiting reset at power-up (PDN pin = “L” →“H”), the AK4438 is in power-down mode until MCLK and LRCK are input. The AK4438 is set to Manual Setting Mode at power-up (PDN pin = “L” →“H”). When changing the clock, the AK4438 must be reset by the PDN pin or RSTN bit. If the clock is stopped, a click noise occurs when restarting the clock. Mute the digital output externally if the click noise affects system applications.
- Manual Setting Mode (ACKS bit = “0”)
MCLK frequency corresponding to each sampling speed should be provided externally (Table 2, Table 3). changed, the AK4438 should be reset by RSTN bit. Table 1. Sampling Speed (Manual Setting Mode) Table 2. System Clock Example (Manual Setting Mode) Table 3. System Clock Example (Manual Setting Mode)
- Auto Setting Mode (ACKS bit = “1”)
Table 4. Sampling Speed (Auto Setting Mode) Table 5. System Clock Example (Auto Setting Mode) Table 6. System Clock Example (Auto Setting Mode) Table 7. Relationship of DR, S/N and MCLK frequency (fs = 44.1kHz)
DAC3(SDTI3) and DAC4(SDTI4) by register settings.
1 Normal Speed Mode 0 1 OFF (default)
2 Normal Speed Mode 1 0 48kHz
3 Normal Speed Mode 1 1 32kHz
Table 8. De-emphasis Control
[AK4438] 016001925-E-00 2016/03 - 25 - ■ Audio Interface Format TDM1-0 bits, DIF2-0 bits, SDS2-0 bits, TDM1-0 pins and DIF pin settings should not be changed during operation. [1] PCM Mode Normal Mode (TDM1-0 bit=“00”) Eight channels audio data is shifted in via the SDTI1-4 pins using BICK and LRCK inputs. Data is selected by SDS2-0 bits. Eight data formats are supported and selected by the DIF2-0 bits as shown in Table 9. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used in 16-bit and 20-bit MSB justified and Mode 6 can be used in 16-bit, 20-bit and 24-bit MSB justified formats by zeroing the unused LSBs. TDM128 Mode (TDM1-0 bit=“01”) Eight channels audio data is shifted in via the SDTI1-2 pins using BICK and LRCK inputs. Data is selected by SDS2-0 bits. The data input to the SDTI3-4 pins are ignored. BICK is fixed to 128fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 9. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. TDM256 Mode (TDM1-0 bit=“10”) Sixteen channels audio d ata is shifted in via the SDT I1-2 pins using BICK and LRCK input s. Data is selected by SDS2-0 bits. The data input to the SDTI3-4 pins are ignored. BICK is fixed to 256fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 9. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK. TDM512 Mode (TDM1-0 bit=“11”) Sixteen channels audio data is shifted in via the SDTI1 pin using BICK and LRCK inputs. Data is selected by SDS2-0 bits. The data input to the SDTI2-4 pins are ignored. BICK is fixed to 512fs. Six data formats are supported and selected by the DIF2-0 bits as shown in Table 9. In all formats the serial data is MSB first, 2's compliment format and is latched on the rising edge of BICK.
Note 21. BICK that is input to each channel must be longer than the bit length of setting format. Table 9. Audio Data Format
128 BICK
32 BICK
Figure 17. Mode 8/11/12 Timing Figure 18. Mode 9/13 Timing Figure 19. Mode 10 Timing
256 BICK
Figure 20. Mode 14/17/18 Timing Figure 21. Mode 15/19 Timing Figure 22. Mode 16 Timing
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
Figure 23. Mode 20/23/24 Timing Figure 24. Mode 21/25 Timing Figure 25. Mode 22 Timing
SDS2-0 bits control the playback channel of each DAC. Figure 26. Data Slot in Normal Mode Figure 27. Data Slot in TDM128 Mode Figure 28. Data Slot in TDM256 Mode
512 BICK
Figure 29. Data Slot in TDM512 Mode
Table 10. Data Select
filters are selected by SD bit, SLOW bit and SSLOW bit. **Table 11. Digital Filter Setting (*: don’t care)**
0 Not zero L
1 Not zero H
Not zero: One of the zero detection channels set by L1-4 bits and R1-4 bits does not detect zero. Zero detect: All zero detection channels set by L1-4 bits and R1-4 bits detect zero. Table 12. DZF Pin Function
each DAC1-4 can be set by ATT7-0 bits (register 0A-11H), respectively (Table 13). Table 13. Attenuation level of Digital Attenuator transition between set values is a soft transition in Mode0/1/2 eliminating switching noise in the transition. Table 14. Transition Time of Digital Volume @fs=48kHz) from FFH to 00H. If the PDN pin goes to “L”, ATT7-0 bits are initialized to FFH. immediately without soft transition.
Table 15. Output Select for DAC1 Table 16. Output Select for DAC2
Table 17. Output Select for DAC3 Table 18. Output Select for DAC4
stopping the signal transmission. (2) The analog output corresponding to the digital input has group delay (GD). discontinued and returned to ATT level by the same cycle. DZF pin goes to “H”. The DZF pin immediately returns to “L” if input data are not zero. Figure 30. Soft Mute Function and Zero Detection
acknowledge (ACK) in error status. 1 Internal Reference Voltage Error Internal reference voltage is not powered up. Table 19. Error Detection valid in 1ms. The AK4438 is in power-down state until MCLK and LRCK input.
floating (Hi-Z) state. Power-up and power-down timings are shown in Figure 31. (1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 800ns. (2) After PDN pin = “H”, the internal LDO and VCOM power-up. The internal registers are initialized. Register writing is available in 1msec after PDN pin = “H”. (3) The analog output corresponding to digital input has group delay (GD). (4) Analog outputs are floating (Hi-Z) in power down mode. (5) Click noise occurs at an edge of PDN signal. This noise is output even if “0” data is input. (6) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”). The timing example is shown in this figure. (8) The DZF pin outputs “L” in internal power-down mode. Figure 31. Pin Power Down/Up Sequence Example
Table 20. Power OFF and Reset Function
reset by bit settings. Figure 32 shows a timing example of power-on and power-down. (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs are floating (Hi-Z) in power down mode. (5) Mute the analog output externally if the click noise (3) adversely affect system performance. (6) The DZF pin outputs “L”, in power down mode (PW4-1 bits = “0000”). Figure 32. Power-off/on Sequence Example
LRCK) are input. Figure 33 shows an example of reset sequence by RSTN bit. (1) he analog output corresponding to digital input has group delay (GD). (2) Analog outputs are VCOM in power down mode. “1” to the internal RSTN bit “1”. Figure 33. Reset Sequence Example
reset state and starts the operation. Zero detect function is disable when MCLK is stopped. (1) After AVDD and TVDD are powered-up, the PDN pin should be “L” for 800ns. (2) The analog output corresponding to digital input has group delay (GD). (3) When MCLK is stopped, analog outputs go to VCOM voltage. “0” data during this period. inputs. This noise occurs even when “0” data is input. example is shown in this figure. Figure 34. Reset Sequence Example2
PCM mode and a rising edge of LRCK in I2C mode. shows a synchronization sequence by RSTN bit. (1) Refer to Table 14 internal transition time of ATT. (3) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset. (4) Click noise occurs when the internal counter is reset. This noise is output even if “0” data is input. Mute the analog output externally if this click noise adversely affects system performance. even if the synchronization function is enabled. Figure 35. Clock Synchronization Sequence with Continuous Zero Data
= “H”. Figure 36 shows synchronization sequence with RSTN bit. rising edge of RSTN bit. During this period the synchronization function is enabled. (2) Internal data is fixed to “0” for 4~5/fs forcibly when the internal counter is reset. when writing “0” data to RSTN bit, “0” period should be longer than the GD period. (4) It takes 3~4/fs to fall down and 2~3/fs to rise up for the internal RSTN signal from RSTN bit writing. synchronization function becomes enabled immediately by setting RSTN bit = “0”. Figure 36. Clock Synchronization Sequence by RSTN bit
operate in default setting of registers. The system clock is always in auto setting mode. Audio interface format of the parallel mode is controlled by TDM1-0 and DIF pins (Table 21). Zero detection function and functions set by registers are not available in parallel mode. Table 21. Parallel Mode The soft mute operation is controlled by SMUTE pin (Figure 30).
*Register writings are not available when the PDN pin = “L”. a low-to-high transition of CSN. The clock speed of CCLK is 5MHz (max). is reset by setting RSTN bit = “0” but register values are not initialized. Figure 37. Control I/F Timing
- The AK4438 does not support read commands in 3-wire serial control mode.
[AK4438] 016001925-E-00 2016/03 - 52 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN 01H Control 2 0 0 SD DFS1 DFS0 DEM11 DEM10 SMUTE 02H Control 3 0 0 0 0 MONO1 DZFB SELLR1 SLOW 03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 DFS2 SSLOW 06H - 0 0 0 0 0 0 0 0 07H Control 6 L3 R3 L4 R4 0 0 0 SYNCE 08H Control 7 L1 R1 L2 R2 0 0 0 0 09H - 0 0 0 0 0 0 0 0 0AH Control 8 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM21 DEM20 0BH Control 9 ATS1 ATS0 0 SDS0 PW4 PW3 0 0 0CH Control 10 INVR4 INVL4 INVR3 INVL3 0 0 0 0 0DH Control 11 MONO4 MONO3 MONO2 0 SELLR4 SELLR3 0 0 0EH Control 12 DEM41 DEM40 DEM31 DEM30 0 0 0 0 0FH L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 10H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 11H L3ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 12H R3ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 13H L4ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 14H R4ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Notes: Data must not be written into addresses from 15H to 1FH. The bit defined as 0 must contain a “0” value. When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset, but registers are not initialized.
[AK4438] 016001925-E-00 2016/03 - 53 - ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 1 RSTN: Internal Timing Reset 0: Reset The DZF pin goes “H” but register values are not initialized. 1: Normal Operation (default) DIF2-0: Audio Data Interface Modes (Table 9) Default value is “110” (Mode 6: 32-bit MSB justified). ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode (default) 1: Enable, Auto Setting Mode When ACKS bit = “1”, the MCLK frequency is detected automatically. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 0 0 SD DFS1 DFS0 DEM11 DEM10 SMUTE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 1 0 SMUTE: Soft Mute Enable. 0: Normal Operation (default) 1: DAC outputs soft-muted. DEM11-0: DAC1 De-emphasis Response (Table 8) Default value is “01” (OFF). DFS2-0: Sampling Speed Control (Table 1) Default value is “000” (Normal Speed). A click noise occurs when switching DFS2-0 bits setting. SD: Short delay Filter Enable. (Table 11) 0: Sharp roll off filter or Slow roll off filter 1: Short delay Sharp roll off filter or Short delay Slow roll off filter (default)
[AK4438] 016001925-E-00 2016/03 - 54 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Control 3 0 0 0 0 MONO1 DZFB SELLR1 SLOW R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SLOW: Slow Roll-off Filter Enable (Table 11) 0: Sharp Roll-off Filter (default) 1: Slow Roll-off Filter SELLR1: The data selection of DAC1 (Table 15) Default value is “0” DZB: Inverting Enable of DZF (Table 12) 0: DZF pin goes “H” at Zero Detection (default) 1: DZF pin goes “L” at Zero Detection MONO1: DAC1 enters monaural output mode when MONO bit = “1” (Table 15). 0: Stereo mode (default) 1: MONO mode Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 ATT7-0: Attenuation Level (Table 13) Default value is “FF” (0dB) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 DFS2 SSLOW R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SSLOW: Digital Filter bypass mode Enable (Table 11) 0: Disable (default) 1: Enable DFS2-0: Sampling Speed Control (Table 1) Default value is “000” (Normal Speed). A click noise occurs when switching DFS2-0 bits setting. SELLR2: The data selection of DAC2 (Table 16) Default value is “0” INVL1: AOUTL1 Output Phase Inverting Bit (Table 15) INVR1: AOUTR1 Output Phase Inverting Bit (Table 15) INVL2: AOUTL2 Output Phase Inverting Bit (Table 16) INVR2: AOUTR2 Output Phase Inverting Bit (Table 16) 0: Normal (default) 1: Inverted
[AK4438] 016001925-E-00 2016/03 - 55 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Control 6 L3 R3 L4 R4 0 0 0 SYNCE R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 1 SYNCE: SYNC Mode Enable 0: SYNC Mode Disable 1: SYNC Mode Enable (default) L3-4, R3-4: Zero Detect Flag Enable Bit for the DZF pin 0: Disable(default) 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Control 7 L1 R1 L2 R2 0 0 0 0 R/W R/W R/W RD RD R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 L1-2, R1-2: Zero Detect Flag Enable Bit for the DZF pin 0: Disable(default) 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Control 8 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM21 DEM20 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 1 DEM21-20: DAC2 De-emphasis Response (Table 8) Default value is “01”. (OFF) PW2-1: Power Down control for DAC PW2: Power management for DAC2 0: DAC2 power OFF 1: DAC2 power ON (default) PW1: Power management for DAC1 0: DAC1 power OFF 1: DAC1 power ON (default) SDS2-0: DAC1-4 Data Select 0: Normal Operation 1: Output Other Slot Data (Table 10) Default value is “000”. TDM1-0: TDM Mode Select (Table 9) Default value is “00”.
[AK4438] 016001925-E-00 2016/03 - 56 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0BH Control 9 ATS1 ATS0 0 SDS0 PW4 PW3 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 PW4-3: Power Down control for DAC PW4: Power management for DAC4 0: DAC4 power OFF 1: DAC4 power ON (default) PW3: Power management for DAC3 0: DAC3 power OFF 1: DAC3 power ON (default) SDS2-0: DAC1-4 Data Select 0: Normal Operation 1: Output Other Slot Data (Table 10) The default value is “000”. ATS1-0: Transition Time between Set Values of ATT7-0 bits (Table 14) The default value is “00”. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH Control 6 INVR4 INVL4 INVR3 INVL3 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 INVL3: AOUTL3 Output Phase Inverting Bit (Table 17) INVR3: AOUTR3 Output Phase Inverting Bit (Table 17) INVL4: AOUTL4 Output Phase Inverting Bit (Table 18) INVR4: AOUTR4 Output Phase Inverting Bit (Table 18) 0: Normal (default) 1: Inverted Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Control 6 MONO4 MONO3 MONO2 0 SELLR4 SELLR3 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 SELLR3: The data selection of DAC3 (Table 17) SELLR4: The data selection of DAC4 (Table 18) The default value is “0”. MONO2: DAC2 enters Mono output mode when MONO2 bit =“1”. (Table 16) MONO3: DAC3 enters Mono output mode when MONO3 bit =“1”. (Table 17) MONO4: DAC4 enters Mono output mode when MONO4 bit =“1”. (Table 18) 0: Stereo mode (default) 1: MONO mode
[AK4438] 016001925-E-00 2016/03 - 57 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Control 6 DEM41 DEM40 DEM31 DEM30 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 1 0 1 0 0 0 0 DEM31-30: DAC3 De-emphasis Response (Table 8) DEM41-40: DAC4 De-emphasis Response (Table 8) The default value is “01”, OFF Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 10H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 11H L3ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 12H R3ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 13H L4ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 14H R4ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 1 1 1 1 1 ATT7-0: Attenuation Level (Table 13) The default value is “FF”, (0dB)
- Recommended External Circuits
Figure 47. Typical Connection Diagram Note: The AK4438 integrates smoothing filters.
[AK4438] 016001925-E-00 2016/03 - 59 - 1. Grounding and Power Supply Decoupling The AK4438 requires careful attention to power supply and grounding arrangements. AVDD and TVDD are usually supplied from the analog supply of the system. If AVDD and TVDD are supplied separately, the power-up sequences between AVDD and TVDD is not critical. VSS1 and VSS2 must be connected to the same analog ground plane. System analog ground and digital ground should be wired separately and connected together as close as possible to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK4438 as possible. 2. Voltage Reference The differential voltage between VREFH pin and VREFL pin sets the analog output range. The VREFH pin is normally connected to AVDD, and the VREFL pin is normally connected to VSS2. VREFHL and VREFL should be connected with a 0.1µF ceramic capacitor and 10µF electrolytic capacitor as near as possible to the pin to eliminate the effects of high frequency noise. VCOM is a signal ground of this chip and output the voltage AVDDx1/2. A 2.2F ±50% ceramic capacitor attached between the VCOM pin and VSS2 eliminates the effects of high frequency noise. This capacitor should be as close to the pin as possible. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VREFH pin and the VCOM pin in order to avoid unwanted coupling into the AK4438. LDOO outputs 1.2V that is used for internal digital circuit. LDOO and VSS1 should be connected with a 2.2F ±50% ceramic capacitor as near as possible to the pin to stabilize internal LDO. No load current may be drawn from the VCOM pin. 3. Analog Output The output signal range is nominally 0.86 x VREFH Vpp centered around the VCOM voltage. The DAC input data format is 2’s complement. The output voltage is a positive full scale for 7FFFFFFFH (@32bit) and a negative full scale for 80000000H (@32bit). The ideal output is VCOM voltage for 00000000H (@32bit). The internal analog filters remove most of the noise generated by the delta-sigma modulator of DAC beyond the audio passband, in single-ended input mode. Normally, DC component is cut by an external capacitor since the DAC outputs have DC offsets of a few millivolts to the VCOM voltage.
- External Analog Outputs Circuit
cutoff frequency of HPF is shown below. Where the C is the external AC coupling capacitor and the R is load resistance. When C = 1μF and R = 10kΩ, then fs = 16Hz. Figure 48. Output Buffer Circuit Example
[AK4438] 016001925-E-00 2016/03 - 61 - 14. Package ■ Outline Dimensions 32-pin QFN (Unit: mm) ■ Material & Lead Finish Package molding compound: Epoxy, Halogen (Br and Cl) free Lead frame material: Cu Terminal surface treatment: Solder (Pb free) plate
[AK4438] 016001925-E-00 2016/03 - 62 - ■ Marking 4438 XXXX 1) Pin #1 indication 2) Date Code: XXXX (4 digits) 3) Marking Code: 4438 15. Ordering Guide ■ Ordering Guide AK4438VN -40 +105C 32-pin QFN (0.5mm pitch) AKD4438 Evaluation Board for the AK4438 16. Revision History Date (Y/M/D) Revision Reason Page Contents 16/03/04 00 First Edition
[AK4438] 016001925-E-00 2016/03 - 63 - IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this docum ent. You are fully responsible for use of such information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS. 2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily i njury, serious property damage or serious public impact , including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation , traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance -related fields. Do not use Product for the above use unless specifically agreed by AKM in writing. 3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. Do not use or otherwise make available the Product or related technology or any information contained in this document for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology prod ucts (mass destruction weapons). When exporting the Products or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. The Products and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations that regu late the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner whatsoever, any liability of AKM. 7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM.