AK4425A AKM | Alldatasheet
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Technical content
[AK4425A] AK4425A 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output GENERAL DESCRIPTION The AK4425A is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output. Using AKM’s multi bit modulator architecture, the AK4425A delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4425A integrates a combination of switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio applications, such as DVD, AV receiver system and set-top boxes. The AK4425A is offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24-Bit 8 times FIR Digital Filter Switched-Capacitor Filter with High Tolerance to Clock Jitter Single Ended 2Vrms Output Buffer Digital De-emphasis Filter: 32kHz, 44.1kHz or 48kHz Soft mute Digital Attenuator (Linear 256 Step) Control I/F: 3-wire Audio I/F format: 24Bit MSB justified, 24/20/16 LSB justified or I2S compatible Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode) 128fs, 192fs, 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) THD+N: -91dB Dynamic Range: 106dB Automatic Power-on Reset Circuit Power supply: +4.5 ∼ +5.5V Ta = -20 to 85°C Small Package: 16pin TSSOP (6.4mm x 5.0mm) MS1127-E-01 2011/03 - 1 -
[AK4425A] LRCK BICK SDTI Audio Data Interface MCLK ΔΣ Modulator AOUTL Interpolator SCF LPF AOUTR AVDD VSS2 De-emphasis Control Control Interface Clock Divider ΔΣ Modulator Interpolator SCF LPF Charge Pump CP CN VEE VSS1 VDD 1μ 1μ CSN CCLK CDTI Block Diagram MS1127-E-01 2011/03 - 2 -
[AK4425A] ■ Ordering Guide AK4425AET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch) AKD4425A Evaluation Board for AK4425A ■ Pin Layout
1 VDD
■ Compatibility with the AK4426 Functions AK4426 AK4425A Power Supply +4.5 ∼ +5.5V Å DC Offset ± 8mV ± 5mV THD+N -91dB Å DR 106dB Å DEM X Å SMUTE X Å Digital ATT X Å I/F Format 24-bit MSB/ I²S/ 24,20,16bitLSB Å Control I/F I²C Å Operating Temperature ET: -20 ∼ +85°C VT: -40 ∼ +85°C Å -: Not available X: Available MS1127-E-01 2011/03 - 3 -
[AK4425A] PIN/FUNCTION No. Pin Name I/O Function 1 VDD - Digital Circuit and Charge Pump Circuit Power Supply Pin: 4.5V∼5.5V
2 MCLK I Master Clock Input Pin
An external TTL clock must be input on this pin.
3 BICK I Audio Serial Data Clock Pin
4 SDTI I Audio Serial Data Input Pin
5 LRCK I L/R Clock Pin
6 CSN I Chip Select Pin
7 CCLK I Control Clock input Pin
8 CDTI I Control Data Input Pin
9 AOUTR O Rch Analog Output Pin
When power down, outputs VSS(0V, typ). 10 AVDD - Analog Block Power Supply Pin: 4.5V∼5.5V
11 VSS2 - Ground Pin2
12 AOUTL O Lch Analog Output Pin
When power down, outputs VSS(0V, typ).
13 VEE O
Negative Voltage Output Pin Connect to VSS1 with a 1.0 μF capacitor which is low ESR (Equivalent Series Resistance) over all temperatur e range. When this capacitor has the polarity, the positive polarity pin must be connected to the VSS1 pin. Non polarity capacitors can also be used.
14 CN I
Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0 μF capacitor which is low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin must be connect ed to the CP pin. Non polarity capacitors can also be used.
15 CP I
Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor which is low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin must be connected to the CP pin. Non polarity capacitors can also be used.
16 VSS1 - Ground Pin1
Note: All input pins except for the CN pin should not be left floating. MS1127-E-01 2011/03 - 4 -
[AK4425A] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 1) Parameter Symbol min max Units Power Supply VDD CVDD -0.3 -0.3 +6.0 +6.0 V V Input Current (any pins except for supplies) IIN - ±10 mA Input Voltage VIND -0.3 VDD+0.3 V Ambient Operating Temperature Ta -20 85 °C Storage Temperature Tstg -65 150 °C Note 1. All voltages with respect to ground. Note 2. VSS1, VSS2 connect to the same analog ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 1) Parameter Symbol min typ max Units Power Supply VDD AVDD +4.5 +5.0 VDD +5.5 V Note 3. AVDD should be equal to VDD *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS1127-E-01 2011/03 - 5 -
[AK4425A] ANALOG CHARACTERISTICS (Ta = 25°C; VDD=AVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) fs=44.1kHz, BW=20kHz -91 -84 dB fs=96kHz, BW=40kHz -91 - dB THD+N fs=192kHz, BW=40kHz -91 - dB Dynamic Range (-60dBFS with A-weighted. (Note 5) 100 106 dB S/N (A-weighted. (Note 6) 100 106 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0 0.5 dB DC Accuracy DC Offset (at output pin) -5 0 +5 mV Gain Drift 100 - ppm/°C Output Voltage (Note 7) 2.05 2.2 2.35 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 9) Normal Operation (fs≤96kHz) Normal Operation (fs=192kHz) Power-Down Mode (Note 10) 100 mA mA μA Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual. Note 5. 98dB for 16bit input data Note 6. S/N does not depend on input data size. Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD, AOUT (typ.@0dB) = 2.2Vrms × VDD/5. Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load. Note 9. The current into VDD and AVDD. Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS1(VSS2) or VDD(AVDD). MS1127-E-01 2011/03 - 6 -
[AK4425A] SHARP ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz; DEM = OFF; SLOW = “0”) Parameter Symbol min typ max Units Digital filter Passband ±0.05dB (Note 11) –6.0dB PB 0 22.05 20.0 kHz kHz Stopband (Note 11) SB 24.1 kHz Passband Ripple PR ± 0.02 dB Stopband Attenuation SA 54 dB Group Delay (Note 12) GD - 19.3 - 1/fs Digital Filter + LPF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.1kHz fs=96kHz fs=192kHz FR FR FR ± 0.05 ± 0.05 ± 0.05 dB dB dB Note 11. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. SLOW ROLL-OFF FILTER CHARACTERISTICS (Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”) Parameter Symbol min typ max Units Digital Filter Passband ±0.04dB (Note 13) -3.0dB PB 18.2 8.1 kHz kHz Stopband (Note 13) SB 39.2 kHz Passband Ripple PR ± 0.005 dB Stopband Attenuation SA 72 dB Group Delay (Note 12) GD - 19.3 - 1/fs Digital Filter + LPF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.kHz fs=96kHz fs=192kHz FR FR FR +0/-5 +0/-4 +0/-5 dB dB dB Note 13. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.185×fs (@±0.04dB), SB=0.888×fs. MS1127-E-01 2011/03 - 7 -
[AK4425A] DC CHARACTERISTICS (Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V Input Leakage Current Iin - - ± 10 μA SWITCHING CHARACTERISTICS (Ta = 25°C; VDD=AVDD = +4.5 ∼ +5.5V) Parameter Symbol min Typ max Units Master Clock Frequency Duty Cycle fCLK dCLK 2.048 11.2896 36.864 MHz LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 120 192 kHz kHz kHz Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 14) LRCK Edge to BICK “↑” (Note 14) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/64fsd 1/64fsq ns ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Note 14. BICK rising edge must not occur at the same time as LRCK edge. MS1127-E-01 2011/03 - 8 -
Table 1. Sampling Speed (Manual Setting Mode) Table 2. System Clock Example Table 3. Sampling Speed(Auto Setting Mode: Default)
Table 4. System Clock Example (Auto Setting Mode) Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) (Auto Setting Mode) on the rising edge of BICK. Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs. Table 6. Audio Data Format in Serial control mode
Figure 8. Mode 3 Timing
Table 8. ATT Transition Time level by the same cycle. The soft mute is effective for changing the signal source without stopping the signal transmission. (2) The analog output corresponding to the digital input has group delay, GD. returned to ATT level by the same cycle. Figure 11. Soft Mute function
up. The AK4425A is in power-down mode until LRCK are input. power up. Therefore, the power supply voltage must reach 80% VDD from 0.3V in less than 20msec. (2) Register writings are valid after 50ms (max). (3) When internal reset is released, approximately 20us after a MCLK input, the internal analog circuit is powered-up. (4) The digital circuit and charge pump circuit are powered-up in 2, 3 LRCK cycle when the analog circuit is powered-up. Figure 12. System Reset Diagram
typ). When the MCLK, LRCK and BICK are restarted, the AK4425A returns to normal operation mode. inputting the “0” data during this period. (2) The analog output corresponding to a specific digital input has group delay (GD). (3) No audible click noise occurs under normal conditions. (4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped). Figure 13. Reset Timing Example
Figure 14. 3-wire Serial Control I/F Timing
[AK4425A] ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN 01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE 02H Control 3 RRST 0 0 INVL INVR 0 0 0 03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Notes: Do not write any data to the register over 05H directly. Writing “1” to D7 and D6 of Addr01H and D2 of Addr02H is ignored. The bits defined as 0 must contain a “0” value. When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default values. All data can be written to the register even if PW or RSTN bit is “0”. Do not write the registers within 50msec after the power supplies are fed. MS1127-E-01 2011/03 - 20 -
[AK4425A] ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN default 1 0 0 0 1 0 1 1 RSTN: Internal timing reset control 0: Reset. All registers are not initialized. 1: Normal Operation The click noise, which occurs when MCLK frequency or DFS is changed, can be reduced by RSTN bit. PW: Power down control 0: Power down. All registers are not initialized. 1: Normal Operation DIF2-0: Audio data interface formats (Table 6) Initial: “010”, Mode 2 ACKS: Master Clock Frequency Auto Setting Mode Enable 0: Disable, Manual Setting Mode 1: Enable, Auto Setting Mode Master clock frequency is detected automatically at ACKS bit “1”. In this case, the settings of DFS1-0 are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Control 2 0 0 SLOW DFS1 DFS0 DEM1 DEM0 SMUTE default 0 0 0 0 0 0 1 0 SMUTE: Soft Mute Enable 0: Normal operation 1: DAC outputs soft muted DEM1-0: De-emphasis Response (Table 7) Initial: “01”, OFF DFS1-0: Sampling speed control 00: Normal Speed Mode 01: Double Speed Mode 10: Quad Speed Mode When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs. SLOW: Slow Roll-off Filter Enable 0: Sharp Roll-off Filter 1: Slow Roll-off Filter MS1127-E-01 2011/03 - 21 -
[AK4425A] Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Control 3 RRST 0 0 INVL INVR 0 0 0 default 0 0 0 0 0 0 0 0 INVR: Inverting Lch Output Polarity 0: Normal Output 1: Inverted Output INVL: Inverting Rch Output Polarity 0: Normal Output 1: Inverted Output RRST: Register Reset 0: Normal Operation 1: Register Reset (except RRST bit) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 default 1 1 1 1 1 1 1 1 A T T = 2 0 l o g 10 (ATT_DATA / 255) [dB] 00H: Mute MS1127-E-01 2011/03 - 22 -
- Grounding and Power Supply Decoupling
VDD and AVDD are supplied from the analog supply and should be separated from the system digital supply. between VDD and AVDD is not critical. reduce noise beyond the audio passband. Figure 16. External 1st order LPF Circuit Example
[AK4425A] PACKAGE 0-10° Detail A Seating Plane 0.10 *5.0±0.1 1.1 (max) A 1 8 9 16 16pin TSSOP (Unit: mm) *4.4±0.1 6.4±0.2 0.5±0.2 0.1±0.1 NOTE: Dimension "*" does not include mold flash. 0.13 M ■ Package & Lead frame material Package molding compound: Epoxy, Halogen (bromine and chlorine) free L e a d f r a m e m a t e r i a l : C u Lead frame surface treatme nt: Solder (Pb free) plate MS1127-E-01 2011/03 - 25 -
[AK4425A] MARKING AKM 4425AET XXYYY 1) Pin #1 indication 2) Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code 3) Marketing Code : 4425AET 4) Asahi Kasei Logo Date (YY/MM/DD) Revision
REVISION HISTORY
11/03/01 01 Error Correction 24 1. Grounding and Power Supply Decoupling The description was changed. MS1127-E-01 2011/03 - 26 -
[AK4425A] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility fo r such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS1127-E-01 2011/03 - 27 -