AK4420 AKM | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
[AK4420] 192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output AK4420 GENERAL DESCRIPTION The AK4420 is a 5V 24-bit stereo DAC with an integrated 2Vrms output buffer. A charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2Vrms output. Using AKM’s multi bit modulator architecture, the AK4420 delivers a wide dynamic range while preserving linearity for improved THD+N performance. The AK4420 integrates a combination of switched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. The 24-bit word length and 192kHz sampling rate make this part ideal for a wide range of consumer audio applications, such as DVD, AV receiver system and set-top boxes. The AK4420 is offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz 128 times Oversampling (Normal Speed Mode) 64 times Oversampling (Double Speed Mode) 32 times Oversampling (Quad Speed Mode) 24-Bit 8 times FIR Digital Filter Switched-Capacitor Filter with High Tolerance to Clock Jitter Single Ended 2Vrms Output Buffer Digital de-emphasis Soft mute I/F format: 24-Bit MSB justified or I2S Master clock: 512fs, 768fs or 1152fs (Normal Speed Mode) 256fs or 384fs (Double Speed Mode) 128fs, 192fs (Quad Speed Mode) THD+N: -92dB Dynamic Range: 105dB Automatic Power-on Reset Circuit Power supply: +4.5 ∼ +5.5V Ta = -20 to 85°C Small Package: 16pin TSSOP (6.4mm x 5.0mm) DIF LRCK BICK SDTI Audio Data Interface MCLK ΔΣ Modulator AOUTL Interpolator SCF LPF AOUTR VDD VSS1 Control Interface Clock Divider ΔΣ Interpolator SCF LPF Charge Pump CP CN VEE VSS2 CVDD 1μ 1μ DZF SMUTE Modulator MS0683-E-02 2007/12 - 1 -
[AK4420] ■ Ordering Guide AK4420ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch) AKD4420 Evaluation Board for AK4420 ■ Pin Layout 1 CN CP MCLK SMUTE BICK SDTI DIF 8 VEE VSS2 CVDD DZF VSS1 VDD AOUTL AOUTR AK4420 Top View LRCK MS0683-E-02 2007/12 - 2 -
[AK4420] PIN/FUNCTION No. Pin Name I/O Function
1 CN I
Negative Charge Pump Capacitor Terminal Pin Connect to CP with a 1.0 μF capacitor that should have the low ESR (Equivalent Series Resistance ) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used.
2 CP I
Positive Charge Pump Capacitor Terminal Pin Connect to CN with a 1.0μF capacitor that should have the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used.
3 SMUTE I Soft Mute Enable Pin (Internal pull down: 100kΩ)
“H”: Enable, “L”: Disable
4 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
5 BICK I Audio Serial Data Clock Pin
6 SDTI I Audio Serial Data Input Pin
7 LRCK I L/R Clock Pin
8 DIF I Audio Data Interface Format Pin
“L”: Left Justified, “H”: I2S
9 AOUTR O Rch Analog Output Pin
When power down, outputs VSS(0V, typ).
10 AOUTL O Lch Analog Output Pin
When power down, outputs VSS(0V, typ). 11 VDD - DAC Power Supply Pin: 4.5V∼5.5V
12 VSS1 - Ground Pin1
13 DZF O Zero Input Detect Pin
14 CVDD - Charge Pump Power Supply Pin: 4.5V∼5.5V
15 VSS2 - Ground Pin2
16 VEE O
Negative Voltage Output Pin Connect to VSS2 with a 1.0 μF capacitor that should have the low ESR (Equivalent Series Resistance ) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be used. Note: All input pins except for the CN pin should not be left floating. MS0683-E-02 2007/12 - 3 -
[AK4420] ABSOLUTE MAXIMUM RATINGS (VSS1=VSS2=0V; Note 1) Parameter Symbol min max Units Power Supply VDD CVDD -0.3 -0.3 +6.0 +6.0 V V Input Current (any pins except for supplies) IIN - ±10 mA Input Voltage VIND -0.3 VDD+0.3 V Ambient Operating Temperature Ta -20 85 °C Storage Temperature Tstg -65 150 °C Note 1. All voltages with respect to ground. Note 2. VSS1, VSS2 connect to the same analog grand. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1=VSS2=0V; Note 1) Parameter Symbol min typ max Units Power Supply VDD CVDD +4.5 +5.0 VDD +5.5 V Note 3. CVDD should be equal to VDD *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0683-E-02 2007/12 - 4 -
[AK4420] ANALOG CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +5.0V; fs = 44.1 kHz; BICK = 64fs; Signal Frequency = 1 kHz; 24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ) Parameter min typ max Units Resolution 24 Bits Dynamic Characteristics (Note 4) fs=44.1kHz, BW=20kHz -92 -84 dB fs=96kHz, BW=40kHz -92 - dB THD+N (0dBFS) fs=192kHz, BW=40kHz -92 - dB Dynamic Range (-60dBFS with A-weighted. (Note 5) 98 105 dB S/N (A-weighted. (Note 6) 98 105 dB Interchannel Isolation (1kHz) 90 100 dB Interchannel Gain Mismatch 0.2 0.5 dB DC Accuracy DC Offset (at output pin) -60 0 +60 mV Gain Drift 100 - ppm/°C Output Voltage (Note 7) 1.97 2.12 2.27 Vrms Load Capacitance (Note 8) 25 pF Load Resistance 5 kΩ Power Supplies Power Supply Current: (Note 9) Normal Operation (fs≤96kHz) Normal Operation (fs=192kHz) Power-Down Mode (Note 10) 100 mA mA μA Note 4. Measured by Audio Precision (System Two). Refer to the evaluation board manual. Note 5. 98dB for 16bit input data Note 6. S/N does not depend on input data size. Note 7. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD, AOUT (typ.@0dB) = 2.12Vrms × VDD/5. Note 8. In case of driving capacitive load, inset a resistor between the output pin and the capacitive load. Note 9. The current into VDD and CVDD. Note 10. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD MS0683-E-02 2007/12 - 5 -
[AK4420] FILTER CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V; fs = 44.1 kHz) Parameter Symbol min Typ max Units Digital filter Passband ±0.05dB (Note 11) –6.0dB PB 0 22.05 20.0 kHz kHz Stopband (Note 11) SB 24.1 kHz Passband Ripple PR ± 0.02 dB Stopband Attenuation SA 54 dB Group Delay (Note 12) GD - 19.3 - 1/fs Digital Filter + LPF Frequency Response 20.0kHz 40.0kHz 80.0kHz fs=44.1kHz fs=96kHz fs=192kHz FR FR FR ± 0.05 ± 0.05 ± 0.05 dB dB dB Note 11. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs. Note 12. Calculated delay time caused by digital filter. This time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. DC CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V High-Level Input Voltage (Iout = -80uA) Low-Level Input Voltage (Iout = 80uA) VIH VIL VDD-0.4 0.4 V V Input Leakage Current Iin - - ± 10 μA Note 13. The SMUTE pin is not included. The SMUTE pin has internal pull-up resistor (typ.100kΩ) . MS0683-E-02 2007/12 - 6 -
[AK4420] SWITCHING CHARACTERISTICS (Ta = 25°C; VDD=CVDD = +4.5 ∼ +5.5V) Parameter Symbol min Typ max Units Master Clock Frequency Duty Cycle fCLK dCLK 4.096 11.2896 36.864 MHz LRCK Frequency Normal Speed Mode Double Speed Mode Quad Speed Mode Duty Cycle fsn fsd fsq Duty 120 192 kHz kHz kHz Audio Interface Timing BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low Pulse Width High BICK “↑” to LRCK Edge (Note 14) LRCK Edge to BICK “↑” (Note 14) SDTI Hold Time SDTI Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/64fsd 1/64fsq ns ns ns ns ns ns ns ns ns Note 14. BICK rising edge must not occur at the same time as LRCK edge. MS0683-E-02 2007/12 - 7 -
clock is set to the appropriate frequency (Table 1). power-up, the AK4420 is in the power-down mode until MCLK and LRCK are input. Table 1. system clock example is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) Table 3. In all modes the serial data is MSB-first, two’s complement format and it is latched on the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
0 L 24bit MSB justified ≥48fs Figure 3
1 H 24bit I2S Figure 4≥48fs
Table 3. Audio Data Formats
changing the signal source without stopping the signal transmission. Normal Speed Mode: 1024 LRCK cycles (1020/fs). Double Speed Mode: 2048 LRCK cycles (2048/fs). Quad Speed Mode : 4096 LRCK cycles (4096/fs). (2) The analog output corresponding to a specific digital input has a group delay, GD. returned to ATT level in the same cycle. DZF pin immediately is set to “L” if the input data are not zero after going to DZF “H”. Figure 7. Soft Mute and Zero detect function
The AK4420 is in power down mode upon power-up. The MLCK should be input after the power supplies are ramped up. The AK4420 is in power-down mode until LRCK are input. (1) Approximately 20us after a MCLK input is detected, the internal analog circuit is powered-up. (2) The digital circuit is powered-up after 2 or 3 LRCK cycles following the detection of MCLK. (4) No audible click noise occurs under normal conditions. (5) The DZF pin is “L” in the power-down mode. supply voltage achieves 80% of VDD. If not, click noise may occur at a different time from this figure. Figure 8. System reset diagram
When the MCLK or LRCK stops, the AK4420 is placed in reset mode and its analog outputs are set to VSS (0V, typ). when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied. the “0” data during this period. (2) The analog output corresponding to a specific digital input has group delay (GD). (3) No audible click noise occurs under normal conditions. (4) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped). AK4420 exits reset mode after LRCK is inputted.. (6) The DZF pin is set to “L” in the reset mode. Figure 9. Reset Timing Example
[AK4420] PACKAGE 0-10° Detail A Seating Plane 0.10 *5.0±0.1 1.05±0.05 A 1 8 916 16pin TSSOP (Unit: mm) *4.4±0.1 6.4±0.2 0.5±0.2 0.1±0.1 NOTE: Dimension "*" does not include mold flash. 0.13 M ■ Package & Lead frame material Package molding compound: Epoxy L e a d f r a m e m a t e r i a l : C u Lead frame surface treatme nt: Solder (Pb free) plate MS0683-E-02 2007/12 - 17 -
[AK4420] MARKING AKM 4420ET XXYYY 1) Pin #1 indication 2) Date Code : XXYYY (5 digits) XX: Lot# YYY: Date Code 3) Marketing Code : 4420ET 4) Asahi Kasei Logo
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents 07/11/05 00 First Edition 07/12/04 01 13 Figure 8. The description of the click noise was corrected. Error Correction 14 Figure 9. The description of the click noise was corrected. 07/12/17 02 Error Correction 14 “The BICK can be stopped when MCLK or LRCK is stopped, but it must not be stopped when MCLK and LRCK are supplied.” was deleted. MS0683-E-02 2007/12 - 18 -
[AK4420] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these produc ts, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0683-E-02 2007/12 - 19 -