AK4309B AKM | Alldatasheet
Document overview
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Technical content
Features
Sampling Rate Ranging from 8kHz to 50kHz On chip Perfect filtering
- 8 times FIR Interpolator
- 2nd order SCF and CTF
- T otal Response: ±0.5dB at 20kHz On chip Buffer with Single End Output Master Clock: 256fs or 384fs High T olerance to Clock Jitter TTL Level Digital Interface THD+N: -84dB Dynamic Range: 90dB Output Level: 3.4Vpp Power Supply: 5V±10% Low Power Dissipation: 80mW at 5V Small Package: 20pin SSOP Pin Compatible with AK4310/4309A
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 2 - Ordering Guide AK4309BVM -10 ~+70°C 20pin SSOP(0.65mm pitch) AKD4309B Evaluation Board (AK4309B's board is the same as AK4310's) Pin Layout Compatibility with AK4310/09A Parameter AK4310 AK4309A AK4309B Digital I/F level CMOS TTL TTL DR 92dB 91dB 90dB Output Voltage 2.8Vpp 3.4Vpp 3.4Vpp Click Noise High Middle Low Function of Pin 4 PD PD NC Package 24SSOP 24SSOP 20SSOP
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 3 - PIN/FUNCTION No. Pin Name I/O Function
1 TST1 I T est Pin (Pull-down pin)
Must be left floating or tied to DVSS.
2 DVDD - Digital Power Supply Pin
3 DVSS - Digital Ground Pin
4 NC - No Connection
5 RST I R e s e t P i n
When at "L", the AK4309B is in power-down mode and is held in reset. The AK4309B should always be reset upon power-up.
6 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin. The fs is selected by CKS pin.
7 CKS I Master Clock Select Pin
"L": MCLK=256fs, "H": MCLK=384fs
8 BICK I Serial Bit Input Clock Pin
This clock is used to latch SDA TA.
9 SDA TA I Serial Data Input Pin
2's complement MSB-first data is input on this pin.
10 LRCK I L/R Clock Pin
This input determines which channel is currently being input on the Serial Data Input pin, SDA TA. "H": Lch, "L": Rch
11 AOUTR O Rch analog output pin
12 AOUTL O Lch analog output pin
13 VCOM O Common Voltage pin, AVDD/2
Normally connected to AVSS with a 0.1uF ceramic capacitor in parallel with a 10uF electrolytic cap.
14 AVDD - Analog Power Supply Pin
15 AVSS - Analog Ground Pin
- No Connection
18 VREFH I "H" Voltage Reference Input Pin
The differential Voltage between VREFH and VREFL inputs set the analog output range. The VREFH pin is normally connected to AVDD and the VREFL pin is connected to AVSS. A 0.1uF ceramic capacitor should be as near to both pins.
19 VREFL I "L" Voltage Reference Input Pin
20 DZF O Zero Input Detect Pin
When SDA T A of both channels follow a total 8192 LRCK cycles with "0" input data, this pin goes "H". * NC pins are not bonded internally.
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 4 - ABSOLUTE MAXIMUM RATINGS (AVSS,DVSS=0V; Note 1 ) Parameter Symbol min max Units Power Supplies: Analog Digital DVDD-AVDD AVDD DVDD VDA -0.3 -0.3 6.0 6.0 0.3 V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Input Voltage VIND -0.3 AVDD+0.3 V Ambient Operating Temperature T a -10 70 °C Storage Temperature Tstg -65 150 °C Note: 1 . All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS,DVSS=0V; Note 1 ) Parameter Symbol min typ max Units Power Supplies: Analog (Note 2 ) Digital AVDD DVDD 4.5 4.5 5.0 5.0 5.5 AVDD V V Voltage Reference(VREFH) (Note 3 ) VREF 3.0 - AVDD V Notes: 2 . AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. 3 . Analog output voltage scales with the voltage of VREFH at VREFL=AVSS. AOUT(typ.@0dB)=3.4Vpp*VREFH/5. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 5 - ANALOG CHARACTERISTICS (T a=25°C ; AVDD,DVDD=5.0V; VREFH=AVDD,VREFL=AVSS; fs=44.1kHz; Signal Frequency=1kHz; Measurement Bandwidth=10Hz~20kHz; RL‡10kW ; unless otherwise specified) Parameter min typ max Units Resolution 16 Bits Dynamic Characteristics (Note 4 ) THD+N (0dB Output) -84 -79 dB Dynamic Range (-60dB Output, A weight) 85 90 dB S/N (A weight) 85 90 dB Interchannel Isolation(1kHz) 80 90 dB DC Accuracy Interchannel Gain Mismatch 0.15 0.3 dB Gain Drift (Note 5 ) 60 - ppm/°C DC Accuracy Output Voltage (Note 6 ) 3.23 3.4 3.57 Vpp Load Resistance 10 kW Power Supplies Power Supply Current Normal Operation ( RST = "H") AVDD DVDD Power-Down-Mode ( RST = "L") AVDD+DVDD (Note 7 ) mA mA uA Power Dissipation (AVDD+DVDD) Normal Operation Power-Down-Mode (Note 7 ) 115 250 mW uW Power Supply Rejection (Note 8 ) 50 dB Notes: 4 . Measured by AD725C(SHIBASOKU). Averaging mode. Refer to the eva board manual. 5 . The voltage on VREFH pin is held +5V externally. 6 . Full-scale voltage(0dB). Output voltage scales with the voltage of VREH-VREFL. AOUT(typ.@0dB)=3.4Vpp*(VREFH-VREFL)/5. 7 . Power Dissipation in the power-down mode is applied with no external clocks (MCLK,BICK,LRCK held "H" or "L"). 8 . PSR is applied to AVDD,DVDD with 1kHz, 100mVpp. VREF pin is held +5V .
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 6 - FILTER CHARACTERISTICS (T a=25°C ; AVDD,DVDD=4.5V~5.5V; fs=44.1kHz) Parameter Symbol min typ max Units Digital Filter Passband -0.2dB (Note 9 ) -6.0dB PB 0 - 22.05 20.0 kHz kHz Stopband (Note 9 ) SB 24.3 kHz Passband Ripple PR ±0.05 dB Stopband Attenuation SA 41 dB Group Delay (Note 10 ) GD - 14.5 - 1/fs Digital Filter + SCF + CTF Frequency Response 0~20.0kHz - ±0.5 -d B Note: 9 . The passband and stopband frequencies scale with fs. For example, PB=0.4535*fs(@-0.2dB), SB=0.55*fs. 10 . The calculating delay time which occurred by digital filtering. This time is from setting the 16bit data of both channels to input register to the output of analog signal. DIGITAL CHARACTERISTICS (T a=25°C ; AVDD,DVDD=4.5~5.5V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.2 0.8 V V High-Level Output Voltage (Iout=-100A) Low-Level Output Voltage (Iout=100A) VOH VOL DVDD-0.5 0.5 V V Input Leakage Current Iin - - ±10 uA
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 7 - SWITCHING CHARACTERISTICS (T a=25°C ; AVDD,DVDD=4.5~5.5V; CL=20pF) Parameter Symbol min typ max Unit Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High fCLK tCLKL tCLKH fCLK tCLKL tCLKH 2.048 3.072 12.8 19.2 MHz ns ns MHz ns ns LRCK Frequency Duty Cycle fs Duty 44.1 50 kHz kHz Serial Interface Timing BICK Period BICK Pulse Width Low Pulse Width High BICK rising to LRCK edge (Note 11 ) LRCK Edge to BICK rising (Note 11 ) SDA TA Hold Time SDA TA Setup Time tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 312.5 100 100 ns ns ns ns ns ns ns Reset Timing RST Pulse Width (Note 12 ) tRST 150 ns Notes: 11 . BICK rising edge must not occur at the same time as LRCK edge. 12 . The AK4309B can be reset by bringing RST "L" to "H" only upon power up.
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 8 - Timing Diagram
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 11 - 1. Grounding and Power Supply Decoupling T o minimize coupling by digital noise, decoupling capacitors should be connected to AVDD and DVDD, respectively. AVDD is supplied from analog supply in system and DVDD is supplied from AVDD via 10W resistor as shown in Figure 3 . Alternatively if AVDD and DVDD are supplied separately, AVDD and DVDD should be powered at the same time or AVDD should be powered earlier than DVDD. Analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors for high frequency should be placed as near as possible. 2. Voltage reference The differential Voltage between VREFH and VREFL set the analog output range. VREFH pin is normally connected to AVDD and VREFL pin is connected to AVSS with a 0.1uF ceramic capacitor. VCOM is a signal ground of this chip. An electrolytic capacitor of around 10uF in parallel with a 0.1uF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be drawn from VCOM pin. All signals, especially clocks, should be kept away from the VREF and VCOM pins in order to avoid unwanted coupling into the AK4309B. 3. Analog Outputs The analog outputs are also single-ended and centered around the VCOM voltage. The output signal range is typically 3.4Vpp. AC coupling capacitors of larger than 1uF are recommended. The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. Therefore, any external filters are not required for typical application. The output voltage is a positive full scale for 7FFFH(@16bit) and a negative full scale for 8000H(@16bit). The ideal output is VCOM voltage for 0000H(@16bit). DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VCOM + a few mV .
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 12 - PACKAGE zzzz 20pin SSOP (Unit: mm) Package & Lead frame material Package molding compound : Epoxy Lead frame material : Cu Lead frame surface treatment : Solder plate NOTE: Dimension “*” does not include mold flash.
ASAHI KASEI [AK4309B] 0177-E-00 1997/6 - 13 - MARKING Contents of AAXXXX AA: Lot# XXXX: Date Code
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