AK4213 AKM | Alldatasheet
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[AK4213] MS0949-E-01 - 1 - 2008/07 GENERAL DESCRIPTION The AK4213 is an audio mono class-D speaker amplifier with stereo cap-less headphone amplifier. The AK4213 features analog mixing circuit that allow easy interfacing in mobile phone and portable A/V player designs. The input circuit supports both of single-ended and differential modes, and headphone supports stereo and mono modes. The speak er amplifier includes ALC (Automatic Level Control) circuit which is able to stabilize each output sound levels. The AK4213 is available in CSP package (3.0mm x 3.0mm), utilizing less board space than competitive offerings. FEATURE Single-ended / Differential Input Analog Mixing Circuit Analog Input Volume: +10dB to –20dB, 2dB step µP Interface: I2C Bus (Ver1.0, 400 kHz Fast-Mode) Thermal Shutdown / Short Protection circuit Mono Class-D Speaker Amplifier: - BTL output - Output Power: 1.6W @ 8Ω, SVDD=5V 0.8W @ 8Ω, SVDD=3.6V - THD+N: -65dB @ 8Ω, Po = 0.25W, SVDD=3.6V - Output Noise Level: 85μVrms - ALC (Automatic Level Control) Circuit - Bypass Mode - Pop Noise Free at Power-ON/OFF and Mute - External filter-less Stereo Cap-less Headphone Amplifier: - Mono / Stereo Mode - Output Power: 64mW x 2ch @ 16Ω, SVDD=3.3V, THD+N=-40dB - THD+N: -58dB @ 16Ω, Po=30mW, SVDD=3.3V - Output Noise Level: 24μVrms - Output Volume: +12dB to –50dB, 2dB Step - Pop Noise Free at Power-ON/OFF and Mute Power Supply: - Analog: 2.6V ∼ 3.6V - Headphone Amplifier: 2.6V ∼ 3.6V - Speaker Amplifier: 3.0V ∼ 5.5V - Digital Interface: 1.6V ∼ 3.6V Ta: −40 ∼ 85°C Package: 29pin CSP (3.0mm x 3.0mm, 0.5mm pitch) Mono Class-D SPK-Amp with Stereo Cap-less HP-Amp AK4213
Figure 1. AK4213 Block Diagram
[AK4213] MS0949-E-01 - 3 - 2008/07 ■ Ordering Guide AK4213ECB −40 ∼ +85°C 29pin CSP (3.0mm x 3.0mm, 0.5mm pitch) AKD4213 Evaluation board for AK4213 ■ Pin Layout A B C E D Top View F
5 HPR LIN3/IN3- VCOM RIN1/IN1+ SVDD LIN1/IN1-
4 HPL RIN3/IN3+ RIN2/IN2+ SPN VSS2 SPP
3 PVEE VSS3 PDN LIN2/IN2- TEST SPIN
2 PVDD SDA TVDD RVINN RVINP
1 CP CN SCL VSS1 AVDD MIXO
[AK4213] MS0949-E-01 - 4 - 2008/07 PIN / FUNCTION No. Pin Name I/O Function E1 AVDD - Analog Power Supply Pin D1 VSS1 - Ground 1 Pin E3 TEST O Test Pin This pin must be open. D2 TVDD - Digital Interface Power Supply Pin C1 SCL I Control Data Clock Pin C2 SDA I/O Control Data Input/Output Pin C3 PDN I Power-Down Mode Pin “H”: Power-up, “L”: Power-down, resets and initialization of the control register. The AK4213 must be reset once upon power-up. A1 CP I Positive Charge Pump Capacitor Terminal Pin B1 CN I Negative Charge Pump Capacitor Terminal Pin B2 PVDD - Charge Pump Circuit Positive Power Supply Pin B3 VSS3 - Ground 3 Pin A3 PVEE O Charge Pump Circuit Negative Voltage Output Pin A4 HPL O Lch Headphone-Amp Output Pin A5 HPR O Rch Headphone-Amp Output Pin F2 RVINP I Receiver Positive Input Pin E2 RVINN I Receiver Negative Input Pin B4 RIN3/IN3+ I Analog Input Pin B5 LIN3/IN3- I Analog Input Pin C5 VCOM O Analog Common Voltage Output Pin C4 RIN2/IN2+ I Analog Input Pin D3 LIN2/IN2- I Analog Input Pin D5 RIN1/IN1+ I Analog Input Pin F5 LIN1/IN1- I Analog Input Pin E5 SVDD - Speaker-Amp Power Supply Pin E4 VSS2 - Speaker-Amp Ground Pin (Ground 2 Pin) F4 SPP O Positive Speaker-Amp Output Pin D4 SPN O Negative Speaker-Amp Output Pin F1 MIXO O MIX-Amp Output Pin F3 SPIN I Speaker-Amp Input Pin Note 1. Do not allow all input pins except analog input pins (LIN1/IN1-, RIN1/IN1+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-, RIN3/IN3+, SPIN, RVINP and RVINN) to float. ■ Handling of Unused Pin The unused I/O pins must be processed appropriately as below. Classification Pin Name Setting Analog HPL, HPR, MIXO, SPIN, SPP, SPN, LIN1/IN1-, RIN1/IN1+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-, RIN3/IN3+, RVINP, RVINN, TEST These pins must be open.
[AK4213] MS0949-E-01 - 5 - 2008/07 ABSOLUTE MAXIMUM RATING (VSS1=VSS2=VSS2=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog AVDD −0.3 6.0 V (Note 3) Digital I/F TVDD −0.3 6.0 V Speaker-Amp & Headphone-Amp SVDD −0.3 6.0 V Charge Pump PVDD −0.3 4.0 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 4) VINA1 −0.3 (AVDD + 0.3) or 6.0 V (Note 5) VINA2 −0.3 (SVDD + 0.3) or 6.0 V Digital Input Voltage (Note 6) VIND −0.3 (TVDD + 0.3) or 6.0 V Ambient Temperature (powered applied) Ta −40 85 °C Storage Temperature Tstg −65 150 °C Ta=85ºC (Note 8) Pd1 - 0.65 W Maximum Power Dissipation (Note 7) Ta=70ºC (Note 9) Pd2 - 0.8 W Note 2. All voltages with respect to ground. Note 3. VSS1, VSS2, and VSS3 must be connected to the same analog plane. Note 4. LIN1/IN1-, RIN1/IN1+, LIN2/IN2-, RIN2/IN2+, LIN3/IN3-, RIN3/IN3+ and SPIN pins The maximum value is low value either (AVDD+0.3)V or 6.0V. Note 5. RVINP and RVINN pins The maximum value is low value either (SVDD+0.3)V or 6.0V. Note 6. SDA, SCL and PDN pins. The maximum value is low value either (TVDD+0.3)V or 6.0V. Pull-up resistors at SCL and SDA pins should be connected to (TVDD + 0.3)V or less voltage. Note 7. In case that PCB wiring density is 300% or more. This power is the AK4213 internal dissipation that does not include power of externally connected headphone and speaker. Note 8. In the case of Ta=85ºC, HP-Amp and SPK-Amp must not be powered-up simultaneously. When SPK-Amp be used, HP-Amp should power-down, and the power of SPK-Amp should less than 1.3W @8Ω. Note 9. In the case of Ta=70ºC, HP-Amp and SPK-Amp can be powered-up simultaneously. When HP-Amp and SPK-Amp be used simultaneously, the power of HP-Amp should less than 30mW @16Ω, and the power of SPK-Amp should less than 1.2W @8Ω. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
[AK4213] MS0949-E-01 - 6 - 2008/07 RECOMMEND OPERATING CONDITIONS (VSS1=VSS2=VSS3=0V; Note 2) Parameter Symbol min typ max Units Power Analog AVDD 2.7 3.3 3.6 V Supplies Digital I/F TVDD 1.6 1.8 3.6 V (Note 10) Speaker-Amp & Headphone-Amp SVDD 3.0 3.6 5.5 V Charge Pump PVDD 2.7 3.3 3.6 V Difference AVDD - PVDD -0.3 0 0.3 V SVDD - AVDD -0.3 - - V Note 10. The power up sequence among AVDD, TVDD, SVDD, and PVDD is not critical. The PDN pin must be held to “L” when power-up. The PDN pin must be set to “H” after power supplies are powered-up. The AK4213 should be operated by the recommended power-up/down sequence shown in “System Design” to avoid pop noise at speaker output and headphone output. The AK4213 supports the following two cases of partial power ON/OFF. In these cases, the PDN pin must be “L”. 1. TVDD=SVDD=ON: AVDD=PVDD can be power ON/OFF. 2. TVDD=ON: AVDD=PVDD=SVDD can be power ON/OFF. When the power state is changed from OFF to ON in the above cases, the PDN pin must be changed from “L” to “H” after all power supply pins are supplied. “L” time of 150ns or more is needed to reset the AK4213. * AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4213] MS0949-E-01 - 7 - 2008/07 ANALOG CHARACTERISTICS (Ta=25°C; AVDD=PVDD=3.3V, SVDD=3.6V, TVDD=1.8V, VSS1=VSS2=VSS3=0V; Input Signal Frequency =1 kHz; Measurement band width=10Hz ∼ 20kHz; Headphone-Amp: RL =16Ω; Speaker-Amp: RL =8Ω + 10μH; Charge Pump Circuit External Capacitance: C1=C2= 2.2μF (Figure 4); unless otherwise specified) Parameter min typ max Units LIN1, RIN1, LIN2, RIN2, LIN3, RIN3 pins Input Resistance 25 50 110 kΩ Input Analog Volume: L1V3-0, R1V3-0, L2V3-0, R2V3-0, L3V3-0, R3V3-0 bits Step Size 1 2 3 dB Gain Control Range -20 - +10 dB MIX-Amp: MIXO pin Load Resistance 10 - - kΩ Load Capacitance - - 30 pF Headphone-Amp: LIN/RIN Æ HPL/HPR pins, HPGA = 0dB Output Power (THD+N=1%) SVDD=3.3V mW THD+N: 0.7Vrms Single-ended Input, Po = 30mW - -58 -40 dB Output Noise Level (A-weighted) ( Note 11) - 24 40 μVrms Interchannel Gain Mismatch - 0.2 0.8 dB Load Resistance 16 - - Ω Load Capacitance - - 300 pF Output Voltage: 0.7Vrms Single-ended Input 0.62 0.69 0.76 Vrms PSRR 217Hz (Note 12) 1kHz (Note 12) 217Hz (Note 13) 1kHz (Note 13) 100 dB dB dB dB Interchannel Isolation 60 80 - dB Headphone Analog Volume (HPGA4-0 bits) Step Size 0.5 2 3.5 dB Gain Control Range -50 - +12 dB Class-D Speaker-Amp: LIN or RIN Æ SPP/SPN; BTL, ALC = OFF, Input Volume=SPGA=0dB, ALC OFF Output Power (THD+N=10%) SVDD=5.0V SVDD=3.6V 1.6 0.8 W W Output Level SVDD=5.0V, Input Level = 0.85Vrms (Note 14) SVDD=3.6V, Input Level = 0.64Vrms (Note 15) SVDD=3.6V, Input Level = 0.46Vrms (Note 16) 1.33 2.7 2.0 1.48 1.63 Vrms Vrms Vrms THD+N: Po=0.25W, Input Level =0.46Vrms (Note 16) -65 -40 dB Output Noise Level (A-weighted) ( Note 17) - 85 150 μVrms Load Resistance 8 - - Ω Load Capacitance ( Note 21) - - 300 pF PSRR 217Hz (Note 18) 1kHz (Note 18) 217Hz (Note 19) 1kHz (Note 19) dB dB dB dB Switching Frequency 150 250 400 kHz Current Limit at Short ( Note 20) - 40 120 mA Start-Up Time 18 30 48 ms
[AK4213] MS0949-E-01 - 8 - 2008/07 Parameter min typ max Units SPIN pins Input Resistance 15 26 36 kΩ Speaker Analog Volume: SPGA5-0 bits Step Size 0.1 0.5 0.9 dB Gain Control Range -12 - +19.5 dB Bypass Mode: Figure 2, Input Level = 1.13Vrms, Common Voltage = 1.8V, Measured by SPP/SPN pins 1.13Vrms, 3.2Vpp - -50 - dB THD+N 0.71Vrms, 2.0Vpp - -60 -50 dB Output level - 0.46 - Vrms Switch ON Resistance (BYPE bit = “1”) - 2.8 - Ω Switch Off Isolation ; 3.6V DC Input, Figure 3 (SPP/SPN pins– RVINP/RVINN pins) - 90 - dB Power Supplies Power Supply Current Normal Operation (PDN pin = “H”) AVDD+TVDD: ALL ON ( Note 22) - 4.0 6.5 mA HP-Amp ON ( Note 23) - 2.0 - mA SPK-Amp ON ( Note 24) - 2.8 - mA PVDD (No Output): HP-Amp ON - 1.3 3.2 mA SVDD (No Output): HP-Amp ON - 2.0 4.0 mA SPK-Amp ON 1.0 4.0 mA Power-Down Mode (PDN pin = “L”) ( Note 25) AVDD+PVDD+SVDD+TVDD - 1 30 μA Note 11. In case of singled-ended mode. Only mixer path of inputting signal is ON. (In case of differential mode, this value is typically 29μVrms.) Note 12. PSR is applied to AVDD and PVDD with 100mpVpp sine wave. Note 13. PSR is applied to SVDD with 0.89Vpp sine wave. Note 14. In case of single-ended mode. (In case of differential mode, the input signal level is 0.425Vrms. The signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) Note 15. In case of single-ended mode. (In case of differential mode, the input signal level is 0.32Vrms. The signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) Note 16. In case of single-ended mode. (In case of differential mode, the input signal level is 0.23Vrms. The signals with amplitude and inverted phase should be input to positive input pin and negative input pin.) Note 17. In case of singled-ended mode. Only mixer path of inputting signal is ON. (In case of differential mode, this value is typically 90μVrms. ) Note 18. PSR is applied to AVDD with 100mpVpp sine wave. Note 19. PSR is applied to SVDD with 100mpVpp sine wave. Note 20. Average current between SVDD and VSS2 when the SPP and SPN pins are shorted and 0.85Vrms, 1kHz sine wave is input to the AK4213 in single-ended mode. Note 21. This is capacitance value between output pin and VSS1. When a capacitor is connected between output pins, load capacitance for each output pin doubles. Therefore, it is necessary to decide load capacitance in consideration of these. Note 22. All Circuits are powered-up. (PMVCM = PMOSC = PMCP = PMHPL = PMHPR = PMMHL = PMMHR = PMSPK = PMMSP = PMV1 = PMV2 = PMV3 bits= “1”) Note 23. Minimum blocks for Headphone-Amp path are powered-up. (PMVCM = PMOSC = PMCP = PMHPL = PMHPR = PMMHL = PMMHR = PMV1 bits= “1”, PMSPK = PMMSP = PMV2 = PMV3 bits= “0”) Note 24. Minimum blocks for Speaker-Amp path are powered-up (PMVCM = PMOSC = PMCP = PMSPK = PMMSP = PMV1 bits= “1”, PMHPL = PMHPR = PMMHL = PMMHR = PMV2 = PMV3 bits= “0”) Note 25. All digital input pins are held at VSS1.
[AK4213] MS0949-E-01 - 10 - 2008/07 DC CHARACTERISTICS Parameter Symbol min typ max Units High-Level Input Voltage (2.2V ≤ TVDD ≤ 3.6V) VIH 70%TVDD - - V (1.6V ≤ TVDD < 2.2V) VIH 80%TVDD - - V Low-Level Input Voltage (2.2V ≤ TVDD ≤ 3.6V) VIL - - 30%TVDD V (1.6V ≤ TVDD < 2.2V) VIL - - 20%TVDD V Low-Level Output Voltage (2.0V ≤ TVDD ≤ 3.6V: Iout = 3mA) VOL - - 0.4 V (1.6V ≤ TVDD < 2.0V: Iout = 3mA) VOL - - 20%TVDD V Input Leakage Current Iin - - ±2 μA SWITCHING CHARACTERISTICS Parameter Symbol min typ max Units Control Interface Timing: (Note 26) SCL Clock Frequency FSCL - - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - - μs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - - μs Clock Low Time tLOW 1.3 - - μs Clock High Time tHIGH 0.6 - - μs Setup Time for Repeated Start Condition tSU:STA 0.6 - - μs SDA Hold Time from SCL Falling (Note 27) tHD:DAT 0 - μs SDA Setup Time from SCL Rising tSU:DAT 0.1 - - μs Rise Time of Both SDA and SCL Lines tR - - 0.3 μs Fall Time of Both SDA and SCL Lines tF - - 0.3 μs Setup Time for Stop Condition tSU:STO 0.6 - - μs Capacitive load on bus Cb - 400 pF Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 - 50 ns Power-down & Reset Timing PDN Pulse Width ( Note 28) tPD 150 - - ns Note 26. I2C is a registered trademark of Philips Semiconductors. Note 27. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 28. The PDN pin must change from “L” to “H” after all power supply pins are supplied. The AK4213 can be also reset by bringing the PDN pin = “L” to “H”.
Table 1. Input Volume Setting
0 Single-ended Mode (default)
1 Differential Mode
Table 2. Input Mode Setting
Figure 7. Input Selector & Volume in Single-ended Mode (SD3-1 bits = “000”)
Figure 8. Input Selector and Volume in Differential Mode (SD3-1 bits = “111”)
power-up / down transition time is 30ms (typ.) and 48ms (max). The write operation to SPGA5-0 bits is prohibited within 1.6ms after PMSPK bit is set to “1”.
0 Power-down (default)
1 Power-up & Output
Table 3. Speaker-Amp output state SPK-Amp are output from the SPP/SPN pin. In case of PMSPK bit = “1”, BYPE bit is ignored. case of Bypass Mode setting, PMVCM bit should be set to “1” if thermal shut-down function is used. Table 4. Speaker and Receiver Modes (x: Don’t care) Figure 12. Bypass Mode
- Speaker Mode Î Bypass Mode
- Bypass Mode Î Speaker Mode
b. Speaker-Amp power-up: Figure 18 shows the details of sequence.
The ALC (Automatic Level Control) operation of speaker-amp output is operated by ALC block when ALC bit = “1”. When ALC bit is “0”, the speaker volume depends on the setting value of SPGA5-0 bits. SPGA value is attenuated automatically to the amount defined by ALC limiter ATT step (LMTH1-0 bits). both the ALC limiter and recovery operation. When ZELMN bit = “1” (zero crossing detection is disabled), SPGA value is immediately (period: typ. 125μs, max. 200μs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits. The attenuate operation is executed continuously until the ALC output level becomes ALC limiter detection level or less. Table 5. ALC Limiter Detection Level / Recovery Counter Reset Level Table 6. ALC Limiter ATT Step (x: Don’t care) Table 7. ALC Zero Crossing Timeout Period
ZTM1-0 bits or longer period. the waiting timer of ALC recovery operation starts. small singal level in the large noise can be improved by this fast recovery operation. Table 8. ALC Recovery Waiting Timer Period Table 9. ALC Recovery GAIN Step Table 10. Reference Level at ALC Recovery Operation
Table 11 shows the example of the ALC setting. The ALC starts from the value of SPGA5-0 bits. Table 11. Example of the ALC setting operation is finished by ALC bit = “0”. the same or smaller than REF’S. Figure 13. Registers set-up sequence at ALC operation
The speaker volume becomes manual mode when ALC bit is “0”. This mode is used in the case shown below.
- Set-up the registers for the ALC operation (ZTM1-0, LMTH and etc).
- Set-up the initial value of SPGA when ALC starts.
- When SPGA is used as a manual volume.
bit is changed from “0” to “1”, writing to SPGA5-0 bits is inhibit within 1.6ms. Table 12. Speaker-Amp Volume Setting Figure 14. SPGA value during ALC operation (1) ALC operation starts from the SPGA value when ALC bit is changed to “1”. an interval more than zero crossing timeout period after ALC bit = “0”.
set by PTS1-0 bits when MOFF bit is “0”. When MOFF bit is “1”, the mute ON/OFF is switched immediately. Table 14. Headphone amplifier Mode Setting (x: Don’t’ care) [Vpp] after the charge pump circuit is powered-up. Figure 16. Wired OR with External HP-Amp
The mute ON/OFF time of headphone-amp is set to PTS1-0 bits. These operations are soft transition. mute ON/OFF is switched immediately. Table 15. Registers with Transition Time MUTE ON/OFF Time PTS1 PTS0 typ. max. Table 16. Headphone-Amp Mute ON/OFF Transition Time
- VCOM Power-Up; PMVCM bit = “0” Æ “1”
- Bypass Mode Enable: BYPE bit = “0” Æ “1”
- Bypass Mode Disable: BYPE bit = “1” Æ “0”
- VCOM Power-down; PMVCM bit = “1” Æ “0”
contents of the control register are maintained until reset is executed.
Figure 17. HP-Amp Power-up/down sequence example (1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4213. (AVDD, TVDD, PVDD, SVDD) ON. (2) PTS1-0, MOFF, HPGA4-0, and SD3-1 bits must be set during this period. The PVEE pin becomes PVEE voltage within 10ms (max.). of the Charge Pump circuit, Headphone-Amp is powered-up after the Charge Pump circuit is powered-up. depends on the setting of PTS1-0 and MOFF bits. Headphone-Amp goes to the mute state after the transition time set by PTS1-0 and MOFF bits. Headphone-Amp is powered-down immediately. The PVEE pin becomes 0V according to the time constant of the capacitor at the PVEE pin and the internal resistor. The internal resistor is 17.5kΩ (typ.). Charge Pump Circuit can be powered-up during this period.
Figure 18. SPK-Amp Power-up/down Sequence Example (1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4213. (AVDD, TVDD, PVDD, SVDD) are ON. SD3-1 bits must be set during this period. (6) ALC setting: ALC is enabled at 30ms (max.). Refer to “Registers set-up sequence at ALC operation”. (7) Speaker-Amp goes to the normal operation at 48ms (max.) after PMSPK bit is changed to “1”. PMMSP, PMSPK bit = “1” Æ “0”, before PMVCM,PMOSC bit = “1” Æ “0”, please wait more than 0.5ms.
Example: The signal path changes from LIN1/RIN1 to LIN2/RIN2 when HP-Amp is powered-up. Figure 19. Example of changing signal path during HP-Amp is powered-up (4) Input volume of LIN2/RIN2 is powered-up at 26.3ms (max.).
[AK4213] MS0949-E-01 - 30 - 2008/07 ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 PMMHR PMMHL PMHPR PMHPL PMCP PMOSC PMVCM 01H Power Management 1 0 0 0 0 0 PMMSP 0 PMSPK 02H Power Management 2 0 0 0 0 0 PMV3 PMV2 PMV1 03H Mode Control 0 THDET 0 0 BYPE 0 SD3 SD2 SD1 04H Lch Headphone Mixer 0 0 HPLR3 HPLL3 HPLR2 HPLL2 HPLR1 HPLL1 05H Rch Headphone Mixer 0 0 HPRR3 HPRL3 HPRR2 HPRL2 HPRR1 HPRL1 06H Speaker Mixer 0 0 SPKR3 SPKL3 SPKR2 SPKL2 SPKR1 SPKL1 07H Reserved 0 0 0 0 0 0 0 0 08H Input Volume #1 R1V3 R1V2 R1V1 R1V0 L1V3 L1V2 L1V1 L1V0 09H Input Volume #2 R2V3 R2V2 R2V1 R2V0 L2V3 L2V2 L2V1 L2V0 0AH Input Volume #3 R3V3 R3V2 R3V1 R3V0 L3V3 L3V2 L3V1 L3V0 0BH Reserved 0 0 0 0 0 0 0 0 0CH Mode Control 1 0 0 MOFF 0 PTS1 PTS0 0 0 0DH Headphone PGA Control 0 HPZ HPMTN HPGA4 HPGA3 HPGA2 HPGA1 HPGA0 0EH Speaker PGA Control 0 0 SPGA5 SPGA4 SPGA3 SPGA2 SPGA1 SPGA0 0FH ALC Mode Control 1 0 0 REF5 REF4 REF3 REF2 REF1 REF0 10H ALC Mode Control 2 0 0 0 ZTM1 ZTM0 WTM2 WMT1 WMT0 11H ALC Mode Control 3 0 ALC ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH 12H TEST 0 0 0 0 0 0 0 0 All registers writing are inhibited at PDN pin = “L”. The PDN pin = “L” resets the registers to their default value. Note 29. The bit indicated as “0” in the register map must contain a “0” value. Note 30. Only write to address 00H to 12H.
[AK4213] MS0949-E-01 - 31 - 2008/07 ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Management 0 0 PMMHR PMMHL PMHPR PMHPL PMCP PMOSC PMVCM R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMVCM: Power Management for VCOM and Regulator which used for Headphone-Amp 0: Power OFF (default) 1: Power ON PMOSC: Power Management for Internal Oscillator 0: Power OFF (default) 1: Power ON PMCP: Power Management for Charge Pump Circuit 0: Power OFF (default) 1: Power ON PMHPL: Power Management for Lch Headphone-Amp 0: Power OFF (default) 1: Power ON PMHPR: Power Management for Rch Headphone-Amp 0: Power OFF (default) 1: Power ON PMMHL: Power Management for Mixing & Selector Circuit of Lch Headphone-Amp 0: Power OFF (default) 1: Power ON PMMHR: Power Management for Mixing & Selector Circuit of Rch Headphone-Amp 0: Power OFF (default) 1: Power ON
[AK4213] MS0949-E-01 - 32 - 2008/07 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Power Management 1 0 0 0 0 0 PMMSP 0 PMSPK R/W RD RD RD RD RD R/W RD R/W Default 0 0 0 0 0 0 0 0 PMSPK: Power Management for Speaker-Amp 0: Power OFF (default) 1: Power ON When PMSPK bit is “0”, SPP pin and SPN pin becomes Hi-Z. PMMSP: Power Management for Mixing & Selector Circuit of Speaker-Amp 0: Power OFF (default) 1: Power ON Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Power Management 2 0 0 0 0 0 PMV3 PMV2 PMV1 R/W RD RD RD RD RD R/W R/W R/W Default 0 0 0 0 0 0 0 0 PMV1: Power Management for Input Volume #1 0: Power OFF (default) 1: Power ON PMV2: Power Management for Input Volume #2 0: Power OFF (default) 1: Power ON PMV3: Power Management for Input Volume #3 0: Power OFF (default) 1: Power ON All blocks can be powered-down by setting the PDN pin to “L” regardless of register values setup. In this case, all control register values are initilized. When all power management bits are “0” in the 00H, 01H and 02H addresses, all blocks are powered-down. The register values will remain unchanged. Power supply current is 18uA (typ) in this case. For fully shut down, The PDN pin should be “L”.
[AK4213] MS0949-E-01 - 33 - 2008/07 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Mode Control 0 THDET 0 0 BYPE 0 SD3 SD2 SD1 R/W RD RD RD R/W RD R/W R/W R/W Default 0 0 0 0 0 0 0 0 SD1: Input mode setting of LIN1/IN1- and RIN1/IN1+ pins 0: Single-ended Mode (default) 1: Differential Mode SD2: Input mode setting of LIN2/IN2- and RIN2/IN2+ pins 0: Single-ended Mode (default) 1: Differential Mode SD3: Input mode setting of LIN3/IN3- and RIN3/IN3+ pins 0: Single-ended Mode (default) 1: Differential Mode BYPE: Bypass Mode Enable 0: Disable (default) 1: Enable When BYPE bit is changeed from “0” to “1” at PMSPK bit = “1”, the AK4213 changes to Bypass mode after the speaker amp is powered-down. When BYPE bit is changed from “1” to “0”, SPK-Amp starts operating according to the setting of PMSPK bit after exiting Bypass mode. THDET: Thermal Shutdown Detection 0: Normal Operation (default) 1: Thermal Shutdown status Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Lch Headphone Mixer 0 0 HPLR3 HPLL3 HPLR2 HPLL2 HPLR1 HPLL1 05H Rch Headphone Mixer 0 0 HPRR3 HPRL3 HPRR2 HPRL2 HPRR1 HPRL1 06H Speaker Mixer 0 0 SPKR3 SPKL3 SPKR2 SPKL2 SPKR1 SPKL1 07H Reserved 0 0 0 0 0 0 0 0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Input Mixers: (Figure 7) 0: OFF (default) 1: ON Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Input Volume #1 R1V3 R1V2 R1V1 R1V0 L1V3 L1V2 L1V1 L1V0 09H Input Volume #2 R2V3 R2V2 R2V1 R2V0 L2V3 L2V2 L2V1 L2V0 0AH Input Volume #3 R3V3 R3V2 R3V1 R3V0 L3V3 L3V2 L3V1 L3V0 0BH Reserved 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 1 0 1 0 1 0 Input Volumes: Default: 0dB (Table 1)
[AK4213] MS0949-E-01 - 34 - 2008/07 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0CH Mode Control 1 0 0 MOFF 0 PTS1 PTS0 0 0 R/W RD RD R/W RD R/W R/W RD RD Default 0 0 0 0 0 0 0 0 PTS1-0: Headphone-Amp Mute ON/OFF Transition Time Default: “00”, typ. 16.4ms (Table 16) MOFF0: Soft transition for changing HPMTN bit 0: Enable (default) 1: Disable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Headphone PGA Control 0 HPZ HPMTN HPGA4 HPGA3 HPGA2 HPGA1 HPGA0 R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 1 0 0 1 HPGA4-0: Headphone-Amp Volume Setting Default: 19H; 0dB (Table 13) HPMTN: Headphone-Amp Mute 0: Mute (default) 1: Normal Output HPZ: Headphone-Amp Pull-down Control 0: Ground Mode (default) HPL/HPR pins are shorted to VSS3. 1: Hi-Z Mode HPL/HPR pins are pulled-down by 25kΩ(typ) to VSS3. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0EH Speaker PGA Control 0 0 SPGA5 SPGA4 SPGA3 SPGA2 SPGA1 SPGA0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 0 1 1 0 0 0 SPGA5-0: Speaker-Amp Volume Setting Default: 18H; 0dB (Table 12) When PMSPK bit is set to “0”, reading and writing of SPGA5-0 bits are inhibited. When changing from PMSPK bit = “0” to PMSPK bit = “1”, SPGA volume becomes default value (0dB) regardless of the setting of SPGA5-0 bits. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH ALC Mode Control 1 0 0 REF5 REF4 REF3 REF2 REF1 REF0 R/W RD RD R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 1 0 0 REF5-0: Reference value at ALC Recovery Operation Default: 3CH; +18dB (Table 10)
[AK4213] MS0949-E-01 - 35 - 2008/07 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 10H ALC Mode Control 2 0 0 0 ZTM1 ZTM0 WTM2 WTM1 WTM0 R/W RD RD RD R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 1 WTM2-0: ALC Recovery Waiting Period Default: “101”, 524.8ms (typ.) (Table 8) ZTM1-0: ALC Zero Crossing Timeout Period Default: “01”, 32.8ms (typ.) (Table 7) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H ALC Mode Control 3 0 ALC ZELMN LMAT1 LMAT0 RGAIN1 RGAIN0 LMTH R/W RD R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 LMTH: ALC Limiter Detection Level / Recovery Wainting Counter Reset Level Default: “0” (Table 5) RGAIN1-0: ALC Recovery GAIN Step Default: “00”; 1 step (Table 9) LMAT1-0: ALC Limiter ATT Step Default: “00”; 1 step (Table 6) ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (default) 1: Disable ALC: ALC Enable 0: ALC Disable (default) 1: ALC Enable When ALC bit is set to “1”, the ALC operation is enabled. The initial value is “0” (Disable). Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 12H TEST 0 0 0 0 0 0 0 0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 Write “0” into the “0” registers.
[AK4213] MS0949-E-01 - 37 - 2008/07 PACKAGE 29pin CSP (3.0mm x 3.0mm, 0.5mm pitch, BGA) Top View Bottom View 0.65 ± 0.05 0.08 S S E C D A B 2.96 ± 0.05 F 2.96 ± 0.05 4 2 1 3 X X X X B 0.50 0.23 A φ 0.30 ± 0.05 φ 0.05 ABSM B DCFE A 0.48 0.25 ± 0.05
[AK4213] MS0949-E-01 - 38 - 2008/07 MARKING 4213 XXXX A XXXX: Date code (4 digit) Pin #A1 indication
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents 08/05/19 00 First Edition 08/07/09 01 Spec Change 3 ■ Ordering Guide AK4213EC → AK4213ECB 32 ■ Register Definitions 01H, GDDLY bit was deleted.
37 PACKAGE
Package plan was changed. Black type. IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these produc ts, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to func tion or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD pr oducts, who distributes, dis poses of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.