AK4125_07 AKM | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 26
Technical content
[AK4125] AK4125 192kHz / 24Bit High Performance Asynchronous SRC GENERAL DESCRIPTION The AK4125 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very simple configuration because the AK4125 has an internal PLL and does not need any master clock at slave mode. The AK4125 is suitable for the application interfacing to different sample rates such as high-end Car Audio and DVD recorder.
FEATURES
- SRC
- Asynchronous Sample Rate Converter
- Input Sample Rate Range (fsi): 8kHz ∼ 216kHz
- Output Sample Rate Range (fso): 8kHz ∼ 216kHz
- Input to Output Sample Rate Ratio: 1/6 to 6
- THD+N: −130dB
- Dynamic Range: 140dB (A-weighted)
- I/F format: MSB justified, LSB justified and I2S compatible
- PLL for Internal Operation Clock
- Clock for Master mode: 128/192/256/384/512/768fsi, 128/192/256/384/512/768fso
- SRC Bypass mode
- Soft Mute Function 2. Power Supply
- AVDD, DVDD: 3.0 ∼ 3.6V (typ. 3.3V) 3. Ta = −40 ∼ 85°C 4. Package: 30pin VSOP 5. AK4124 Pin-compatible PLL PDN SMUTE OLRCK OBICK SDTO OMCLK Serial Audio I/F SRC Serial Audio I/F ILRCK SDTI IBICK PLL1 PLL2 IDIF2 IDIF1 IDIF0 ODIF1 ODIF0 OBIT1 OBIT0 UNLOCK IMCLK AVDD AVSS DVDD DVSS CMODE2 CMODE1 CMODE0 PLL0 DITHER MS0379-E-04 2007/07 - 1 -
[AK4125] ■ Ordering Guide AK4125VF −40 ∼ +85°C 30pin VSOP (0.65mm pitch) AKD4125 Evaluation Board for AK4125 ■ Pin Layout PDN SMUTE ILRCK IBICK FILT AVSS DITHER PLL2 IDIF0 IDIF1 IDIF2 PLL0 PLL1 SDTI Top View DVDD OMCLK SDTO OBICK OLRCK DVSS AVDD CMODE2 OBIT1 IMCLK CMODE0 ODIF0 ODIF1 CMODE1
16 OBIT0UNLOCK 15
- 2 -
[AK4125] ■ Compatibility with AK4124 AK4124 AK4125 0.985 ≤ FSO/FSI ≤ 6.000 0.4583FSI ← 0.905 ≤ FSO/FSI < 0.985 0.4167FSI ← Digital Filter Passband 0.3195FSI 0.714 ≤ FSO/FSI < 0.905 ← 0.2852FSI 0.656 ≤ FSO/FSI < 0.714 ← 0.2182FSI 0.536 ≤ FSO/FSI < 0.656 ← 0.2177FSI 0.492 ≤ FSO/FSI < 0.536 0.1982FSI 0.1948FSI 0.452 ≤ FSO/FSI < 0.492 0.1740FSI 0.1458FSI 0.357 ≤ FSO/FSI < 0.452 0.1212FSI 0.1302FSI 0.324 ≤ FSO/FSI < 0.357 0.1072FSI 0.0917FSI 0.246 ≤ FSO/FSI < 0.324 0.0595FSI 0.0826FSI 0.226 ≤ FSO/FSI < 0.246 0.0484FSI 0.0583FSI 0.1667 ≤ FSO/FSI < 0.226 0.0182FSI Refer to Table 8 for the detail of filter response. MS0379-E-04 2007/07 - 3 -
[AK4125] PIN/FUNCTION No. Pin Name I/O Function
1 FILT O PLL Loop Filter Pin
2 AVSS - Analog Ground Pin
Power-Down Mode Pin 3 PDN I “H”: Power up, “L”: Power down reset and initializes the control register. Soft Mute Pin 4 SMUTE I “H” : Soft Mute, “L” : Normal Operation Dither Enable Pin 5 DITHER I “H” : Dither ON, “L” : Dither OFF
6 PLL2 I PLL Mode Select 2 Pin
7 ILRCK I/O Input Channel Clock Pin
8 IBICK I/O Audio Serial Data Clock Pin
9 SDTI I Audio Serial Data Input Pin
10 IDIF0 I Audio Interface Format 0 Pin for Input PORT
11 IDIF1 I Audio Interface Format 1 Pin for Input PORT
12 IDIF2 I Audio Interface Format 2 Pin for Input PORT
13 PLL0 I PLL Mode Select 0 Pin
14 PLL1 I PLL Mode Select 1 Pin
15 UNLOCK O Unlock Status Pin
16 OBIT0 I Bit Length Select 0 Pin for Output Data
17 OBIT1 I Bit Length Select 1 Pin for Output Data
18 IMCLK I Master Clock Input Pin for Input PORT
19 CMODE0 I Clock Mode Select 0 Pin
20 CMODE1 I Clock Mode Select 1 Pin
21 CMODE2 I Clock Mode Select 2 Pin
22 ODIF0 I Audio Interface Format 0 Pin for Output PORT
23 ODIF1 I Audio Interface Format 1 Pin for Output PORT
24 SDTO O Audio Serial Data Output Pin for Output PORT
25 OBICK I/O Audio Serial Data Clock Pin for Output PORT
26 OLRCK I/O Output Channel Clock Pin for Output PORT
27 OMCLK I Master Clock Input Pin for Output PORT
28 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
29 DVSS - Digital Ground Pin
30 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V Note: All input pins must not be left floating. MS0379-E-04 2007/07 - 4 -
[AK4125] ■ Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name Setting Analog FILT This pin should be open. SMUTE, DITHER These pins should be connected to DVSS. Digital IMCLK, OMCLK These pins should be connected to DVSS in slave mode. UNLOCK This pin should be open. ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: Analog AVDD −0.3 4.6 V Digital DVDD −0.3 4.6 V |AVSS − DVSS| (Note 2) ΔGND - 0.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Digital Input Voltage VIND −0.3 DVDD+0.3 V Ambient Temperature (Power applied) Ta −40 85 °C Storage Temperature Tstg −65 150 °C Note 1. All voltages with respect to ground. Note 2. AVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 1) Parameter Symbol min typ max Units Analog AVDD 3.0 3.3 3.6 V Power Supplies Note 3) Digital DVDD 3.0 3.3 AVDD V ( Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not important. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. MS0379-E-04 2007/07 - 5 -
[AK4125] SRC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=3.3V; AVSS=DVSS=0V; Single Frequency = 1 kHz, data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution 24 Bits Input Sample Rate FSI 8 216 kHz Output Sample Rate FSO 8 216 kHz THD+N (Input = 1kHz, 0dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz - −130 - dB FSO/FSI = 48kHz/44.1kHz - −124 - dB FSO/FSI = 48kHz/192kHz - −133 - dB FSO/FSI = 192kHz/48kHz - −124 - dB Worst Case (FSO/FSI = 32kHz/176.4kHz) - - −91 dB Dynamic Range (Input = 1kHz, −60dBFS, Note 4) FSO/FSI = 44.1kHz/48kHz - 136 - dB FSO/FSI = 48kHz/44.1kHz - 136 - dB FSO/FSI = 48kHz/192kHz - 136 - dB FSO/FSI = 192kHz/48kHz - 132 - dB Worst Case (FSO/FSI = 48kHz/32kHz) 132 - - dB Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 4) FSO/FSI = 44.1kHz/48kHz - 140 - dB Ratio between Input and Output Sample Rate FSO/FSI 1/6 6 - Note 4. Measured by Audio Precision System Two Cascade. MS0379-E-04 2007/07 - 6 -
[AK4125] FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V) Parameter Symbol min typ max Units Digital Filter 0.4583FSI 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 kHz 0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz Passband −0.01dB 0.3195FSI 0.714 ≤ FSO/FSI < 0.905 PB 0 kHz 0.2852FSI 0.656 ≤ FSO/FSI < 0.714 PB 0 kHz 0.2182FSI 0.536 ≤ FSO/FSI < 0.656 PB 0 kHz 0.2177FSI 0.492 ≤ FSO/FSI < 0.536 PB 0 kHz 0.1948FSI 0.452 ≤ FSO/FSI < 0.492 PB 0 kHz 0.1458FSI 0.357 ≤ FSO/FSI < 0.452 PB 0 kHz 0.1302FSI 0.324 ≤ FSO/FSI < 0.357 PB 0 kHz 0.0917FSI 0.246 ≤ FSO/FSI < 0.324 PB 0 kHz 0.0826FSI 0.226 ≤ FSO/FSI < 0.246 PB 0 kHz 0.0583FSI 0.1667 ≤ FSO/FSI < 0.226 PB 0 kHz 0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz 0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz Stopband 0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz 0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz 0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz 0.492 ≤ FSO/FSI < 0.536 SB 0.2813FSI kHz 0.452 ≤ FSO/FSI < 0.492 SB 0.2604FSI kHz 0.357 ≤ FSO/FSI < 0.452 SB 0.2116FSI kHz 0.324 ≤ FSO/FSI < 0.357 SB 0.1969FSI kHz 0.246 ≤ FSO/FSI < 0.324 SB 0.1573FSI kHz 0.226 ≤ FSO/FSI < 0.246 SB 0.1471FSI kHz 0.1667 ≤ FSO/FSI < 0.226 SB 0.1020FSI kHz Passband Ripple PR ±0.01 dB 0.985 ≤ FSO/FSI ≤ 6.000 SA 121.2 dB 0.905 ≤ FSO/FSI < 0.985 SA 121.4 dB 0.714 ≤ FSO/FSI < 0.905 SA 115.3 dB Stopband Attenuation 0.656 ≤ FSO/FSI < 0.714 SA 116.9 dB 0.536 ≤ FSO/FSI < 0.656 SA 114.6 dB 0.492 ≤ FSO/FSI < 0.536 SA 100.2 dB 0.452 ≤ FSO/FSI < 0.492 SA 103.3 dB 0.357 ≤ FSO/FSI < 0.452 SA 102.0 dB 0.324 ≤ FSO/FSI < 0.357 SA 103.6 dB 0.246 ≤ FSO/FSI < 0.324 SA 104.0 dB 0.226 ≤ FSO/FSI < 0.246 SA 103.3 dB 0.1667 ≤ FSO/FSI < 0.226 SA 73.2 dB Group Delay (Note 5) GD - 56 - 1/fs Note 5. This delay is the a period from the rising edge of ILRCK, just after the data is input, to the rising edge of OLRCK, just after the data is output, when there is no phase difference between ILRCK and OLRCK. MS0379-E-04 2007/07 - 7 -
[AK4125] DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V) Parameter Symbol min typ max Units High-Level Input Voltage VIH 70%DVDD - - V Low-Level Input Voltage VIL - - 30%DVDD V High-Level Output Voltage (Iout=−400μA) VOH DVDD−0.4 - - V Low-Level Output Voltage (Iout=400μA) VOL - - 0.4 V Input Leakage Current Iin - - ±10 μA Power Supplies Power Supply Current Normal operation (PDN pin = “H”) mA FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V 13 mA FSI=FSO=192kHz at Master Mode: AVDD=DVDD=3.3V 55 mA : AVDD=DVDD=3.6V 85 Power down (PDN pin = “L”) (Note 6) AVDD+DVDD 10 100 μA Note 6. All digital input pins are held DVSS. MS0379-E-04 2007/07 - 8 -
[AK4125] MS0379-E-04 2007/07 - 9 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 1.024 0.4/fCLK 0.4/fCLK 41.472 MHz ns ns LRCK for Input data (ILRCK) Frequency Duty Cycle Slave Mode Master Mode fs Duty Duty 216 kHz LRCK for Output data (OLRCK) Frequency Duty Cycle Slave Mode Master Mode fs Duty Duty 216 kHz Audio Interface Timing Input PORT (Slave mode) IBICK Period (8kHz ∼ 108kHz) (108kHz ∼ 216kHz) IBICK Pulse Width Low Pulse Width High ILRCK Edge to IBICK “↑” (Note 7) IBICK “↑” to ILRCK Edge (Note 7) SDTI Hold Time from IBICK “↑” SDTI Setup Time to IBICK “↑” tBCK tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/128fs 1/64fs ns ns ns ns ns ns ns ns Input PORT (Master mode) IBICK Frequency IBICK Duty IBICK “↓” to ILRCK SDTI Hold Time from IBICK “↑” SDTI Setup Time to IBICK “↑” fBCK dBCK tMBLR tSDH tSDS −20 64fs Hz ns ns ns Output PORT (Slave mode) OBICK Period (8kHz ∼ 108kHz) (108kHz ∼ 216kHz) OBICK Pulse Width Low Pulse Width High OLRCK Edge to OBICK “↑” (Note 7) OBICK “↑” to OLRCK Edge (Note 7) OLRCK to SDTO (MSB) (Except I2S mode) OBICK “↓” to SDTO tBCK tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/128fs 1/64fs ns ns ns ns ns ns ns ns Output PORT (Master mode) OBICK Frequency OBICK Duty OBICK “↓” to OLRCK OBICK “↓” to SDTO fBCK dBCK tMBLR tBSD −20 −20 64fs Hz ns ns Reset Timing PDN Pulse Width (Note 8) tPD 150 ns Note 7. BICK rising edge must not occur at the same time as LRCK edge. Note 8. The AK4125 can be reset by bringing the PDN pin = “L”.
[AK4125] ■ Timing Diagram 1/fCLK MCLK tCLKH tCLKL VIH VIL 1/fs LRCK VIH VIL tBCK BICK tBCKH tBCKL VIH VIL Clock Timing LRCK VIH VIL tBLR BICK VIH VIL tLRS SDTO 50%DVDD tLRB tBSD tSDS SDTI VIL tSDH VIH Audio Interface Timing (Slave mode) Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0379-E-04 2007/07 - 10 -
[AK4125] LRCK BICK 50%DVDD SDTO 50%DVDD tBSD tSDS SDTI VIL tSDH VIH tMBLR dBCK 50%DVDD Audio Interface Timing (Master mode) Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. tPD PDN VIL Power Down & Reset Timing MS0379-E-04 2007/07 - 11 -
The IDIF2-0 pins select the audio interface format for the input port. The audio data is MSB first, 2’s compliment format. BYPASS mode, both IBICK and OBICK are fixed to 64fs.
0 L L L 16bit, LSB justified ≥ 32fsi
1 L L H 20bit, LSB justified ≥ 40fsi
2 L H L 24/20bit, MSB justified ≥ 48fsi Input Input Slave
3 L H H 24/16bit, I2S Compatible ≥ 48fsi or 32fsi
4 H L L 24bit, LSB justified ≥ 48fsi
5 H L H 24bit, MSB justified 64fs Output Output Master 6 H H L 24bit, I2S Compatible 64fs
7 H H H Reserved
Table 1. Input Audio Interface Format (Input PORT)
0 L L L 8k ∼ 96kHz
1 L L H Manual Depending on
2 L H L
3 L H H Reserved IMCLK = DVSS
4 H L L 32fsi (Note 11) IBICK = Input
5 H L H 64fsi
6 H H L 128fsi
7 H H H
8 L L L 128fs 8k ∼ 216kHz
9 L L H 8k ∼ 108kHz 256fs Manual
10 L H L 512fs 8k ∼ 54kHz
11 L H H 8k ∼ 216kHz 128fs Semi-Auto
12 H L L 8k ∼ 216kHz 192fs
13 H L H 8k ∼ 108kHz 384fs
14 H H L 768fs 8k ∼ 54kHz
15 H H H 192fs 8k ∼ 216kHz Semi-Auto
Table 2. PLL Setting (Input PORT) Note 9. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter”. Note 10. IBCIK must be continuous except when the clocks are changed. Note 13. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode.
Figure 5. Mode 4 Timing select the master/slave and bypass mode. The CMODE2-0 pins should be controlled when the PDN pin = “L”. PDN pin = “L”. When in BYPASS mode, both IBICK and OBICK are fixed to 64fs.
1 Mode CMODE0 Master / Slave OMCLK fso
0 L L L Master 256fso 8k ∼ 108kHz
1 L L H Master 384fso 8k ∼ 108kHz
2 L H L Master 512fso 8k ∼ 54kHz
3 L H H Master 768fso 8k ∼ 54kHz
5 H L H Master 128fso 8k ∼ 216kHz
6 H H L Master 192fso 8k ∼ 216kHz
Table 3. Master/Slave Control (Output PORT)
0 L L LSB justified
1 L H (Reserved)
2 H L MSB justified
23 H H I S Compatible
Table 4. Output Audio Interface Format 1 (Output PORT)
0 L L 16bit ≥ 32fso
1 L H 18bit ≥ 36fso Slave
2 H L 20bit ≥ 40fso CMODE2-0 =
3 H H 24bit ≥ 48fso
4 L L 16bit
5 L H 18bit
6 H L 20bit
7 H H 24bit
Table 5. Output Audio Interface Format 2 (Output PORT)
Figure 13. Sequence of changing clocks pin changes to “L”. It makes the data on SDTO remain as “0”. Note 2. SMUTE can also remove the unknown data. outputs “H” and the SDTO = “0”. When the PDN pin = “L”, the UNLOCK pin outputs “H”.
optimum layout, power supply arrangements and measurement results.
- Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
- Output PORT: Slave mode, 24bit MSB justified
- Dither = OFF FILT1 AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 AK4125 AVDD DVSS DVDD
12 IDIF2
13 PLL0
14 PLL1
15 UNLOCK 16OBIT0
- All digital input pins should not be left floating.
Figure 15. Typical Connection Diagram (Slave mode)
- Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified
- Output PORT: Master mode, 24bit MSB justified
- Dither = OFF FILT1 AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 AK4125 AVDD DVSS DVDD
- All digital input pins should not be left floating.
Figure 16. Typical Connection Diagram (Master mode)
- Grounding and Power Supply Decoupling
possible, with the small value ceramic capacitor being the nearest.
- Digital Filter Response Example
Table 8 shows the examples of digital filter response performed by the AK4125. Table 8. Digital Filter Example
[AK4125] PACKAGE Detail A NOTE: Dimension "*" does not include mold flash. 0.22 ±0.1 0.65 *9.7 ±0.1 1.5MAX A 1 15 1630 30pin VSOP (Unit: mm) 5.6±0.1 7.6±0.2 0.45±0.2 -0.05 +0.10 0.3 0.150.12 M 0.08 1.2±0.10 0.10 +0.10 -0.05 ■ Material & Lead finish Package molding compound: Epoxy L e a d f r a m e m a t e r i a l : C u Lead frame surface treatme nt: Solder (Pb free) plate MS0379-E-04 2007/07 - 24 -
[AK4125] MARKING AKM AK4125VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character)
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents 05/01/05 00 First Edition 05/05/10 01 Comment Addition 22 A note on IBICK was added. 06/06/20 02 Error Correction
6 THD+N Worst Case condition
FSO/FSI = 48kHz/8kHz Æ 32kHz/176.4kHz 07/02/20 03 Error Correction
9 Switching Characteristics (ILRCK)
Master/Slave modes were added to Duty Cycle. 20,21 Connections of PLL1/PLL0 pins were corrected. 07/07/25 04 Description Change 16 Figure 9 and Figure 10 were changed. 18 ■ Internal Rest Function for Clock Change ■ Sequence of Changing Clocks ■ UNLOCK pin MS0379-E-04 2007/07 - 25 -
[AK4125] IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these produc ts, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or system Note2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. MS0379-E-04 2007/07 - 26 -