AK4122_1 AKM | Alldatasheet
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ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 1 - GENERAL DESCRIPTION The AK4122 is a digital sample rate converter (SRC) with the digital audio receiver (DIR). The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. By using the AK4122, the system can take very simple configuration because the AK4122 has an internal PLL and does not need any master clock at slave mode. Then the AK4122 is suitable for the application interfacing to different sample rates like Car Audio, DVD recorder, etc.
FEATURES
- SRC
- Asynchronous Sample Rate Converter
- Input Sample Rate Range (fsi) : 8kHz ∼ 96kHz
- Output Sample Rate (fso) : 32kHz, 44.1kHz, 48kHz, 96kHz
- Input to Output Sample Rate Ratio : 0.33 to 6
- THD+N : −113dB
- I/F format : MSB justified, LSB justified (16/24bit) and I2S compatible
- Clock for Master mode : 256/384/512/768fs
- SRC Bypass mode
- Soft Mute Function 2. DIR
- 4-Channel Inputs Selector & 1-Channel Through Output
- AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible
- Low Jitter Analog PLL
- PLL Lock Range : 32kHz ∼ 96kHz
- Auto detection - Non-PCM Bit Stream - DTS-CD Bit Stream - Validity Flag - Sampling Frequency (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz) - Unlock & Parity Error - DAT Start ID
- 40-bit Channel Status Buffer
- Burst Preamble bit Pc, Pd Buffer for Non-PCM bit streams
- Q-subcode Buffer for CD bit streams 3. 4-wire Serial µP Interface 4. Power Supply
- AVDD: 3.0 ∼ 3.6V (typ. 3.3V)
- DVDD: 3.0 ∼ 3.6V (typ. 3.3V) 5. Ta = −10 ∼ 70°C 6. Package : 48pin LQFP 24-Bit 96kHz SRC with DIR AK4122
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 2 - Block Diagram RX2 RX2 PDN RX1 RX1 IPS1-0 Serial Audio I/F LRCK1 SDTI LRCK1 SDTI BICK1 BICK1 Serial Audio I/F LRCK2 SDTIO LRCK2 SDTIO BICK2 BICK2 MCLK2 LRCK BICK SDTO LRCK BICK SDTO OMCLK SMUTE Control Register CDTO CDTI CCLK CSNAVDD AVSS DVDD DVSS M/S2 M/S3 SRC PLL Serial Audio I/F De-em Filter PORT1 PORT2 PORT3 RX3 RX3 RX4 RX4 DIR TX TX ISEL1-0 OSEL BYPS INT0 INT1 R FILTINT2 OPS1-0 Block diagram
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 3 - Ordering Guide AK4122VQ −10 ∼ +70°C 48pin LQFP (0.5mm pitch) AKD4122 Evaluation Board for AK4122 Pin Layout CDTI CCLK 48 47 46 45 44 43 42 41 40 39 38 2322212019181716151413 AK4122VQ Top View CDTO TST1 INT2 TST2 TST3 M/S2 M/S3 SMUTE TST4 TST5 AVSS PDN LRCK1 BICK1 SDTI DVSS DVDD MCLK2 LRCK2 BICK2 SDTIO CSN BVSS DVDD DVSS OMCLK LRCK BICK SDTO TX INT1 12FILT 25 R INT0 TST6 AVDD AVSS RX1 TST7 RX2 TST8 RX3 TST9 RX4 TST10 TST11
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 4 - PIN/FUNCTION No. Pin Name I/O Function
1 CDTI I Control Data Input Pin
2 CDTO O Control Data Output Pin
3 TST1 O Test 1 Pin
4 INT2 O Interrupt 2 Pin
5 TST2 O Test 2 Pin
6 TST3 I Test 3 Pin
This pin should be connected to DVSS.
7 M/S2 I Master / Slave Mode Pin for PORT2
“H” : Master mode, “L” : Slave Mode
8 M/S3 I Master / Slave Mode Pin for PORT3
“H” : Master mode, “L” : Slave Mode
9 SMUTE I Soft Mute Pin
“H” : Soft Mute, “L” : Normal Operation
10 TST4 I Test 4 Pin
This pin should be connected to AVSS.
11 TST5 I Test 5 Pin
This pin should be connected to AVSS.
12 FILT O
470Ω±5% resistor and 2.2µF±50% ceramic capacitor in parallel with a 2.2nF±50% ceramic capacitor should be connected to AVSS externally.
13 AVSS - Analog Ground Pin
14 AVDD - Analog Power Supply Pin, 3.0 ∼ 3.6V
15 TST6 I Test 6 Pin
This pin should be connected to AVSS. 16 RX1 I Receiver Input 1 Pin with Amp for 0.2Vpp (Internal Biased Pin)
17 TST7 I Test 7 Pin
This pin should be connected to AVSS. 18 RX2 I Receiver Input 2 Pin with Amp for 0.2Vpp (Internal Biased Pin)
19 TST8 I Test 8 Pin
This pin should be connected to AVSS. 20 RX3 I Receiver Input 3 Pin with Amp for 0.2Vpp (Internal Biased Pin)
21 TST9 I Test 9 Pin
This pin should be connected to AVSS. 22 RX4 I Receiver Input 4 Pin with Amp for 0.2Vpp (Internal Biased Pin)
23 TST10 I Test 10 Pin
This pin should be connected to AVSS.
24 TST11 O Test 11 Pin
Note: All input pins except internal biased pins should not be left floating.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 5 -
25 R - External Resistor Pin
12kΩ±5% resistor should be connected to AVSS externally.
26 AVSS - Analog Ground Pin
27 PDN I Power-Down Mode Pin
“H”: Power up, “L”: Power down reset and initializes the control register.
28 LRCK1 I Input Channel Clock Pin
29 BICK1 I Audio Serial Data Clock Pin
30 SDTI I Audio Serial Data Input Pin
31 DVSS - Digital Ground Pin
32 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
33 MCLK2 I Master Clock Input Pin
34 LRCK2 I/O Input / Output Channel Clock Pin
35 BICK2 I/O Audio Serial Data Clock Pin
36 SDTIO I/O Audio Serial Data Input / Output Pin
37 INT0 O Interrupt 0 Pin
38 INT1 O Interrupt 1 Pin
39 TX O Transmitter Output Pin
40 SDTO O Audio Serial Data Output Pin
41 BICK I/O Audio Serial Data Clock Pin
42 LRCK I/O Output Channel Clock Pin
43 OMCLK I Master Clock Input Pin
44 DVSS - Digital Ground Pin
45 DVDD - Digital Power Supply Pin, 3.0 ∼ 3.6V
46 BVSS - Substrate Ground Pin
This pin should be connected to AVSS.
47 CSN I Chip Select Pin
48 CCLK I Control Data Clock Pin
Note: All input pins except internal biased pins should not be left floating.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 6 - Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name Setting PORT1 BICK1, LRCK1, SDTI These pins should be connected to DVSS. MCLK2 This pin should be connected to DVSS. BICK2, LRCK2 These pins should be connected to DVSS in slave mode or open in master mode. SDTIO This pin should be connected to DVSS. PORT2 M/S2 This pin should be connected to DVDD or DVSS. OMCLK This pin should be connected to DVSS. BICK, LRCK These pins should be connected to DVSS in slave mode or open in master mode. SDTO This pin should be open. PORT3 M/S3 This pin should be connected to DVDD or DVSS. RX1, RX2, RX3, RX4 These pins should be open. DIR INT0, INT1, INT2, TX These pins should be open. CSN, CCLK, CDTI These pins should be connected to DVSS. Control PORT CDTO This pin should be open. Other SMUTE This pin should be connected to DVSS. TST1, TST2, TST11 These pins should be open. TST3 This pin should be connected to DVSS. TEST TST4, TST5, TST6, TST7, TST8, TST9, TST10 These pins should be connected to AVSS.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 7 - ABSOLUTE MAXIMUM RATINGS (AVSS, BVSS, DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: Analog Digital |BVSS − DVSS| (Note 2) AVDD DVDD ∆GND −0.3 −0.3 4.6 4.6 0.3 V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Digital Input Voltage 1 (Except RX1-4 pins) VIND1 −0.3 DVDD+0.3 V Digital Input Voltage 2 (RX1-4 pins) VIND2 −0.3 AVDD+0.3 V Ambient Temperature (Power applied) Ta −10 70 °C Storage Temperature Tstg −65 150 °C Note 1. All voltages with respect to ground. Note 2. AVSS, BVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, BVSS, DVSS=0V; Note 1) Parameter Symbol min typ max Units Power Supplies (Note 3) Analog Digital AVDD DVDD 3.0 3.0 3.3 3.3 3.6 AVDD V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD and DVDD is not critical. WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 8 - SRC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=3.3V; AVSS=BVSS=DVSS=0V; data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units SRC Characteristics: Resolution (Note 4) 24 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 32 96 kHz THD+N (Input = 1kHz, 0dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 48kHz/8kHz) −113 −113 −114 −111 −103 dB dB dB dB dB Dynamic Range (Input = 1kHz, −60dBFS, Note 5) FSO/FSI = 44.1kHz/48kHz FSO/FSI = 48kHz/44.1kHz FSO/FSI = 32kHz/48kHz FSO/FSI = 96kHz/32kHz Worst Case (FSO/FSI = 32kHz/44.1kHz) Dynamic Range (Input = 1kHz, −60dBFS, A-weighted, Note 5) FSO/FSI = 44.1kHz/48kHz 112 114 115 115 116 117 dB dB dB dB dB dB Ratio between Input and Output Sample Rate (Note 6) FSO/FSI 0.33 6 - Note 4. Input data for SRC corresponds to 24bit data. When LSB 4bit data is input, the AK4122 calculates as “0” data because SRC is 20bit calculation. Therefore, SRC outputs “0” data. Note 5. Measured by ROHDE & SCHWARZ UPD04, Rejection Filter = wide, 8192point FFT. Note 6. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz. The “6” is the ratio of FSO/FSI when FSI is 8kHz and FSO is 48kHz. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V) Parameter Symbol min typ max Units Input Resistance Zin - 10 - k Ω Input Voltage VTH 200 mVpp Input Sample Frequency fs 32 - 96 kHz
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 9 - FILTER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; DEM=OFF) Parameter Symbol min typ max Units Digital Filter 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz 0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz 0.714 ≤ FSO/FSI < 0.905 PB 0 0.3195FSI kHz 0.656 ≤ FSO/FSI < 0.714 PB 0 0.2852FSI kHz 0.536 ≤ FSO/FSI < 0.656 PB 0 0.2245FSI kHz 0.492 ≤ FSO/FSI < 0.536 PB 0 0.2003FSI kHz 0.452 ≤ FSO/FSI < 0.492 PB 0 0.1781FSI kHz Passband −0.001dB 0.333 ≤ FSO/FSI < 0.452 PB 0 0.1092FSI kHz 0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz 0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz 0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz 0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz 0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz 0.492 ≤ FSO/FSI < 0.536 SB 0.2732FSI kHz 0.452 ≤ FSO/FSI < 0.492 SB 0.2510FSI kHz Stopband 0.333 ≤ FSO/FSI < 0.452 SB 0.1822FSI kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 96 dB Group Delay (Note 7) GD - 58.5 - 1/fs Note 7. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input. DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V) Parameter Symbol min typ max Units High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD 30%DVDD V V High-Level Output Voltage (Iout=−400µA) Low-Level Output Voltage (Iout=400µA) VOH VOL DVDD−0.4 0.4 V V Input Leakage Current Iin - - ±10 µA Parameter min typ max Units Power Supply Current Normal operation (PDN pin = “H”) (Note 8) FSI=FSO=48kHz at Slave Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.3V FSI=FSO=96kHz at Master Mode: AVDD=DVDD=3.6V Power down (PDN pin = “L”) (Note 9) AVDD+DVDD 100 mA mA mA µA Note 8. Typ and max values are the value of AVDD+DVDD in each power supply voltage. Power supply current of each path@Slave Mode, AVDD=DVDD=3.3V, FSI=FSO=48kHz 1. PORT1 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 2. PORT2 → SRC → PORT3: AVDD=5mA(typ), DVDD=10mA(typ) 3 . D I R → SRC → PORT3: AVDD=6mA(typ), DVDD=9mA(typ) Note 9. All digital input pins are held DVSS.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 10 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=3.0 ∼ 3.6V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Pulse Width Low Pulse Width High fCLK tCLKL tCLKH 8.192 0.4/fCLK 0.4/fCLK 36.864 MHz ns ns LRCK for Input data (LRCK1, LRCK2) Frequency Duty Cycle fs Duty kHz LRCK for Output data (LRCK, LRCK2) Frequency (Note 10) Duty Cycle Slave Mode Master Mode fs Duty Duty kHz S/PDIF Clock Recover Frequency fPLL 32 96 kHz Audio Interface Timing Input for PORT1 BICK1 Period BICK1 Pulse Width Low Pulse Width High LRCK1 Edge to BICK1 “↑” (Note 11) BICK1 “↑” to LRCK1 Edge (Note 11) SDTI Hold Time from BICK1 “↑” SDTI Setup Time to BICK1 “↑” tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/64fs ns ns ns ns ns ns ns Input for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “↑” (Note 11) BICK2 “↑” to LRCK2 Edge (Note 11) SDTIO Hold Time from BICK2 “↑” SDTIO Setup Time to BICK2 “↑” tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS 1/64fs ns ns ns ns ns ns ns Output for PORT2 (Slave mode) BICK2 Period BICK2 Pulse Width Low Pulse Width High LRCK2 Edge to BICK2 “↑” (Note 11) BICK2 “↑” to LRCK2 Edge (Note 11) LRCK2 to SDTIO (MSB) (Except I 2S mode) BICK2 “↓” to SDTIO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/64fs ns ns ns ns ns ns ns Note 10. Min value is 8kHz at BYPASS mode. Note 11. BICK1 rising edge must not occur at the same time as LRCK1 edge. BICK2 rising edge must not occur at the same time as LRCK2 edge.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 11 - Parameter Symbol min typ max Units Output for PORT3 (Slave mode) BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (Except I 2S mode) BICK “↓” to SDTO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/64fs ns ns ns ns ns ns ns Output for PORT2 (Master mode) BICK2 Frequency BICK2 Duty BICK2 “↓” to LRCK2 BICK2 “↓” to SDTIO fBCK dBCK tMBLR tBSD −20 −20 64fs Hz ns ns Output for PORT3 (Master mode) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO fBCK dBCK tMBLR tBSD −20 −20 64fs Hz ns ns Control Interface Timing CCLK Period (Note 12) CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 1000 ns ns ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 13) tPD 150 ns Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. In case of using INT2. When INT2 is not used, the max value is not limited. Note 13. The AK4122 can be reset by bringing the PDN pin = “L”.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 12 - Timing Diagram 1/fCLK MCLK tCLKH tCLKL VIH VIL 1/fs LRCK VIH VIL tBCK BICK tBCKH tBCKL VIH VIL Clock Timing LRCK VIH VIL tBLR BICK VIH VIL tLRS SDTO 50%DVDD tLRB tBSD tSDS SDTI VIL tSDH VIH Audio Interface Timing (Slave mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 13 - LRCK BICK 50%DVDD SDTO 50%DVDD tBSD tSDS SDTI VIL tSDH VIH tMBLR dBCK 50%DVDD Audio Interface Timing (Master mode) Note : BICK shows BICK1 of PORT1, BICK2 of PORT2 and BICK of PORT3. LRCK shows LRCK1 of PORT1, LRCK2 of PORT2 and LRCK of PORT3. SDTI shows SDTI of PORT1 or SDTIO of PORT2 that is used as input port. SDTO shows SDTO of PORT3 or SDTIO of PORT2 that is used as output port. CSN VIH VIL tCSS CCLK tCDS VIH VIL CDTI VIH tCCKHtCCKL tCDH VIL C1 C0 R/W CDTO Hi-Z WRITE/READ Command Input Timing
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 14 - CSN VIH VIL tCSH CCLK VIH VIL CDTI VIH tCSW VIL D1 D0 CDTO Hi-Z WRITE Data Input Timing CSN VIH VIL CCLK VIH VIL CDTI VIH VIL CDTO 50%DVDD tDCD D7 D6Hi-Z READ Data Output Timing 1
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 15 - CSN VIH VIL tCSH CCLK VIH VIL CDTI VIH tCSW VIL CDTO 50%DVDDD2 D1 D0 tCCZ Hi-Z READ Data Output Timing 2 tPD PDN VIL Power Down & Reset Timing
(ISEL1-0 bits etc) in Figure 1 correspond to the register bits that control the switch function. Refer to Table 1. Figure 1. Connection Input Source & Output Source Table 1. Path Select After PDN pin = “L” → “H”, SDTIO pin of PORT2 is the input pin. Refer to Table 6 and 7 for Master/Slave mode setting.
MCLK2 I This pin should be connected to DVSS. BICK2 I This pin should be connected to DVSS. LRCK2 I This pin should be connected to DVSS. SDTIO I This pin should be connected to DVSS. MCLK2 I This pin should be connected to DVSS. BICK2 O This pin should be open. LRCK2 O This pin should be open. SDTIO I This pin should be connected to DVSS. Table 2. Pin Setting for PORT2 OMCLK I This pin should be connected to DVSS. BICK I This pin should be connected to DVSS. LRCK I This pin should be connected to DVSS. SDTO O This pin should be open. OMCLK I This pin should be connected to DVSS. BICK O This pin should be open. LRCK O This pin should be open. SDTO O This pin should be open. Table 3. Pin Setting for PORT3 selected output port (PORT2 or PORT3) should be input. Table 4. MCLK2 frequency select for Master mode Table 5. OMCLK frequency select for Master mode
Table 6. Master mode/Slave mode for PORT2 Table 7. Master mode/Slave mode for PORT3 compliment format. The SDTI is latched on the rising edge of BICK1. PORT1 corresponds to slave mode only. Table 8. Audio Interface Format for PORT1 Figure 2. Mode 0 Timing
and returned to 0dB by the same cycles. The soft mute is effective for changing the signal source. Figure 12. Soft Mute Function (1) The output data is attenuated by −∞ during 1024 LRCK cycles (1024/fs). (2) Digital output delay from the digital input is called the group delay (GD). returned to 0dB by the same number of clock cycles.
frequencies (32kHz, 44.1kHz and 48kHz). the internal de-emphasis filter is always bypassed. Table 11. De-emphasis Auto Control (DEAU bit = “1”) Table 12. De-emphasis Manual Control (DEAU bit = “0”) the internal de-emphasis filter is bypassed. Table 13. De-emphasis Manual Control activated by the PWN bit. The AK4122 should be reset once at power-up by bringing PDN pin = “L”. registers are initialized and clocks are stopped. Read/Write operations to the registers are disabled. operations to the registers are enabled.
received sync interval is incorrect. 200mVpp or greater signal. The IPS1-0 bits select the receiver channel (Table 14). Table 14. Recovery Data Select output buffer (Line Driver), the TX pin cannot drive the 75Ω coaxial cable directly. Table 15. Output Data Select for TX
MCLK when DIR is used, MCLK (MCLK2 or OMCLK) of selected output port (PORT2 or PORT3) should be input. Table 16. Reference MCLK Frequency Table 17. fs Information Note 2. In consumer mode, Byte3 Bit3-0 are copied to FS3-0. default (CS12 bit = “0”). It can be switched to channel 2 by changing the CS12 bit in the control register.
0 OFF ≠ 0X100 ≠ 100
1 ON 0X100 100
Table 18. PEM Information
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 28 - Interrupt Handling for DIR There are nine events that cause the INT2-0 pins to go “H”. 1. UNLCK: PLL unlock state detection “1” when the PLL loses lock. The AK4122 loses lock when the distance between two preambles is not correct or when those preambles are not correct. 2. PAR: Parity error or biphase coding error detection “1” when parity error or biphase coding error is detected, updated every sub-frame cycle. 3. AUTO: Non-PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits is output to the AUTO bit. 4. V: Validity flag detection “1” when validity flag is detected. Updated every sub-frame cycle. 5. AUDN: Non-audio detection “1” when the “AUDN” bit in recovered channel status indicates “1”. Updated every block cycle. 6. STC: Sampling frequency or pre-emphasis information change detection “1” when FS3-0 or PEM bit changes. Reading 07H register resets it. 7. QINT: U bit (Q-subcode) sync flag “1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated every sync code cycle for Q-subcode. Reading 07H register resets it. 8. CINT: Channel status sync flag “1” when received C bits differ from old ones, and stays “1” until this register is read. Updated every block cycle. Reading 07H register resets it. 9. DAT: DAT Start ID detection When the category code shows DAT, “1” when the Start ID of DAT is detected. Reading 08H register resets it. INT1-0 pins output an OR’ed signal based on the above nine interrupt events. When masked, the interrupt event does not affect the operation of the INT1-0 pins (the masks do not affect the registers (UNLCK, PAR, etc.) themselves). Once INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared. INT2 pin output a state change on the above 1 ∼ 5 and an OR’ed signal based on the above 6 ∼ 9. It stays “H” until 07H and 08H registers are read. Mask bits are shared with INT0. UNLCK, AUTO, V and AUDN bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or CINT and DAT bit goes to “1”, it stays “1” until the register is read. When the AK4122 loses lock, the channel status bits are initialized. In this initial state, INT0 and INT2 outputs the OR’ed signal between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDN. INT2-0 pins are “L” when the DIR is not selected. When DIR is used as input port and the PLL loses lock (unlock state), the output data is muted automatically. When AMUTE bit = “1”, SDTIO and SDTO are muted automatically when the AK4122 detects unlock, Non-Audio or Non-PCM/DTS-CD. After the interrupt events are cleared, mute is cancelled automatically. When AMUTE bit = “0”, SDTIO and SDTO outputs “L” when the PLL loses lock (unlock state), and outputs data when other errors (PAR, AUTO etc.).
Figure 17. INT2-0 Timing (UNLCK, PAR, AUTO, V, AUDN bits)
Figure 18. INT2-0 Timing (STC, CINT, QINT bits)
Figure 19. INT2-0 Timing (DAT bit)
Figure 20. Interrupt Handling Sequence Example 1
Figure 21. Interrupt Handling Sequence Example 2
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detecti on of this pattern will set the NPCM to “1”. and Pd (Pc: burst information, Pd: length code; Refer to Table 22, 23) that follow those sync codes are stored to registers. without MCLK, BICK and , LRCK. Figure 25. Control I/F Timing
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 36 - Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H PDN & Mode Control XTL1 XTL0 TXE SMUTE DEAU DEM1 DEM0 PWN 01H Selector & Clock Control BYPS OS EL ISEL1 ISEL0 ICKS1 ICKS0 OCKS1 OCKS0 02H Audio Interface Format 0 0 0 ODIF IDIF1 IDIF0 DIF1 DIF0 03H DIR Control CS12 AMUTE EFH1 EFH0 IPS1 IPS0 OPS1 OPS0 04H INT0 Mask MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 05H INT1 Mask MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 06H DAT Mask & DTS Detect 0 0 0 0 DTS16 DTS14 MDAT1 MDAT0 07H Receiver Status 0 UNLCK PAR AUTO V AUDN STC CINT QINT 08H Receiver Status 1 DAT DTSCD NPCM PEM FS3 FS2 FS1 FS0 09H Receiver Status 2 0 0 0 0 0 0 CCRC QCRC 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR1 5 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR2 3 CR22 CR21 CR20 CR1 9 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR3 1 CR30 CR29 CR28 CR2 7 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR3 9 CR38 CR37 CR36 CR3 5 CR34 CR33 CR32 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 13H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 PDN pin = “L” resets the registers to their default values. When PORT1 or PORT2 are selected as input port, the status registers (07H ∼ 1CH) are initialized. Note. Unused bits must contain a “0” value. Note. For addresses from 1DH ∼ 1FH, data must not be written.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 37 - Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H PDN & Mode Control XTL1 XTL0 TXE SMUTE DEAU DEM1 DEM0 PWN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 1 0 0 0 1 1 PWN: Power Down Control 0 : Power down 1 : Normal operation (Default) “0” powers down all sections. The contents of all register are not initialized and enabled to write to the registers. The internal registers (00H ∼ 06H) are not initialized, however, the status registers (07H ∼ 1CH) are initialized. Read/Write operations to the registers are enabled. DEM1-0: De-emphasis Control (Table 12, 13) Initial values are “01”. DEAU: De-emphasis Auto Control 0 : Disable (Default) 1 : E n a b l e When DEAU bit = “1”, the de-emphasis filter is enabled automatically by sampling frequency and pre-emphasis information in the channel status. SMUTE: Soft Mute Control 0 : Normal operation (Default) 1 : SDTIO and SDTO soft mute When SMUTE bit = “1”, SDTO and SDTIO outputs “L”. TXE: TX Output enable 0 : Disable, TX outputs “L”. 1 : Enable (Default) XTL1-0: Reference MCLK Frequency Select (Table 16) Initial values are “11”.
Table 19. Input PORT Select
0 PORT3
1 PORT2
Table 20. Output PORT Select
LRCK of Table 21 is DIR’s LRCK, the hold time scales with 1/fs. Table 21. Hold count select Non-Audio or Non-PCM/DTS-CD. This bit selects that channel status is used to derive C-bit buffers, AUDN, PEM, FS3-0, Pc, Pd and CRC.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 40 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H INT0 Mask MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 1 1 1 MQIT0: Mask enable for QINT bit 0 : Mask disable 1 : Mask enable MCIT0: Mask enable for CINT bit 0 : Mask disable 1 : Mask enable MSTC0: Mask enable for STC bit 0 : Mask disable 1 : Mask enable MAUD0: Mask enable for AUDN bit 0 : Mask disable 1 : Mask enable MV0: Mask enable for V bit 0 : Mask disable 1 : Mask enable MAUT0: Mask enable for AUTO bit 0 : Mask disable 1 : Mask enable MPAR0: Mask enable for PAR bit 0 : Mask disable 1 : Mask enable MULK0: Mask enab le for UNLCK bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to “0” affects INT0 and INT2 pins operation.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 41 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H INT1 Mask MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 0 0 0 1 1 1 MQIT1: Mask enable for QINT bit 0 : Mask disable 1 : Mask enable MCIT1: Mask enable for CINT bit 0 : Mask disable 1 : Mask enable MSTC1: Mask enable for STC bit 0 : Mask disable 1 : Mask enable MAUD1: Mask enable for AUDN bit 0 : Mask disable 1 : Mask enable MV1: Mask enable for V bit 0 : Mask disable 1 : Mask enable MAUT1: Mask enable for AUTO bit 0 : Mask disable 1 : Mask enable MPAR1: Mask enable for PAR bit 0 : Mask disable 1 : Mask enable MULK1: Mask enab le for UNLCK bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to “0” affects INT1 pin operation.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 42 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H DAT Mask & DTS Detect 0 0 0 0 DTS16 DTS14 MDAT1 MDAT0 R/W RD RD RD RD R/W R/W R/W R/W Default 0 0 0 0 1 1 1 1 MDAT0: Mask enable for DAT bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to “0” affects INT0 and INT2 pins operation. MDAT1: Mask enable for DAT bit 0 : Mask disable 1 : Mask enable The factor which mask bit is set to “0” affects INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0 : No detect 1 : Detect (Default) DTS16: DST-CD 16bit Sync Word Detect 0 : No detect 1 : Detect (Default)
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 43 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Receiver Status 0 UNLCK PAR AUTO V AUDN STC CINT QINT R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 QINT: Q-subcode Buffer Interrupt 0 : No change 1 : Changed This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH is updated. CINT: Channel Status Buffer Interrupt 0 : No change 1 : Changed This bit goes to “1” when C-bit stored in register addresses 0AH to 0EH changes. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0 : No detect 1 : D e t e c t This bit goes to “1” when either the FS3-0 or PEM bit changes. AUDN: Audio Bit Output 0 : Audio 1 : Non audio This bit is made by encoding channel status bits. V: Validity Bit 0 : Valid 1 : Invalid AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection 0 : No detect 1 : D e t e c t This bit outputs the OR’ed value of NPCM and DTSCD bits. PAR: Parity Error or Bi-phase Error Status 0 : No error 1 : Error This bit goes to “1” if a parity error or biphase error is detected in the sub-frame. UNLCK: PLL Lock Status 0 : L o c k 1 : Unlock QINT, CINT and STC bits are initialized when 07H is read.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 44 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Receiver Status 1 DAT DTSCD NPCM PEM FS3 FS2 FS1 FS0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 1 FS3-0: Sampling Frequency Detection (Table 17) PEM: Pre-emphasis Detect (Table 18) 0 : O F F 1 : O N This bit is made by encoding the channel status bits. NPCM: Non-PCM Bit Stream Auto Detection 0 : No detect 1 : D e t e c t DTSCD: DTS-CD Bit Stream Auto Detect 0 : No detect 1 : D e t e c t DAT: DAT Start ID Detect 0 : No detect 1 : D e t e c t When the category code shows DAT, “1” when the Start ID of DAT is detected. Reading 08H register resets it. DAT bit is initialized when 08H is read. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 09H Receiver Status 2 0 0 0 0 0 0 CCRC QCRC R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 QCRC: Cyclic Redundancy Check for Q-subcode 0 : No error 1 : Error CCRC: Cyclic Redundancy Check for Channel Status 0 : No error 1 : Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 45 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR1 5 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR2 3 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR3 1 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR3 9 CR38 CR37 CR36 CR35 CR34 CR33 CR32 R/W RD Default Not initialized CR39-0: Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every block (192 frames) cycle. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 13H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 14H Q-subcode Track Q17 Q1 6 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q2 4 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q3 2 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q4 0 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q5 6 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized Q81-2: Q-subcode All 80 bits are updated at the same time every sync code cycle for Q-subcode.
Figure 26. Data Structure of IEC60958 Table 22. Burst Preamble Word
Table 23. Field of Burst Information Pc
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 52 - PACKAGE 1 12 48 13 7.0 9.0 ± 0.2 7.0 9.0 ± 0.2 0.22 ± 0.08 48pin LQFP(Unit: mm) 0.10 37 24 2536 0.16 ± 0.07 1.40 ± 0.05 0.13 ± 0.13 1.70Max 0° ∼ 10° 0.10 0.5 ± 0.2 0.5 M Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 53 - MARKING AKM AK4122VQ XXXXXXX XXXXXXXX: Date code identifier
ASAHI KASEI [AK4122] MS0267-E-03 2004/08 - 54 -
Revision History
Date (YY/MM/DD) Revision Reason Page Contents 03/10/03 00 First Edition 04/01/27 01 Spec Change 10, 11 SWITCHING CHARACTERISTICS Audio Interface Timing BICK1/BICK2/BICK Period@Slave mode: min 160ns → 1/64/fs Add Spec 9 Add FILTER CHARACTERISTICS 04/07/23 02 Add Spec 16, 18 Add a sentence: “The DIF1-0 bits of the PORT1 should be set a value except “10” (I2S Compatible) when the DIR is selected as an input port.” 04/8/16 03 Add Spec 51 Add Jitter Tolerance IMPORTANT NOTICE
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