AK4121A_10 AKM | Alldatasheet

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[AK4121A] MS0337-E-06 2010/04 - 1 - GENERAL DESCRIPTION The AK4121A is a stereo asynchronous sample rate converter. The input sample rate ranges from 8kHz to 96kHz. The output sample rate is 32kHz, 44.1kHz, 48kHz or 96kHz. Since the internal PLL eliminates the need for a master clock in slave mode, the AK4121 simplifies the system design. Therefore, the AK4121A is suitable for applications requiring multiple sample rates, such as Car Audio, DVD recorders, and digital audio recording.

FEATURES

† Stereo asynchronous sample rate converter † Input sample rate range (FSI): 8kHz to 96kHz † Output sample rate (FSO): 32kHz/44.1kHz/48kHz/96kHz † Input to output Sample rate ratio: FSO/FSI = 0.33 to 6 † THD+N: –113dB † I/F format: MSB justified, LSB justified (24/20/16bit) and I2S † Clock for Master mode: 256/384/512/768fso † De-emphasis filter: 32kHz/44.1kHz/48kHz † SRC Bypass mode † Soft Mute function † Power Supply: VDD: 3.0 to 3.6V, TVDD: 3.0 to 5.5V (for input tolerant) † Ta: –40 to +85°C Serial Audio I/F Sample Rate Converter Serial Audio I/F ILRCK IBICK SDTI OLRCK OBICK SDTO (MCLK) PDN IDIF1 VDD DVSS PLL De-em filter DEM0 DEM1 IDIF0 ODIF1 ODIF0 IDIF2 CMODE0 SMUTE CMODE1 AVSS FILT TVDD CMODE2 soft mute Asynchronous Sample Rate Converter AK4121A

[AK4121A] MS0337-E-06 2010/04 - 2 - ■ Ordering Guide AK4121AVF −40 ∼ +85°C 24pin VSOP (0.65mm pitch) AKD4121A Evaluation Board for AK4121A ■ Pin Layout ■ Difference between AK4121 and AK4121A The AK4121A has a better performance than the AK4121 regarding of the tracking capability to the change of the input sampling frequency (FSI) which normally takes long se ttling time. Refer to “Tracking to the Input Sampling Frequency”.

1 FILT

9 SDTI

[AK4121A] MS0337-E-06 2010/04 - 3 - PIN/FUNCTION No. Pin Name I/O Function

1 FILT O Loop-Filter Pin for PLL

2 AVSS I Analog Ground Pin

3 PDN I Power-Down pin

When “L”, the AK4121A is powered-down and reset.

4 SMUTE I Soft Mute Pin

5 DEM0 I De-emphasis Filter Control Pin #0

6 DEM1 I De-emphasis Filter Control Pin #1

7 ILRCK I L/R Clock Pin for Input

8 IBICK I Audio Serial Data Clock Pin for Input

9 SDTI I Audio Serial Data Input Pin

10 IDIF0 I Input Data Format pin #0

11 IDIF1 I Input Data Format pin #1

12 IDIF2 I Input Data Format pin #2

13 CMODE0 I Clock Mode Select Pin #0

14 CMODE1 I Clock Mode Select Pin #1

15 CMODE2 I Clock Mode Select Pin #2

16 ODIF0 I Output Data Format pin #0

17 ODIF1 I Output Data Format pin #1

18 SDTO O Audio Serial Data Output Pin

19 OBICK I/O Audio Serial Data Clock Pin for Output

20 OLRCK I/O L/R Clock Pin for Output

21 MCLK I Master Clock Pin for Output

22 TVDD I Input Buffer Power Supply Pin, 3.3V or 5V

23 DVSS I Digital Ground Pin

24 VDD I Power Supply Pin, 3.3V

[AK4121A] MS0337-E-06 2010/04 - 4 - ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=0V; Note 1) Parameter Symbol min max Units Power Supplies: Core Input Buffer |AVSS-DVSS| ( Note 1) VDD TVDD Δ GND −0.3 −0.3 4.6 6.0 0.3 V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Input Voltage VIN −0.3 TVDD+0.3 V Ambient Temperature (Power applied) Ta −40 85 °C Storage Temperature Tstg −65 150 °C Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: Core Input Buffer VDD TVDD 3.0 VDD 3.3 3.6 5.5 V V Note 2. All voltages with respect to ground. SRC PERFORMANCE (Ta=−40∼85°C; VDD=3.0∼3.6V; TVDD=3.0~5.5V; data=20bit; measurement bandwidth=20Hz~FSO/2; unless otherwise specified.) Parameter Symbol min typ max Units Resolution 20 Bits Input Sample Rate FSI 8 96 kHz Output Sample Rate FSO 32 96 kHz Dynamic Range (Input= 1kHz, −60dBFS, Note 3) FSO/FSI=44.1kHz/48kHz FSO/FSI=48kHz/44.1kHz FSO/FSI=32kHz/48kHz FSO/FSI=96kHz/32kHz Worst Case (FSO/FSI=48kHz/96kHz) Dynamic Range (Input= 1kHz, −60dBFS, A-weighted, Note 3) FSO/FSI=44.1kHz/48kHz 112 114 114 114 115 117 dB dB dB dB dB dB T H D + N ( I n p u t = 1 k H z , 0 d B F S , Note 3) FSO/FSI=44.1kHz/48kHz FSO/FSI=48kHz/44.1kHz FSO/FSI=32kHz/48kHz FSO/FSI=96kHz/32kHz Worst Case (FSO/FSI=48kHz/8kHz) −113 −112 −113 −111 −103 dB dB dB dB dB Ratio between Input and Output Sample Rate (FSO/FSI, Note 4, Note 5) FSO/FSI 0.33 Note 3. Measured by Rohde & Schwarz UPD04, Rejection Filter= wide, 8192point FFT. Note 4. The “0.33” is the ratio of FSO/FSI when FSI is 96kHz and FSO is 32kHz Note 5. The “6” is the ratio when FSI is 8kHz and FSO is 48kHz.

[AK4121A] MS0337-E-06 2010/04 - 5 - DIGITAL FILTER (Ta=−40∼85°C; VDD=3.0∼3.6V; TVDD=3.0~5.5V) Parameter Symbol min typ max Units Digital Filter 0.985 ≤ FSO/FSI ≤ 6.000 PB 0 0.4583FSI kHz 0.905 ≤ FSO/FSI < 0.985 PB 0 0.4167FSI kHz 0.714 ≤ FSO/FSI < 0.905 PB 0 0.3195FSI kHz 0.656 ≤ FSO/FSI < 0.714 PB 0 0.2852FSI kHz 0.536 ≤ FSO/FSI < 0.656 PB 0 0.2245FSI kHz 0.492 ≤ FSO/FSI < 0.536 PB 0 0.2003FSI kHz 0.452 ≤ FSO/FSI < 0.492 PB 0 0.1781FSI kHz Passband −0.001dB 0.333 ≤ FSO/FSI < 0.452 PB 0 0.1092FSI kHz 0.985 ≤ FSO/FSI ≤ 6.000 SB 0.5417FSI kHz 0.905 ≤ FSO/FSI < 0.985 SB 0.5021FSI kHz 0.714 ≤ FSO/FSI < 0.905 SB 0.3965FSI kHz 0.656 ≤ FSO/FSI < 0.714 SB 0.3643FSI kHz 0.536 ≤ FSO/FSI < 0.656 SB 0.2974FSI kHz 0.492 ≤ FSO/FSI < 0.536 SB 0.2732FSI kHz 0.452 ≤ FSO/FSI < 0.492 SB 0.2510FSI kHz Stopband 0.333 ≤ FSO/FSI < 0.452 SB 0.1822FSI kHz Passband Ripple PR ±0.01 dB Stopband Attenuation SA 96 dB G r o u p D e l a y ( Note 6) GD - 57.5 - 1/fs Note 6. This value is the time from the rising edge of LRCK after data is input to rising edge of LRCK after data is output, when LRCK for Output data corresponds with LRCK for Input.(at 20bit MSB justified, 16bit and 20bit LSB justified) DC CHARACTERISTICS (Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V) Parameter Symbol min typ max Units Power Supply Current (VDD+TVDD) Normal operation: FSI=FSO=48kHz at Sl ave Mode: VDD=TVDD=3.3V FSI=FSO=96kHz at Master Mode: VDD=TVDD=3.3V : V D D = T V D D = 3 . 6 V P o w e r d o w n : P D N = “ L ” (Note 7) 100 mA mA mA μA High-Level Input Voltage Low-Level Input Voltage VIH VIL 0.7xVDD 0.3xVDD V V High-Level Output Voltage (Iout= −400μA) Low-Level Output Voltage (Iout=400 μA) VOH VOL VDD-0.4 0.4 V V Input Leakage Current Iin - - ± 10 μA Note 7. All digital inputs including clock pins are held DVSS.

[AK4121A] MS0337-E-06 2010/04 - 6 - SWITCHING CHARACTERISTICS (Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Input (MCLK) Frequency Duty Cycle fCLK dCLK 8.192 36.864 MHz L/R clock for Input data (ILRCK) Frequency Duty Cycle fs Duty kHz L/R clock for Output data (OLRCK) Frequency ( Note 8) fs 32 96 kHz Duty Cycle Slave Mode Duty 48 50 52 % Master Mode Duty 50 % Audio Interface Timing Input IBICK Period IBICK Pulse Width Low IBICK Pulse Width High ILRCK Edge to IBICK “↑” ( Note 9) ILRCK Frequency = 8kHz ~ 32kHz ILRCK Frequency = 32kHz ~ 48kHz ILRCK Frequency = 48kHz ~ 96kHz BICK “↑” t o I L R C K E d g e (Note 9) SDTI Hold Time from IBICK “↑” SDTI Setup Time to IBICK “↑” tBCK tBCKL tBCKH tLRB tLRB tLRB tBLR tSDH tSDS 1/64fs 1/256fs+45 1/256fs+25 1/256fs+15 16/256fs 16/256fs 16/256fs ns ns ns ns ns ns ns ns ns Output (Slave Mode) OBICK Period OBICK Pulse Width Low OBICK Pulse Width High OLRCK Edge to OBICK “↑” ( Note 9) OBICK “↑” t o O L R C K E d g e (Note 9) OLRCK to SDTO (MSB) OBICK “↓” to SDTO tBCK tBCKL tBCKH tLRB tBLR tLRS tBSD 1/64fs ns ns ns ns ns ns ns Output (Master Mode) BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO fBCK dBCK tMBLR tBSD −20 −20 64fs Hz ns ns Power-down & Reset Timing P D N P u l s e W i d t h ( Note 10) tPD 150 ns Note 8. Min is 8kHz when BYPASS=“H”. Note 9. BICK rising edge must not occur at the same time as LRCK edge. Note 10. The AK4121A must be reset by bringing PDN pin “H” to “L” upon power-up.

MCLK pin should be connected to DVSS. The CMODE2-0 pins must be controlled when PDN pin =“L”.

0 L L L 256fso (fso~96kHz) Master

1 L L H 384fso (fso~96kHz) Master

2 L H L 512fso (fso~48kHz) Master

3 L H H 768fso (fso~48kHz) Master

5 H L H - (Reserved)

6 H H L - (Reserved)

Table 1. Master/Slave control all modes the audio data is MSB-first, 2’s compliment format. The SDTO is clocked out on the falling edge of OBICK. Select these modes when PDN pin=“L”. In BYPASS mode, both IBICK and OBICK are fixed to 64fs.

0 L L L 16bit LSB Justified ≥32fs

1 L L H 20bit LSB Justified ≥40fs

2 L H L 20bit MSB Justified ≥40fs

3 L H H 20/16bit I 2S Compatible ≥40fs or 32fs

4 H L L 24bit LSB Justified ≥48fs

Table 2. Input Audio Data Formats

0 L L 16bit LSB Justified 64fs 64fs

1 L H 20bit LSB Justified 64fs 64fs

2 H L 20/16bit MSB Justified ( Note 13) ≥40fs or 32fs 64fs

3 H H 20/16bit I 2S Compatible (Note 13) ≥40fs or 32fs 64fs

Note 13. The 16bit output is available only when the OBICK = 32fs. Table 3. Output Audio Data Formats

When the SMUTE pin changes to “H”, the output signal is attenuated from 0dB to −∞dB during 1024 OLRCK cycles. to 0dB by the same cycles. The soft mute is effective for changing the signal source. (1) Transition time. 1024 OLRCK cycles (1024/fso). and returned to 0dB by the same number of clock cycles. Figure 8. Soft Mute

1 L H OFF

2 H L 48kHz

3 H H 32kHz

Table 4. De-emphasis Filter Control

time, please refer to the Table 5. Until the output data becomes valid, the SDTO pin outputs “L”. Figure 9. System Reset Table 5. Reset time ta and Data valid time tb.

The recommended sequence for changing clocks is shown in Figure 10. Figure 10. Sequence of changing clocks changes to “L”, which will cause the data on SDTO to remain “0”. from the timing PDN pin changes to “H” while the SMUTE pin = “H”. (typ) after changing clocks.

the system’s analog supply. AVSS and DVSS of the AK4121A must be connected to the analog ground plane. noise should be placed as near to VDD as possible. with C2 (1.0nF). A Care should be taken to ensure that noise on the FILT pin is minimized. Note 14. Those recommended values include temperature dependence. Figure 11. PLL Loop-Filter

[AK4121A] MS0337-E-06 2010/04 - 17 - PACKAGE 0.1±0.1 0-10° Detail A Seating Plane NOTE: Dimension "*" does not include mold flash. 0.10 0.150.22±0.1 0.65 *7.9±0.2 1.25±0.2 A 1 12 13 24 24pin VSOP (Unit: mm) 7.6±0.2 0.5±0.2 *5.6±0.2 +0.1 -0.05 ■ Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb free)

[AK4121A] MS0337-E-06 2010/04 - 18 - MARKING AKM AK4121AVF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code

[AK4121A] MS0337-E-06 2010/04 - 19 -

REVISION HISTORY

Date (YY/MM/DD) Revision Reason Page Contents 04/09/01 00 First Edition 07/06/05 01 Error Correct 4 SRC PERFORMANCE Dynamic Range, Worst Case FSO/FSI=32kHz/44.1kHz → 48kHz/96kHz

Description

ILRCK Edge to IBICK “ ↑” is changed to ILRCK period (8kHz ~ 32kHz): 1/256fs+45 ILRCK period (32kHz ~ 48kHz): 1/256fs+25 ILRCK period (48kHz ~ 96kHz): 1/256fs+15 07/07/25 02 Description Change 13 ■ Internal Reset Function for Clock Change ■ Sequence of Changing Clocks 07/09/14 03 Add Spec 6 Max values of ILRCK Edge to IBICK “↑” were added. ILRCK Frequency =8kHz ~ 32kHz: 16/256fs ILRCK Frequency =32kHz ~ 48kHz: 16/256fs ILRCK Frequency =48kHz ~ 96kHz: 16/256fs Error Correct 6 The Symbol of ILRCK Edge to IBICK “↑” tBLR → tLRB The Symbol of IBICK “↑” to ILRCK Edge tLRB → tBLR The Symbol of OLRCK Edge to OBICK “↑” tBLR → tLRB The Symbol of OBICK “↑” to OLRCK Edge tLRB → tBLR 08/03/05 04 Description Addition 9 Note 13. was added. 08/04/05 05 Description Change 5 DC CHARACTERISTICS Power Supply Current (VDD+TVDD) description was added. VDD =3.3V → VDD=TVDD=3.3V VDD= 3.6V → VDD=TVDD=3.6V 10/04/30 06 Description Addition 13 ■ Sequence of changing clocks Description is added in notes.

[AK4121A] MS0337-E-06 2010/04 - 20 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these product s, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustra te the operation and application exam ples of the semiconductor products. You are fully responsible for the incorporation of these ex ternal circuits, application circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these inform ation herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medi cine, aerospace, nuclear energy, or ot her fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.