AK4117_10 AKM | Alldatasheet
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Technical content
[AK4117] MS0157-E-04 2010/08 - 1 - GENERAL DESCRIPTION The AK4117 is a S/PDIF AES/EBU re ceiver supporting sample rates up to 192kHz and resolution up to 24-bit. The integrated channel status decoder suppor ts both consumer and professional modes. The AK4117 can automatically detect a Non-PCM bit st ream. Combining the AK4117 with a multi-channel codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be controlled via microprocessor serial interface. A low power mode is available for normal speed modes and the small 24pin VSOP package saves board space. *AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low jitter Analog PLL PLL Lock Range : 32kHz to 192kHz Clock Source: PLL or X'tal 2-channel Receiver inputs Selector Auxiliary digital input Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, 192kHz) - Unlock & Parity Error Detection - Validity Flag Detection Up to 24bit Audio Data Format Audio I/F: Left justified, Right justified (16bit, 18bit, 20bit, 24bit), I 40-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream 4-wire Serial µP I/F Master Clock Output: 128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V Small Package: 24pin VSOP Ta: -40 to 85°C Low Power 192kHz Digital Audio Receiver AK4117
[AK4117] MS0157-E-04 2010/08 - 2 - ■ Block Diagram Input Selector Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect µP I/F Audio I/F X'tal Oscillator PDN INT0 LRCK BICK SDTO DAUX XTOXTIRAVDDAVSS CDTI CDTO CCLK CSN DVDD DVSS MCKO RX0 RX1 Error & Detect STATUS INT1 Q-subcode buffer 2 to 1 UOUT
[AK4117] MS0157-E-04 2010/08 - 3 - ■ Ordering Guide AK4117VF -40 ~ +85 °C 24pin VSOP (0.65mm pitch) ■ Pin Layout 1 R AVDD NC RX1 RX0 DVDD DVSS 7 XTI 8 AVSS PDN INT0 INT1 CSN CCLK CDTI CDTO Top View
9 XTO
[AK4117] MS0157-E-04 2010/08 - 4 - PIN/FUNCTION No. Pin Name I/O Function
1 R - External Resistor Pin
12kΩ-5% ~ 13kΩ+5% resistor to A VSS externally.
2 A VDD - Analog Power Supply Pin
3 RX1 I Receiver Channel 1 (Internal Biased Pin)
4 NC - No Connect
No internal bonding.
5 RX0 I Receiver Channel 0 (Internal Biased Pin)
6 DVDD - Digital Power Supply Pin
7 DVSS - Digital Ground Pin
8 XTI I X'tal Input Pin
9 XTO O X'tal Output Pin
10 LRCK O Output Channel Clock Pin
11 BICK O Audio Serial Data Clock Pin
12 SDTO O Audio Serial Data Output Pin
13 DAUX I Auxiliary Audio Data Input Pin
14 MCKO O Master Clock Output Pin
15 NC - No Connect
No internal bonding.
16 UOUT O U-bit Output Pin
When UOUTE bit = “0”, UOUT pin = “L”.
17 CDTO O Control Data Output Pin
18 CDTI I Control Data Input Pin
19 CCLK I Control Data Clock Pin
20 CSN I Chip Select Pin
21 INT1 O Interrupt 1 Pin
22 INT0 O Interrupt 0 Pin
23 PDN I
Power-Down & Reset Pin When “L”, the AK4117 is powered-down and reset, and all output pins go to “L” and the control registers are reset to default state.
24 A VSS - Analog Ground Pin
Note 1: All input pins except internal biased pins should not be left floating.
[AK4117] MS0157-E-04 2010/08 - 5 - ABSOLUTE MAXIMUM RATINGS (AVSS=DVSS=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog Digital |AVSS-DVSS| ( Note 3) AVDD DVDD ΔGND -0.3 -0.3 4.6 4.6 0.3 V V V Input Current (Any pins except supplies) IIN - ±10 mA Input Voltage (Except RX0, RX1 pins) (RX0, RX1 pins) VIN1 VIN2 -0.3 -0.3 DVDD+0.3 AVDD+0.3 V V Ambient Temperature (Power applied) Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note 2. All voltages with respect to ground. Note 3. A VSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS=DVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: Analog Digital AVDD DVDD 2.7 2.7 3.3 3.3 3.6 AVDD V V Note 2. All voltages with respect to ground. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V) Parameter Symbol min typ max Units Input Resistance Zin - 10 - kΩ Input Voltage VTH 350 mVpp Input Sample Frequency fs 32 - 192 kHz DC CHARACTERISTICS (Ta=25°C; AVDD=DVDD=2.7~3.6V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation (PDN= “H”) ( Note 4) LP= “0”, CM1-0= “00” ( Note 5) LP= “1”, CM1-0= “00” ( Note 6) LP= “1”, CM1-0= “01” ( Note 7) Power down (PDN = “L”) ( Note 8) 100 mA mA mA μA High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD DVSS-0.3 DVDD+0.3 30%DVDD V V High-Level Output Voltage (Iout=-400 μA) Low-Level Output Voltage (Iout=400 μA) VOH VOL DVDD-0.4 0.4 V V Input Leakage Current Iin - - ± 10 μA Note 4. A VDD=DVDD=3.3V . Note 5. fs=192kHz, X'tal=24.576MHz, PCKS1-0= “10” , C L=20pF. A VDD=5mA (typ), DVDD=9mA (typ). Note 6. fs=48kHz, X'tal=24.576MHz, CL=20pF. A VDD=4mA (typ), DVDD=3mA (typ). Note 7. fs=48kHz, X'tal=24.576MHz. The external load current is not included. Note 8. RX inputs are open and all digital input pins are held at DVDD or DVSS.
[AK4117] MS0157-E-04 2010/08 - 6 - SWITCHING CHARACTERISTICS (Ta=25 °C; A VDD=DVDD=2.7~3.6V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty Cycle fECLK dECLK 2.048 24.576 MHz MCKO Output Frequency Duty Cycle ( Note 9) fMCK dMCK 1.024 24.576 MHz PLL Clock Recover Frequency (RX0, RX1) fpll 32 - 192 KHz LRCK Timing Frequency PLL mode X’tal mode External Clock mode Duty Cycle fs fs fs dLCK 44.1 192 192 192 kHz kHz kHz Audio Interface Timing BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -20 64fs Hz ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width tPW 150 ns Note 9. Except the external clock input.
sync word of a DTS-CD bitstream, while it does not detect 16bit sync word (0x7FFE8001). received sync interval is incorrect. The AK4117 has two sources for MCKO and SDTO. 1) MCKO and SDTO source is recovered by PLL from RX input. 2) MCKO source is X’tal or External clock. SDTO source is DAUX input. recovery frequency be set differently.
0 ON ON PLL RX 2 1 0 1 ON ON X'tal DAUX
Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Table 1. Clock Operation Mode select
lock range is up to 48kHz and the MCKO frequency is fixed to 256fs. the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 3). Table 2. Master Clock Frequency Select Table 3. Master Clock Frequency Select
When XTL1-0= “11”, FS3-0 bits indicate the decoded sampling frequency information from channel status. Table 4. Reference X’tal frequency 32kHz, FS3-0 bits may indicate “0001”. Note 11. In consumer mode, Byte3 Bit3-0 are copied to FS3-0. Table 5. Sampling frequency information default (CS12=0). It can be switched to channel 2 by changing the CS12 bit in the control register.
0 OFF ≠ 0X100 ≠110
1 ON 0X100 110
Table 6. Pre-emphasis information
once at power-up by bringing PDN pin = “L”. are initialized and clocks are stopped. Read/write operations to the registers are disabled. RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled. are not initialized. Read/write operations to the registers are enabled. (user data) can be output from the UOUT pin.
0 RX0 Default
1 RX1
Table 7. Recovery Data Select Figure 11. UOUT output timing
There are eight events which cause the INT1-0 pins to go “H”.
- UNLCK: PLL unlock state detect
not correct or when those preambles are not correct.
- PAR: Parity error or biphase coding error detection
- AUTO: Non-PCM or DTS-CD Bit Stream detection
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
- V: Validity flag detection
“1” when validity flag is detected. Updated every sub-frame cycle.
- AUDION: Non-audio detection
“1” when the “AUDIO” bit in recovered channel status indicates “1”. Updated every block cycle.
- STC: Sampling frequency or pre-emphasis information change detection
“1” when FS3-0 or PEM bit changes. Reading this register resets it.
- QINT: U bit (Q-subcode) sync flag
every sync code cycle for Q-subcode. Reading this register resets it.
- CINT: Channel status sync flag
every block cycle. Reading this register resets it. not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared. the PLL is OFF (Clock Operation Mode 1). Table 8. Interrupt handling
Figure 17. INT1-0 pin timing
Figure 18. Interrupt Handling Sequence Example 1
Figure 19. Interrupt Handling Sequence Example (for Q/CINT)
are truncated. In Modes 3-7, the last four LSBs are auxiliary data (see Figure 20). Figure 20. Bit configuration Table 9. Audio data format
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. Figure 25. 4-wire Serial Control I/F Timing
[AK4117] MS0157-E-04 2010/08 - 24 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control 0 0 0 EXCK XTL1 XTL0 PWN RSTN 01H Clock Control LP PCKS1 PCKS0 DIV XCKS1 XCKS0 CM1 CM0 02H Input/Output Control IPS UOUTE CS12 EFH1 EFH0 DIF2 DIF1 DIF0 03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 04H INT1 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT 06H Receiver status 1 0 DTSCD NPCM PEM FS3 FS2 FS1 FS0 07H Receiver status 2 0 0 0 0 0 0 CCRC QCRC 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD 7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD 15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 11H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 13H Q-subcode Index Q25 Q 24 Q23 Q22 Q21 Q20 Q19 Q18 14H Q-subcode Minute Q33 Q 32 Q31 Q30 Q29 Q28 Q27 Q26 15H Q-subcode Second Q41 Q 40 Q39 Q38 Q37 Q36 Q35 Q34 16H Q-subcode Frame Q49 Q 48 Q47 Q46 Q45 Q44 Q43 Q42 17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 Note: When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is rese t and all registers except RSTN, PWN, XTL1-0 and EXCK bits are initialized to their default values. All data can be written to the registers even if PWN bit is “0”.
[AK4117] MS0157-E-04 2010/08 - 25 - ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Power Down Control 0 0 0 EXCK XTL1 XTL0 PWN RSTN R/W RD RD RD R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 1 RSTN: Timing Reset & Register Initialize 0: Reset & Initialize (except RSTN, PWN, XTL1-0 and EXCK bits) 1: Normal Operation (Default) PWN: Power-Down for Clock Recovery Part 0: Power Down 1: Normal Operation (Default) XTL1-0: Reference X’tal Frequency Select (Table 4; Default: 00) EXCK: External Clock Mode Select 0: X’tal mode (Default) 1: External clock mode (Feedback resistor of X’tal oscillator circuit is open.) Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Clock Control LP PCKS1 PCKS0 DIV XCKS1 XCKS0 CM1 CM0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 1 0 0 1 0 0 CM1-0: Master Clock Operation Mode Select (Table 1; Default: 00) XCKS1-0: Master Clock Frequency Select at X’tal Mode (Table 3; Default: 01) DIV: Master Clock Output Select at X’tal Mode 0: Same frequency as X’tal (Default) 1: Half frequency of X’tal PCKS1-0: Master Clock Frequency Select at PLL Mode (Table 2; Default: 01) LP: Low Power Mode Select (Table 2) 0: Normal mode 1: Low power mode (Default) In low power mode, fs cannot exceed 48kHz.
[AK4117] MS0157-E-04 2010/08 - 26 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Format Control IPS UOUTE C S12 EFH1 EFH0 DIF2 DIF1 DIF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 1 1 0 0 DIF2-0: Audio Data Format Control (Table 9; Default: 100) EFH1-0: INT0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK (Default) 10: 2048 LRCK 11: 4096 LRCK CS12: Channel Status Select 0: Channel 1 (Default) 1: Channel 2 This bit selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3-0, Pc, Pd and CRC. UOUTE: U-bit Output Enable 0: Disable (Default) 1: Enable. U-bit is output from UOUT pin. IPS: Input Recovery Data Select ( Table 7) 0: RX0 (Default) 1: RX1
[AK4117] MS0157-E-04 2010/08 - 27 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 1 1 1 1 1 MQIT0: Mask Enable for QINT bit MCIT0: Mask Enable for CINT bit MSTC0: Mask Enable for STC bit MAUD0: Mask Enable for AUDION bit MV0: Mask Enable for V bit MAUT0: Mask Enable for AUTO bit MPAR0: Mask Enable for PAR bit MULK0: Mask Enable for UNLOCK bit 0: Mask disable 1: Mask enable The factor which mask bit is set to “0” affects INT0 pin operation. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H INT0 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 1 1 0 0 0 1 1 1 MQIT1: Mask Enable for QINT bit MCIT1: Mask Enable for CINT bit MSTC1: Mask Enable for STC bit MAUD1: Mask Enable for AUDION bit MV1: Mask Enable for V bit MAUT1: Mask Enable for AUTO bit MPAR1: Mask Enable for PAR bit MULK1: Mask Enable for UNLOCK bit 0: Mask disable 1: Mask enable The factor whose mask bit is set to “0” affects INT1 pin operation.
[AK4117] MS0157-E-04 2010/08 - 28 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when Q-subcode stored in register addresses 11H to 1AH is updated. CINT: Channel Status Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when C-bit stored in register addresses 08H to 0CH changes. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0: No detect 1: Detect This bit goes to “1” when either the FS3-0 or PEM bit changes. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. V: Validity Bit 0 : V a l i d 1 : I n v a l i d AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection 0: No detect 1: Detect This bit outputs the OR’ed value of NPCM and DTSCD bits. PAR: Parity Error or Biphase Error Status 0 : N o E r r o r 1 : E r r o r This bit goes to “1” if a parity error or biphase error is detected in the sub-frame. UNLCK: PLL Lock Status 0 : L o c k 1 : U n l o c k QINT, CINT, STC and PAR bits are initialized when 05H is read.
[AK4117] MS0157-E-04 2010/08 - 29 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H Receiver status 1 0 DTSC D NPCM PEM FS3 FS2 FS1 FS0 R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 1 FS3-0: Sampling Frequency Detection (Table 5) PEM: Pre-emphasis Detect 0 : O F F 1 : O N This bit is made by encoding the channel status bits. NPCM: Non-PCM Bit Stream Auto Detection 0 : N o d e t e c t 1 : D e t e c t DTSCD: DTS-CD Bit Stream Auto Detect 0 : N o d e t e c t 1 : D e t e c t Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 07H Receiver status 2 0 0 0 0 0 0 CCRC QCRC R/W RD RD RD RD RD RD RD RD Default 0 0 0 0 0 0 0 0 QCRC: Cyclic Redundancy Check for Q-subcode 0 : N o E r r o r 1 : E r r o r CCRC: Cyclic Redundancy Check for Channel Status 0 : N o E r r o r 1 : E r r o r This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
[AK4117] MS0157-E-04 2010/08 - 30 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 R/W RD Default Not initialized CR39-0: Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every block (192 frames) cycle. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC 14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 11H Q-subcode Address / Control Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 13H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 14H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 15H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 16H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized Q2-81: Q-subcode (Figure 14 and Figure 15) All 80 bits are updated at the same time every sync code cycle for Q-subcode.
Figure 26. Data structure in IEC60958 Table 10. Burst preamble words
Table 11. Fields of burst info Pc
[AK4117] MS0157-E-04 2010/08 - 35 - PACKAGE 0.1±0.1 0-10° Detail A Seating Plane NOTE: Dimension "*" does not include mold flash. 0.10 *7.8±0.15 1.25±0.2 A 1 12 1324 24pin VSOP (Unit: mm) 7.6±0.2 0.5±0.2 *5.6±0.2 ■ Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
[AK4117] MS0157-E-04 2010/08 - 36 - MARKING AKM AK4117VF AAXXXX Contents of AAXXXX AA: Lot# XXXX: Date Code Date (YY/MM/DD) Revision Reason Page Contents 02/05/27 00 First Edition 02/12/12 01 Error Correction
3 Pin Lay Out
Pin#14: MCLK → MCKO
21 Audio Serial Interface Format
1 General Description
“Mode settings can be controlled via microprocessor serial interface or via dedicated pin.” → “Mode settings can be controlled via microprocessor serial interface.” 04/04/19 03 Error Correction 16 Figure 16.Q-subcode register map Addr = 16H~1FH → 11H~1AH 32 Table 11. Fields of burst info Pc Value 7: reserved → MPEG2 AAC ADTS; repetition time of burst: 1024 Value 14: reserved → ATRAC; repetition time of burst: 512 Value 15: reserved → ATRAC2/3; repetition time of burst: 1024 Value 27: (Reserved for MPEG-4 AAC data) → reserved Value 28: MPEG-2 AAC data → reserved 10/08/11 04 Error Correction 11 Table 3. EXTCLK range was changed.
REVISION HISTORY
[AK4117] MS0157-E-04 2010/08 - 37 - IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, a pplication circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the in corporation of these external circuits, app lication circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor authorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.