AK4116 AKM | Alldatasheet
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Technical content
[AK4116] MS0156-E-02 - 1 - GENERAL DESCRIPTION The AK4116 is a low power S/PDIF AES/EBU receiver supporting resolution up to 24-bit. The integrated channel status decoder supports both consumer and professional modes. The AK4116 can automatically detect a Non-PCM bit stream. Combining the AK4116 with a multi-channel codec such as AKM’s AK4527B or AK4529 can create a complete AC-3 system. Mode settings can be controlled via microprocessor serial interface. The small 20pin QFN package saves board space. *AC-3 is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low jitter Analog PLL PLL Lock Range : 32kHz to 48kHz Clock Source: PLL or X'tal Auxiliary digital input Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection (32kHz, 44.1kHz, 48kHz) - Unlock & Parity Error Detection - Validity Flag Detection Up to 24bit Audio Data Format Audio I/F: Left justified, Right justified (16bit, 18bit, 20bit, 24bit), I2S 40-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream 4-wire Serial µP I/F Master Clock Output: 256fs Operating Voltage: 2.7 to 3.6V Power Supply Current: 7mA (PLL mode) 2mA (X’tal mode) Small Package: 20pin QFN Ta: -40 to 85°C Low Power 48kHz Digital Audio Receiver AK4116
[AK4116] MS0156-E-02 - 2 - Block Diagram Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect µP I/F Audio I/F X'tal Oscillator PDN INT0 LRCK BICK SDTO DAUX XTO XTI R AVDD AVSS CDTI CDTO CCLK CSN DVDD DVSS MCKO Error & Detect STATUS INT1 Q-subcode buffer RX0
[AK4116] MS0156-E-02 - 3 - Ordering Guide AK4116VF -40 ~ +85 °C 20pin QFN (0.5mm pitch) Pin Layout RX0 AVDD DVDD DVSS XTI XTO R AVSS LRCK BICK SDTO DAUX MCKO INT1 CSN CCLK CDTI CDTO Top View PDN INT0
[AK4116] MS0156-E-02 - 4 - PIN/FUNCTION No. Pin Name I/O Function RX0 I Receiver Channel 0 (Internal Biased Pin) DVDD Digital Power Supply Pin DVSS Digital Ground Pin XTI I X'tal Input Pin XTO O X'tal Output Pin LRCK O Output Channel Clock Pin BICK O Audio Serial Data Clock Pin SDTO O Audio Serial Data Output Pin DAUX I Auxiliary Audio Data Input Pin MCKO O Master Clock Output Pin CDTO O Control Data Output Pin CDTI I Control Data Input Pin CCLK I Control Data Clock Pin CSN I Chip Select Pin INT1 O Interrupt 1 Pin INT0 O Interrupt 0 Pin PDN I Power-Down & Reset Pin When “L”, the AK4116 is powered-down and reset, and all output pins go to “L” and the control registers are reset to default state. AVSS Analog Ground Pin R External Resistor Pin 12kΩ-5% ~ 13kΩ+5% resistor to AVSS externally. AVDD Analog Power Supply Pin Note 1: All input pins except internal biased pins should not be left floating.
[AK4116] MS0156-E-02 - 5 - ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog Digital |AVSS-DVSS| (Note 3) AVDD DVDD ∆GND -0.3 -0.3 4.6 4.6 0.3 V V V Input Current (Any pins except supplies) IIN ±10 mA Input Voltage (Except RX0, RX1 pins) (RX0, RX1 pins) VIN1 VIN2 -0.3 -0.3 DVDD+0.3 AVDD+0.3 V V Ambient Temperature (Power applied) Ta -40 Storage Temperature Tstg -65 150 Note 2. All voltages with respect to ground. Note 3. AVSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: Analog Digital AVDD DVDD 2.7 2.7 3.3 3.3 3.6 AVDD V V Note 2. All voltages with respect to ground. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V) Parameter Symbol min typ max Units Input Resistance Zin kΩ Input Voltage VTH 350 mVpp Input Sample Frequency fs kHz DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation (PDN= “H”) (Note 4) CM1-0= “00” (Note 5) CM1-0= “01” (Note 6) Power down (PDN = “L”) (Note 7) 100 mA mA µA High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD DVSS-0.3 DVDD+0.3 30%DVDD V V High-Level Output Voltage (Iout=-400µA) Low-Level Output Voltage (Iout=400µA) VOH VOL DVDD-0.4 0.4 V V Input Leakage Current Iin ± 10 µA Note 4. AVDD=DVDD=3.3V. Note 5. fs=48kHz, X'tal=24.576MHz, CL=20pF. AVDD=5mA (typ), DVDD=9mA (typ). Note 6. fs=48kHz, X'tal=24.576MHz. The external load current is not included. Note 7. RX inputs are open and all digital input pins are held at DVDD or DVSS.
[AK4116] MS0156-E-02 - 6 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty Cycle fECLK dECLK 2.048 24.576 MHz MCKO Output Frequency Duty Cycle (Note 8) fMCK dMCK 1.024 24.576 MHz PLL Clock Recover Frequency (RX0) fpll KHz LRCK Timing Frequency PLL mode X’tal mode External Clock mode Duty Cycle fs fs fs dLCK 44.1 kHz kHz kHz Audio Interface Timing BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -20 64fs Hz ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width tPW 150 ns Note 8. Except the external clock input.
has a DTS-CD bitstream auto-detection function. When AK4116 detects DTS-CD bitstreams, the DTSCD bit goes to “1”. word of a DTS-CD bitstearm, while it does not detect 16bit sync word (0x7FFE8001). oscillator or the channel status information. The PLL loses lock when the received sync interval is incorrect. The AK4116 has two sources for MCKO and SDTO. 1) MCKO and SDTO source is recovered by PLL from RX input. 2) MCKO source is X’tal or External clock. SDTO source is DAUX input. recovery frequency be set differently. Note : When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is off. Table 1. Clock Operation Mode select
frequency is fixed to 256fs. the ratio (x1 or x1/2) of the MCKO frequency to the X’tal frequency (Table 2). Table 2. Master Clock Frequency Select
When XTL1-0= “11”, FS3-0 bits indicate the decoded sampling frequency information from channel status. Table 3. Reference X’tal frequency 32kHz, FS3-0 bits indicate any values except 32kHz, 44.1kHz and 48kHz. Note 2: In consumer mode, Byte3 Bit3-0 are copied to FS3-0. Table 4. Sampling frequency information default (CS12=0). It can be switched to channel 2 by changing the CS12 bit in the control register. Table 5. Pre-emphasis information
[AK4116] MS0156-E-02 - 14 - System Reset and Power-Down The AK4116 has a full power-down mode for all circuits that is activated by the PDN pin, and a partial power-down mode activated by the PWN bit. The RSTN bit initializes the internal registers and timing. The AK4116 should be reset once at power-up by bringing PDN pin = “L”. PDN Pin: All analog and digital circuits are placed in power-down and reset modes by bringing PDN= “L”. All the registers are initialized and clocks are stopped. Read/write operations to the registers are disabled. RSTN Bit (Address 00H; D0): All the registers except RSTN, PWN, XTL1-0 and EXCK are initialized by bringing RSTN bit = “0”. The internal timings are also initialized. When RSTN bit= “0”, clocks are output, but SDTO is “L”. All register writes except RSTN, PWN, XTL1-0 and EXCK are disabled. Reading from the registers is enabled. PWN Bit (Address 00H; D1): Clock recovery mode is initialized by bringing PWN bit = “0”. Clocks from the PLL are stopped while the X’tal clocks continue to be output. Unlike the PDN pin operation described above, internal registers and mode settings are not initialized. Read/write operations to the registers are enabled.
There are eight events which cause the INT1-0 pins to go “H”.
- UNLCK: PLL unlock state detect
not correct or when those preambles are not correct. The OR function of NPCM and DTSCD bits is output to the AUTO bit. “1” when validity flag is detected. Updated every sub-frame cycle.
- AUDION: Non-audio detection
“1” when the “AUDIO” bit in recovered channel status indicates “1”. Updated every block cycle. “1” when FS3-0 or PEM bit changes. Reading this register resets it. every sync code cycle for Q-subcode. Reading this register resets it. every block cycle. Reading this register resets it. not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared. the PLL is OFF (Clock Operation Mode 1). Table 6. Interrupt handling
Figure 16. INT1-0 pin timing
Figure 17. Interrupt Handling Sequence Example 1
Figure 18. Interrupt Handling Sequence Example (for Q/CINT)
are truncated. In Modes 3-7, the last four LSBs are auxiliary data (see Figure 19). Figure 19. Bit configuration Table 7. Audio data format
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. Figure 24. 4-wire Serial Control I/F Timing
[AK4116] MS0156-E-02 - 24 - Register Map Addr Register Name 00H Power Down Control EXCK XTL1 XTL0 PWN RSTN 01H Clock Control DIV XCKS1 XCKS0 CM1 CM0 02H Input/Output Control CS12 EFH1 EFH0 DIF2 DIF1 DIF0 03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 04H INT1 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT 06H Receiver status 1 DTSCD NPCM PEM FS3 FS2 FS1 FS0 07H Receiver status 2 CCRC QCRC 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 11H Q-subcode Address / Control 12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 13H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 14H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 15H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 16H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 Note: When PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit goes to “0”, the internal timing is reset and all registers except RSTN, PWN, XTL1-0 and EXCK bits are initialized to their default values. All data can be written to the registers even if PWN bit is “0”.
[AK4116] MS0156-E-02 - 25 - Register Definitions Addr Register Name 00H Power Down Control EXCK XTL1 XTL0 PWN RSTN R/W RD RD RD R/W R/W R/W R/W R/W Default RSTN: Timing Reset & Register Initialize 0: Reset & Initialize (except RSTN, PWN, XTL1-0 and EXCK bits) 1: Normal Operation (Default) PWN: Power-Down for Clock Recovery Part 0: Power Down 1: Normal Operation (Default) XTL1-0: Reference X’tal Frequency Select (Table 3; Default: 00) EXCK: External Clock Mode Select 0: X’tal mode (Default) 1: External clock mode (Feedback resistor of X’tal oscillator circuit is open.) Addr Register Name 01H Clock Control DIV XCKS1 XCKS0 CM1 CM0 R/W RD RD RD R/W R/W R/W R/W R/W Default CM1-0: Master Clock Operation Mode Select (Table 1; Default: 00) XCKS1-0: Master Clock Frequency Select at X’tal Mode (Table 2; Default: 01) DIV: Master Clock Output Select at X’tal Mode 0: Same frequency as X’tal (Default) 1: Half frequency of X’tal
[AK4116] MS0156-E-02 - 26 - Addr Register Name 02H Format Control CS12 EFH1 EFH0 DIF2 DIF1 DIF0 R/W RD RD R/W R/W R/W R/W R/W R/W Default DIF2-0: Audio Data Format Control (Table 7; Default: 100) EFH1-0: INT0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK (Default) 10: 2048 LRCK 11: 4096 LRCK CS12: Channel Status Select 0: Channel 1 (Default) 1: Channel 2 This bit selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3-0, Pc, Pd and CRC.
[AK4116] MS0156-E-02 - 27 - Addr Register Name 03H INT0 MASK MULK0 MPAR0 MAUT0 MV0 MAUD0 MSTC0 MCIT0 MQIT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MQIT0: Mask Enable for QINT bit MCIT0: Mask Enable for CINT bit MSTC0: Mask Enable for STC bit MAUD0: Mask Enable for AUDION bit MV0: Mask Enable for V bit MAUT0: Mask Enable for AUTO bit MPAR0: Mask Enable for PAR bit MULK0: Mask Enable for UNLOCK bit 0: Mask disable 1: Mask enable The factor which mask bit is set to “0” affects INT0 pin operation. Addr Register Name 04H INT0 MASK MULK1 MPAR1 MAUT1 MV1 MAUD1 MSTC1 MCIT1 MQIT1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MQIT1: Mask Enable for QINT bit MCIT1: Mask Enable for CINT bit MSTC1: Mask Enable for STC bit MAUD1: Mask Enable for AUDION bit MV1: Mask Enable for V bit MAUT1: Mask Enable for AUTO bit MPAR1: Mask Enable for PAR bit MULK1: Mask Enable for UNLOCK bit 0: Mask disable 1: Mask enable The factor whose mask bit is set to “0” affects INT1 pin operation.
[AK4116] MS0156-E-02 - 28 - Addr Register Name 05H Receiver status 0 UNLCK PAR AUTO V AUDION STC CINT QINT R/W RD RD RD RD RD RD RD RD Default QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when Q-subcode stored in register addresses 11H to 1AH is updated. CINT: Channel Status Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when C-bit stored in register addresses 08H to 0CH changes. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0: No detect 1: Detect This bit goes to “1” when either the FS3-0 or PEM bit changes. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. V: Validity Bit 0: Valid 1: Invalid AUTO: Non-PCM or DTS-CD Bit Steam Auto Detection 0: No detect 1: Detect This bit outputs the OR’ed value of NPCM and DTSCD bits. PAR: Parity Error or Biphase Error Status 0:No Error 1:Error This bit goes to “1” if a parity error or biphase error is detected in the sub-frame. UNLCK: PLL Lock Status 0: Lock 1: Unlock QINT, CINT, STC and PAR bits are initialized when 05H is read.
[AK4116] MS0156-E-02 - 29 - Addr Register Name 06H Receiver status 1 DTSCD NPCM PEM FS3 FS2 FS1 FS0 R/W RD RD RD RD RD RD RD RD Default FS3-0: Sampling Frequency Detection (Table 4) PEM: Pre-emphasis Detect 0: OFF 1: ON This bit is made by encoding the channel status bits. NPCM: Non-PCM Bit Stream Auto Detection 0: No detect 1: Detect DTSCD: DTS-CD Bit Stream Auto Detect 0: No detect 1: Detect Addr Register Name 07H Receiver status 2 CCRC QCRC R/W RD RD RD RD RD RD RD RD Default QCRC: Cyclic Redundancy Check for Q-subcode 0: No Error 1: Error CCRC: Cyclic Redundancy Check for Channel Status 0: No Error 1: Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit.
[AK4116] MS0156-E-02 - 30 - Addr Register Name 08H RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 09H RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0AH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0BH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0CH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 R/W RD Default Not initialized CR39-0: Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every block (192 frames) cycle. Addr Register Name 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 Addr Register Name 11H Q-subcode Address / Control 12H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 13H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 14H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 15H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 16H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 17H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 18H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 19H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1AH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized Q2-81: Q-subcode (Figure 14 and Figure 15) All 80 bits are updated at the same time every sync code cycle for Q-subcode.
[AK4116] MS0156-E-02 - 31 - Burst Preambles in non-PCM Bitstreams 16 bits of bitstream 11 12 27 28 29 30 31 preamble Aux. LSB MSB V U C P sub-frame of IEC60958 Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 25. Data structure in IEC60958
Contents
Table 8. Burst preamble words
[AK4116] MS0156-E-02 - 32 - Bits of Pc value MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 bit stream number, shall be set to “0” Table 9. Fields of burst info Pc
[AK4116] MS0156-E-02 - 35 - PACKAGE 20pin QFN (Unit: mm) 4.20 ± 0.10 4.20 ± 0.10 0.22 ± 0.05 4.00 ± 0.05 4.00 ± 0.05 0.50 0.05 M 0.05 1.00 S AB 1.00 C0.7 0.22 ± 0.05 45.0° 45.0° 3 - 0.69 ± 0.11 0.35 ± 0.11 0.50 B A 3 - C0.2 0.60 ± 0.10 S + 0.03 - 0.05 0.22 S 0.02TYP 0.005MIN 0.04MAX 0.90 ± 0.05 Note: The black parts of back package should be open. Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
[AK4116] MS0156-E-02 - 36 - MARKING 4116 XXXX XXXX : Date code identifier (4 digits) IMPORTANT NOTICE
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