AK4115 AKM | Alldatasheet
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[AK4115] MS0573-E-00 - 1 - GENERAL DESCRIPTION The AK4115 is a 24-bit stereo digital audio transceiver that supports sampling rates up to 216kHz. The channel status bit decoder supports both consumer and professional modes and can automatically detect Non-PCM bit streams such as Dolby Digital or MPEG. The AK4115 supports a wide array of features a couple of them being; differential cable driver and receiver support, and an internal PLL that can support clock sources such as bi-phase and “word clock”. Control of AK4115 is achieved though a µP or pin-strapping (parallel mode) and it is packaged in a space- saving 64pin-LQFP. * Dolby Digital is a trademark of Dolby Laboratories.
FEATURES
AES3, IEC60958, S/PDIF, EIAJ CP1201 Compatible Very Low Jitter Analog PLL Synchronous / Asynchronous Mode Include Two X’tal Oscillators Clock Source: PLL or External Clock - Reference Clock for PLL:
- Biphase signal: 22kHz to 216kHz
- External Clock (ELRCK pin): 22kHz to 216kHz 8-channel Receiver input - One channel supports Differential Input 2-channel Transmission output (Through output or DIT) - One channel supports Differential Output (RS422 Line Output Buffer) Auxiliary Digital Input De-emphasis for 32kHz, 44.1kHz and 48kHz Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection: (22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) - Unlock & Parity Error Detection - DAT Start ID Detection Up to 24bit Audio Data Format Audio Interface: Master or Slave Mode 192-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream Serial µP Interface: 4-wire or I2C (max. 400kHz) Two Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance Package: 64pin LQFP Ta: -20 to 85°C AK4115 High Feature 192kHz 24bit Digital Audio Interface Transceiver
Figure 1. AK4115 Block Diagram in serial mode
Figure 2. AK4115 Block Diagram in parallel mode
[AK4115] MS0573-E-00 - 4 - Ordering Guide AK4115VQ -20 ~ +85 °C 64pin LQFP (0.5mm pitch) AK4115 Evaluation board for AK4115 Pin Layout DIF0/RX5 IPS0/RX4 TEST DIF1/RX6 PDN XSEL/RX7 DVDD VIN DAUX DVSS MCKO1 MCKO2 AVDD RX3 AVDD RX1 AVSS RXP0 RXN0 ACKS EBICK B C U VOUT TX0 TXP1 TXN1 TVSS XTI1 FILT XTL1 XTL0 PSEL IPS1/IIC BVSS DVSS DVDD OCKS0/CSN/CAD0 OCKS1/CCLK/SCL CM1/CDTI/SDA Top View TVDD AVSS RX2 P/SN XTO1 OVDD CM0/CDTO/CAD1 OVSS BICK SDTO LRCK XTI2 XTO2 OVDD OVSS AVDD VCOM R AVSS INT1 INT0 ELRCK EMCK
[AK4115] MS0573-E-00 - 5 - PIN/FUNCTION No. Pin Name I/O Function DIF0 I Audio Data Interface Format #0 Pin in parallel mode RX5 I Receiver Channel #5 Pin in serial mode (Internal biased pin) TEST I TEST Pin This pin must be connected to AVSS. DIF1 I Audio Data Interface Format #1 Pin in parallel mode RX6 I Receiver Channel #6 Pin in serial mode (Internal biased pin) PDN I Power-Down Mode Pin When “L”, the AK4115 is powered-down and reset. XSEL I X’tal Oscillator Selection Pin in parallel mode “L”: X’tal #1 is powered-up. “H”: X’tal #2 is powered-up. XSEL pin and XSEL bit are ORed. RX7 I Receiver Channel #7 Pin in serial mode (Internal biased pin) DVDD Digital Power Supply Pin, 3.3V VIN I V-bit Input Pin for Transmitter Output DAUX I Auxiliary Audio Data Input Pin DVSS Digital Ground Pin MCKO1 O Master Clock Output #1 Pin MCKO2 O Master Clock Output #2 Pin OVDD Digital Power Supply Pin, 3.3V OVSS Digital Ground Pin BICK I/O Audio Serial Data Clock Pin SDTO O Audio Serial Data Output Pin LRCK I/O Channel Clock Pin B I/O Block-Start Input/Output Pin C I/O C-bit Input/Output Pin U I/O U-bit Input/Output Pin VOUT O V-bit Output Pin for Receiver TVDD Input tolerance & TX Output Buffer Power Supply Pin, 3.3V or 5V TX0 O Transmit Channel (Through Data) Output #0 Pin TXP1 O Transmit Channel Positive Output #1 Pin TXN1 O Transmit Channel Negative Output #1 Pin TVSS Input & TX Output Buffer Ground pin XTI1 I X’tal #1 Input Pin XTO1 O X’tal #1 Output Pin XTI2 I X’tal #2 Input Pin XTO2 O X’tal #2 Output Pin OVDD Digital Power Supply Pin, 3.3V OVSS Digital Ground Pin EBICK I/O External Serial Data Clock Pin EMCK I External Master Clock Input Pin ELRCK I/O External Channel Clock Pin INT0 O Interrupt #0 Pin INT1 O Interrupt #1 Pin Note 1. Do not allow digital input pins except internal biased pins to float.
[AK4115] MS0573-E-00 - 6 - PIN/FUNCTION (Continued) No. Pin Name I/O Function CM0 I Master Clock Operation Mode #0 Pin in parallel mode CDTO O Control Data Output Pin in serial mode, IIC pin = “L”. CAD1 I Chip Address #1 Pin in serial mode, IIC pin = “H”. CM1 I Master Clock Operation Mode #1 Pin in parallel mode CDTI I Control Data Input Pin in serial mode, IIC pin = “L”. SDA I/O Control Data Pin in serial mode, IIC pin = “H”. An external pull-up resistor is required. OCKS1 I Output Clock Select #1 Pin in parallel mode CCLK I Control Data Clock Pin in serial mode, IIC pin = “L” SCL I Control Data Clock Pin in serial mode, IIC pin = “H” An external pull-up resistor is required. OCKS0 I Output Clock Select #0 Pin in parallel mode CSN I Chip Select Pin in serial mode, IIC pin = “L”. CAD0 I Chip Address #0 Pin in serial mode, IIC pin = “H”. DVDD Digital Power Supply Pin, 3.3V DVSS Digital Ground Pin BVSS Substrate Ground Pin IPS1 I Input Channel Select #1 Pin in parallel mode IIC I IIC Select Pin in serial mode “L”: 4-wire Serial, “H”: I2C PSEL I PLL Source Select Pin “L”: S/PDIF Input, “H”: ELRCK Input Clock PSEL pin and PSEL bit are ORed in serial mode. XTL0 I X’tal Frequency Select #0 Pin XTL1 I X’tal Frequency Select #1 Pin FILT O PLL Loop Filter Pin AVSS Analog Ground Pin R O External Resistor Pin 10kΩ ±1% resistor should be connected to AVSS externally. VCOM O Common Voltage Output Pin 4.7µF capacitor should be connected to AVSS externally. AVDD Analog Power Supply Pin, 3.3V P/SN I Parallel/Serial Select Pin “L”: Serial Mode, “H”: Parallel Mode ACKS I Master Clock Frequency Auto Setting Mode Pin. “L”: Disable, “H”: Enable ACKS pin and ACKS bit are ORed in serial mode. RXN0 I Receiver Channel #0 Negative Input Pin (Internal biased pin) In serial mode, this channel is selected as default channel. RXP0 I Receiver Channel #0 Positive Input Pin (Internal biased pin) In serial mode, this channel is selected as default channel. AVSS Analog Ground Pin RX1 I Receiver Channel #1 Pin (Internal biased pin) AVDD Analog Power Supply Pin, 3.3V RX2 I Receiver Channel #2 Pin (Internal biased pin) AVSS Analog Ground Pin RX3 I Receiver Channel #3 Pin (Internal biased pin) AVDD Analog Power Supply Pin, 3.3V IPS0 I Input Channel Select #0 Pin in parallel mode RX4 I Receiver Channel #4 Pin in serial mode (Internal biased pin) Note 1. Do not allow digital input pins except internal biased pins to float.
[AK4115] MS0573-E-00 - 7 - Handling of Unused Pin The unused I/O pin should be processed appropriately as below. 1. Serial Mode (P/SN pin = “L”) Classification Pin Name Setting Analog Input RXP0, RXN0, RX7-1 These pins should be open. TEST This pin should be connected to AVSS. Analog Output FILT This pin should be open. Digital Input VIN, DAUX, XTI1, XTI2, EMCK These pin should be connected to DVSS. Digital Output MCKO1, MCKO2, VOUT, TX0, TXP1, TXN1, XTO1, XTO2, INT0, INT1, CDTO These pins should be open. Digital Input/Output B, U, C These pins should be open when BCU_IC bit is “1”. These pins should be DVSS when BCU_IO bit is “0”. EBICK, ELRCK These pins should be open in master mode. These pins should be connected to DVSS in slave mode. 2. Parallel Mode (P/SN pin = “H”) Classification Pin Name Setting Analog Input RXP0, RXN0, RX3-1 These pins should be open. TEST This pin should be connected to AVSS. Analog Output FILT This pin should be open. Digital Input VIN, DAUX, XTI1, XTI2, EMCK, EBICK, ELRCK These pin should be connected to DVSS. Digital Output MCKO1, MCKO2, VOUT, TX0, TXP1, TXN1, XTO1, XTO2, INT0, INT1, CDTO, B, U, C These pins should be open.
[AK4115] MS0573-E-00 - 8 - ABSOLUTE MAXIMUM RATINGS (AVSS, OVSS, DVSS, TVSS, BVSS=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog Digital Logic Output Buffer Input tolerance and TX Buffer AVDD DVDD OVDD TVDD -0.3 -0.3 -0.3 -0.3 4.6 4.6 4.6 6.0 V V V V | BVSS – AVSS | (Note 3) ∆GND1 0.3 V | BVSS – OVSS | (Note 3) ∆GND2 0.3 V | BVSS – DVSS | (Note 3) ∆GND3 0.3 V | BVSS – TVSS | (Note 3) ∆GND4 0.3 V Input Current (Any pins except supplies) IIN ±10 mA Input Voltage (Note 4) VIN -0.3 “TVDD+0.3” or 6.0 V Ambient Temperature (Power applied) Ta -20 Storage Temperature Tstg -65 150 Note 2. All voltages with respect to ground. Note 3. AVSS, OVSS, DVSS, BVSS and TVSS must be connected to the same ground plane. Pull-up resistor at SDA and SCL pins should be connected to (TVDD+0.3)V or less voltage. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, OVSS, DVSS, TVSS, BVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: (Note 5) Analog Digital Logic Output Buffer Input tolerance and TX Buffer AVDD DVDD OVDD TVDD 2.7 2.7 2.7 DVDD 3.3 3.3 3.3 5.0 3.6 3.6 3.6 5.5 V V V V Difference AVDD – DVDD AVDD – OVDD OVDD – DVDD -0.3 -0.3 -0.3 0.3 0.3 0.3 V V V Note 2. All voltages with respect to ground. Note 5. The power up sequence among AVDD, DVDD, OVDD and TVDD is not critical. *AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
[AK4115] MS0573-E-00 - 9 - S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol min typ max Units Input Resistance Zin kΩ Input Voltage VTH 200 mVpp Input Sample Frequency fs 216 kHz Time deviation Jitter RX input (PSEL = “0”) ELRCK input (PSEL = “1”) 100 300 ps RMS ps RMS Cycle - to - Cycle Jitter RX input (PSEL = “0”) ELRCK input (PSEL = “1”) ps RMS ps RMS DC CHARACTERISTICS (Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN pin = “H” (Note 6) AVDD+DVDD+OVDD: TVDD: mA mA Power down: PDN pin = “L” (Note 7) AVDD+DVDD+OVDD+TVDD: 100 µA High-Level Input Voltage Low-Level Input Voltage Input Level at AC coupling (Only ELRCK pin) VIH VIL VAC 70%DVDD DVSS-0.3 0.5 TVDD 30%DVDD TVDD V V Vpp Except for TX0, TXN1 and TXP1 pins High-Level Output Voltage (Iout=-400µA) Low-Level Output Voltage (Except SDA pin: Iout=400µA) ( SDA pin: Iout= 3mA) VOH VOL VOL OVDD-0.4 0.4 0.4 V V V TX0 Output Level Output Level (Note 8) VTXO0 0.4 0.5 0.6 V TXN1 and TXP1 pins Professional mode (TVDD= 4.5 ~ 5.5V) Output Impedance (Rp + Rn + R1) (Note 9) RTXPN 110 132 Ω Consumer Mode (TVDD = 2.7 ~ 5.5V) Output Level (Note 10) VTXO1 0.4 0.5 0.6 V Input Leakage Current Iin ± 10 µA Note 6. AVDD, OVDD, DVDD = 3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1=1, OCKS0=1, TX0 output circuit: Figure 23, TX1 output circuit: Figure 25. AVDD=10mA (typ), OVDD+DVDD=18mA (typ) Note 7. RX inputs are open and all digital input pins are held TVDD or DVSS. Note 8. By using Figure 23 or Figure 24. Note 9. Rp: Output impedance of TXP1, Rn: Output impedance of TXN1, R1 = 75Ω. By using Figure 25. Note 10. By using Figure 26
[AK4115] MS0573-E-00 - 10 - SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty fECLK dECLK 11.2896 27.648 MHz MCKO1 Output Frequency Duty fMCK1 dMCK1 2.816 27.648 MHz MCKO2 Output Frequency Duty fMCK2 dMCK2 1.408 27.648 MHz PLL Clock Recover Frequency (RX7-0) fpll 216 kHz LRCK Frequency Duty Cycle (at Slave Mode) Duty Cycle (at Master Mode) fs dLCK dLCK 216 kHz Audio Interface Timing 1 Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 11) BICK “↑” to LRCK Edge (Note 11) LRCK to SDTO (MSB) (3.0V ≤ DVDD,OVDD ≤ 3.6V) BICK “↓” to SDTO (3.0V ≤ DVDD,OVDD ≤ 3.6V) LRCK to SDTO (MSB) (2.7V ≤ DVDD,OVDD < 3.0V) BICK “↓” to SDTO (2.7 V≤ DVDD,OVDD < 3.0V) DAUX Hold Time DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tLRM tBSD tDXH tDXS ns ns ns ns ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO DAUX Hold Time fBCK dBCK tMBLR tBSD tDXH -15 64fs Hz ns ns ns DAUX Setup Time tDXS ns Master Clock Timing 2 EMCK Frequency Duty fECLK2 dECLK2 2.816 27.648 MHz ELRCK PLL Lock Range Frequency Duty fEPLL fs dLCK 216 216 kHz kHz Audio Interface Timing 2 Slave Mode EBICK Period EBICK Pulse Width Low Pulse Width High ELRCK Edge to BICK “↑” (Note 12) EBICK “↑” to ELRCK Edge (Note 12) DAUX Hold Time DAUX Setup Time tEBCK tEBCKL tEBCKH tELRB tEBLR tEDXH tEDXS ns ns ns ns ns ns ns Master Mode EBICK Frequency EBICK Duty EBICK “↓” to ELRCK DAUX Hold Time fEBCK dEBCK tEMBLR tEDXH -15 64fs Hz ns ns DAUX Setup Time tEDXS ns Note 11. BICK rising edge must not occur at the same time as LRCK edge. Note 12. EBICK rising edge must not occur at the same time as ELRCK edge.
[AK4115] MS0573-E-00 - 11 - SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; AVDD, OVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Control Interface Timing (4-wire serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 13) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive load on bus Pulse Width of Spike Noise Suppressed by Input Filter fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 0.3 0.3 400 kHz µs µs µs µs µs µs µs µs µs µs pF ns Reset Timing PDN Pulse Width tPW 150 ns Note 13. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Note 14. I2C is a registered tradmark of Philips Semiconductors.
Figure 3. Clock Timing
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”. the 14-bit sync word and the 16-bit sync word. uses either a clock comparison against the X’tal oscillator from the setting of XTL1-0, or the channel status information. The PLL loses lock when the received sync interval is incorrect. Table 1. Setting of PLL Reference Clock related to the setting of the FAST bit. The lock time in Table 2 does not include the power-up time of VCOM voltage. time of VCOM voltage is max. 15ms (Capacitor value of VCOM pin = 4.7µF). Table 2. PLL Lock Time (fs: Sampling Frequency)
frequency (1fs). The internal PLL generates MCLK, BICK and LRCK from the word clock supplied to the ELRCK pin. synchronized to the bi-phase signal, WSYNC bit should be set to “0”. sampling frequencies that are selected by the ASYNC bit. Frequency multiples are not required in asynchronous mode.
- Synchronous Mode: ASYNC bit = “0”
ELRCK and MCKO1/2, BICK and LRCK are generated by the PLL. The data source of SDTO is always DAUX. Note 16: When the X’tal is not used as clock comparison for fs detection (i.e. XTL1,0= “1,1”), the X’tal is OFF. Table 3. Clock operation for DIT/DIR in synchronous mode
- Asynchronous Mode: ASYNC bit = “1”, PSEL = “0”
ELRCK and EBCIK. The master clock of TX can be selected to either X’tal or EMCK by the MSEL bit (See Table 4). Table 4. Master clock setting for TX in asynchronous mode. Note 22. When X’tal is OFF, the clock source supports EMCK only. Table 5. Clock operation for DIT/DIR in asynchronous mode Figure 16. Clocks for DIT/DIR in asynchronous mode
become “L” (BCU_IO bit = “1”) in an unlocked state of Mode 2. Note 23. Channel status bit for RX can be monitored by both C pin and CR191-0 bits. Note 24. Validity bit for RX can be monitored by both VOUT pin and VRX bit. Note 25. C pin and CT191-0 bits are ORed internally. Note 26. VIN pin and VTX bit are ORed internally. Note 27. When UDIT bit is “1”, the recovered U bits are used for DIT(DIR-DIT loop mode of U bit). Table 6. Block start, Channel Status bit, User bit and Validity bit in serial mode except AES3 mode (N/A: Not available)
Note 28. Channel status bit for RX can be monitored by CR191-0 bits and SDTO pin. Note 29. Channel status bit for RX can be monitored by C pin, CR191-0 bits and SDTO pin. Note 30. User bit for RX can be monitored by U pin and SDTO pin. Note 31. Validity bit for RX can be monitored by VOUT pin, VRX bit and SDTO pin. Note 32. C pin and CT191-0 bits are ORed internally. Note 33. Channel status bit can select either CT191-0 bits or DAUX pin by the setting of CTX bit. Note 34. VIN pin and VTX bit are ORed internally. Note 35. When UDIT bit is “1”, the recovered U bits are used for DIT(DIR-DIT loop mode of U bit). Table 7. Block start, Channel Status bit, User bit and Validity bit in serial mode & AES3 mode Table 8. Block start, Channel Status bit, User bit and Validity bit in parallel mode
[AK4115] MS0573-E-00 - 22 - 1. Channel Status bit 1-1. RX The data recovered from the bi-phase input signal is stored in CR191-0 bits. When the BCU_IO bit = “1”, the channel status bits are available on the C pin according to the block signal timing. The channel status bits are outputted from SDTO pin with audio data in AES3 mode. 1-2. TX The channel status bit can controlled by the CT191-0 bits. When BCU_IO bit is “0”, the channel status bits are also controlled by C pin. CT191-0 bits and the signal on the C pin are ORed internally. The input to C pin is ignored in AES3 mode. When CTX bit is set to “0”, the channel status bits on DAUX pin are outputted with audio data from TX. When CTX bit is set to “1”, the values of CT191-0 bits are outputted with audio data from TX. When the CCRE bit is “1” and AK4115 is in professional mode (bit0 = “1”), the CRC code can be generated according to the professional mode definition in the AES3 standard. When the CCRE bit is “0”, the CRC data is not generated and the data from the CT191-0 bits is passed to the TX directly. In the consumer mode (bit0 = “0”), the CRC code is not generated. In the consumer mode (bit0 = “0”), bits20-23(audio channel) must be controlled by the CT20 bit. When the CT20 bit is “1”, the AK4115 corresponds to “stereo mode”, bits20-23 are set to “1000”(left channel) in sub-frame 1, and is set to “0100”(right channel) in sub-frame 2. When the CT20 bit is “0”, bits20-23 is set to “0000” in both sub-frame 1 and sub-frame 2. All CR191-0 bits are transferred to CT191-0 bits when the CTRAN bit changes from “0” to “1”. The transferred CT191-0 bits are valid after the next block start signal is detected. CTRAN bit goes to “0” after finishing the transfer. Don’t write to the CT191-0 bits when the CTRAN bit = “1”. 2. User bit 2-1. RX When the BCU_IO bit is “1”, the recovered user bit is available on the U pin according to block start timing. The user bits are outputted from SDTO pin with audio data in AES3 mode. 2-2. TX When the BCU_IO bit is “0”, the user bit is sent to the U pin according to block start timing. When BCU_IO bit is “1” and the ASYNC bit is “0”(synchronous mode), the user bit is controlled by the UDIT bit. When the UDIT bit is “0”, user bit is set to “0”. When the UDIT bit is “1”, the recovered U bits are used for DIT( DIR-DIT loop mode of U bit). This mode (UDIT bit = “1”) is enabled when the PLL is locked. The input to U pin is ignored in AES3 mode and the user bits on DAUX pin are outputted with audio data from TX.
mode, the validity bit is available on the VOUT pin according to LRCK timing. The VRX bit is available in both modes. The validity bit is outputted from SDTO pin with audio data in AES3 mode. VIN pin when BCU_IO bit is set to “0”.
- Block Start Signal Timing
In synchronous mode, the block start signal timing depends on LRCK. In asynchronous mode, it depends on ELRCK. The input to B pin is ignored in AES3 mode and the B bit on DAUX is used as the block start timing. Figure 17. B, C, U, V Input/output timings
when sampling frequency is 192kHz. Table 9. Master Clock Output Frequency frequency can be set by the DIV bit. MCKO1 outputs a clock that is selected by the CM1-0 bits and OCKS1-0 bits. Note 36. MCKO2 Clock Source is selected by XSEL bit. Table 10. Select output frequency of MCKO2 XTL1-0 = “11”, this mode is not supported. In X’tal mode, the frequencies of MCKO1/MCKO2 depend upon OCKS1-0. The ACKS pin and ACKS bit are ORed internally. Table 11. Master Clock Frequency Select (Master Clock Auto Setting Mode)
- Clock comparison between the recovered clock and X’tal oscillator
- Sampling frequency information from channel status
status sampling frequency information. The detected frequency is available on the FS3-0 bits. Table 13. Reference X’tal frequency Note 38: In consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits. Note 39. In professional mode, FS3-0 bit indicates “0001” except for frequency shown by Table 14. Table 14. fs Information
default. It can be switched to channel 2 by the CS12 bit in control register. Table 15. PEM in Consumer Mode Table 16. PEM in Professional Mode de-emphasis mode is OFF. When the PEM bit is “0”, the internal de-emphasis filter is always bypassed. Table 17. De-emphasis Auto Control at DEAU bit = “1” (Default) Table 18. De-emphasis Manual Control at DEAU bit = “0”
RSTN bit initializes the register and resets the internal timing. In parallel mode, only the control by PDN pin is enabled. The AK4115 should be reset once by bringing PDN pin = “L” upon power-up. registers are initialized, and clocks are stopped. Reading/Writing to the registers is disabled. are not initialized and the mode settings are maintained. Writing and reading to the registers are enabled. Eight receiver inputs (RX7-0) are available in serial mode and four receiver inputs (RX3-0) are available in parallel mode. Table 19. Recovery Data Select in serial mode Table 20. Recovery Data Select in parallel mode
The AK4115 has two transmitter outputs, TX0 and TX1. TX0 is a loop-through output that is selected from the RX input. loop-through output from TX0 is fixed to RX0. parallel mode, TX1 is fixed to DIT. Table 21. Output Data Select for TX0 Table 22. Output Data Select for TX1
[AK4115] MS0573-E-00 - 34 - Error Handing for RX (PSEL = “0”) The followings nine events the INT0 and INT1 pins to trigger the interrupt condition. When the PLL is OFF (Clock Operation Mode 1), INT0 and INT1 pins go to “L”. 1. UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4115 loses lock when the time between two preambles is not correct or when those preambles are not correct. 2. PAR : Parity error or bi-phase coding error detection “1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle. 3. AUTO : Non-Linear PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits.is available at the AUTO bit. 4. VRX : Validity flag detection “1” when validity flag is detected. Updated every sub-frame cycle. 5. AUDION : Non-audio detection “1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle. 6. STC : Sampling frequency or pre-emphasis information change detection When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame. 7. QINT : U-bit Sync flag “1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode. 8. CINT : Channel status sync flag “1” when received C bit differs from the old one. Updated every block cycle. 9. DAT : DAT Start ID detect “1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is “1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”. When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection.
removed. Table 25 shows the state of each output pins when the INT0/1 pin is “H”. signal between UNLCK and PAR. Table 25. Error Handling in parallel mode (x: Don’t care) events not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared. UNLCK, PAR, AUTO, AUDION and VRX bits in Address=07H indicate the interrupt status events above in real time. Once QINT, CINT and DAT bits go to “1”, it stays “1” until the register is read. Table 26. Error Handling in serial mode (x: Don’t care)
Figure 31. INT0/1 pin timing
Figure 32. Error Handling Sequence Example 1
Figure 33. Error Handling Sequence Example (for Q/CINT)
OFF (Clock Operation Mode 1), the INT0 and INT1 pins go to “L”.
- UNLCK : PLL unlock state detect
“1” when the PLL loses lock. ELRCK is more than 5% after “4 x fs”. ELRCK is less than 2% after “256 x fs”. typically 11kHz in this case. events are removed. Each INT0/1 pins can mask those two events individually. the interrupt event does not affect operation of the INT1-0. Table 27. Error Handling (x: Don’t care)
- LRCK, BICK, SDTO and DAUX
BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to 128fs at fs=48kHz. last 4LSBs are auxiliary data (see Figure 34). Operation Mode 1, 3 and unlock state of Mode 2. Master Mode of Mode4 and 5. In Slave Mode, LRCK and BICK should be synchronized with MCKO1/2. SDTO pin. Mode 8-9 support only synchronous mode (ASYNC bit = “0”). Figure 34. Bit configuration
Table 28. Audio data format in serial mode Table 29. Audio data format in parallel mode
- EMCK, ELRCK, EBICK and DAUX
selects X’tal or EMCK by the MSEL bit. In parallel mode, this function is not supported. Table 30. Audio data format in asynchronous mode In asynchronous mode, the frequecny of EMCK/X’tal selects 128fs, 256fs or 512fs. It is controlled by ECKS1-0 bit. Table 31. EMCK Frequency
[AK4115] MS0573-E-00 - 48 - Register Map Addr Register Name 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN 01H Format & De-em Control AES3 DIF2 DIF1 DIF0 DEAU DEM1 DEM0 ACKS 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 03H Input/ Output Control 1 EFH1 EFH0 UDIT BCU_IO DIT IPS2 IPS1 IPS0 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD1 MPAR1 06H DAT Mask & DTS Detect DIV XMCK FAST DCNT DTS16 DTS14 MDAT1 MDAT0 07H Receiver Status 0 QINT AUTO CINT UNLCK VRX STC AUDION PAR 08H Receiver Status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM 09H Receiver Status 2 QCRC CCRC 0AH Clock Control TX1NE MCK2E MCK1E ASYNC WSYNC XSEL PSEL 0BH TX Control MSEL ECKS1 ECKS0 EDIF1 EDIF0 CTRAN CCRE VTX 0CH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 23H RX Channel Status Byte 23 CR191 CR190 CR189 CR188 CR187 CR186 CR185 CR184 24H TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 3BH TX Channel Status Byte 23 CT191 CT190 CT189 CT188 CT187 CT186 CT185 CT184 3CH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 3DH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 3EH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 3FH Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 40H Q-subcode Address / Control 41H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 42H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 43H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 44H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 45H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 46H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 47H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 48H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 49H Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 4AH Optional Control CTX Notes: When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”. Data must not be written to addresses 4BH through FFH.
[AK4115] MS0573-E-00 - 49 - Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation (Default) PWN: Power Down 0: Power Down 1: Normal Operation (Default) OCKS1-0: Master Clock Frequency Select (See Table 9) CM1-0: Master Clock Operation Mode Select (See Table 3 and Table 5) BCU: Block start & C/U Output Mode when BCU_IO bit is “1” 0: B, C and U pins output “L”. 1: B, C, and U pins output the data recovered from biphase signal. (Default) When BCU_IO bit is “0”, BCU bit is ignored. CS12: Channel Status Select 0: Channel 1 (Default) 1: Channel 2 Selects which channel status is used to derive C-bit buffers, AUDION, PEM, FS3, FS2, FS1, FS0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the Parallel Mode. Format & De-emphasis Control Addr Register Name 01H Format & De-em Control AES3 DIF2 DIF1 DIF0 DEAU DEM1 DEM0 ACKS R/W R/W R/W R/W R/W R/W R/W R/W R/W Default ACKS: Master clock Auto Setting Mode 0: Disable (Default) 1: Enable DEM1-0: 32, 44.1, 48kHz De-emphasis Control (See Table 18) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable (Default) DIF2-0, AES3: Audio Data Format Control (See Table 28)
[AK4115] MS0573-E-00 - 50 - Input/Output Control Addr Register Name 02H Input/ Output Control 0 TX1E OPS12 OPS11 OPS10 TX0E OPS02 OPS01 OPS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default OPS02-00: Output Through Data Select for TX0 pin (See Table 21) TX0E: TX0 Output Enable 0: Disable. TX0 outputs “L”. 1: Enable (Default) OPS12-10: Output Through Data Select for TX1 pin (See Table 22) TX1E: TXP1/TXN1 pins Output Enable 0: Disable. TXP1 pin outputs “L”. TXN1 pin outputs “H”. 1: Enable (Default) Addr Register Name 03H Input/ Output Control 1 EFH1 EFH0 UDIT BCU_IO DIT IPS2 IPS1 IPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default IPS2-0: Input Recovery Data Select (See Table 19) DIT: Through data/Transmit data select for TXP1/N1 pins 0: Through data (RX data). 1: Transmit data (DAUX data). (Default) BCU_IO: Select I/O of B, C and U pins 0: Input 1: Output (Default) UDIT: U bit control for DIT 0: U bit is fixed to “0”. (Default) 1: Recovered U bit is used for DIT (loop mode for U bit) EFH1-0: Interrupt 0 Pin Hold Count Select 00: 512 LRCK 01: 1024 LRCK (Default) 10: 2048 LRCK 11: 4096 LRCK
[AK4115] MS0573-E-00 - 51 - Mask Control for INT0 Addr Register Name 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MVRX0 MSTC0 MAUD0 MPAR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MPAR0: Mask enable for PAR bit 0: Mask disable (Default) 1: Mask enable MAUD0:Mask enable for AUDION bit 0: Mask disable 1: Mask enable (Default) MSTC0: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MVRX0:Mask enable for VRX bit 0: Mask disable 1: Mask enable (Default) MULK0:Mask enable for UNLCK bit 0: Mask disable (Default) 1: Mask enable MCIT0: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT0:Mask enable for AUTO bit 0: Mask disable 1: Mask enable (Default) MQIT0: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT0 pin operation.
[AK4115] MS0573-E-00 - 52 - Mask Control for INT1 Addr Register Name 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MVRX1 MSTC1 MAUD MPAR1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MPAR1: Mask enable for PAR bit 0: Mask disable 1: Mask enable (Default) MAUD1:Mask enable for AUDION bit 0: Mask disable (Default) 1: Mask enable MSTC1: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MVRX1:Mask enable for VRX bit 0: Mask disable 1: Mask enable (Default) MULK1:Mask enable for UNLCK bit 0: Mask disable 1: Mask enable (Default) MCIT1: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT1:Mask enable for AUTO bit 0: Mask disable (Default) 1: Mask enable MQIT1: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT1 pin operation.
[AK4115] MS0573-E-00 - 53 - DAT Mask & DTS Detect Addr Register Name 06H DAT Mask & DTS Detect DIV XMCK FAST DCNT DTS16 DTS14 MDAT1 MDAT0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MDAT0: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) The factor which mask bit is set to “0” affects INT0 pin operation. MDAT1: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) The factor which mask bit is set to “0” affects INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0: Disable 1: Enable (Default) DTS16: DTS-CD 16bit Sync Word Detect 0: Disable 1: Enable (Default) DCNT: DAT Start ID Counter 0: Disable 1: Enable (Default) FAST: Select PLL Lock Time when the biphase signal is recovered. 0: ≤ (20ms + 384/fs) (Default) 1: ≤ (20ms + 1/fs) XMCK: Select output frequency of MCKO2 (See Table 10) 0: Depends on CM1-0 bits and OCKS1-0 bits (Default) 1: Fixed to X’tal Mode DIV: MCKO2 Output Frequency Select at X’tal Mode (See Table 10) 0: Same frequency as X’tal (Default) 1: Half frequency of X’tal
[AK4115] MS0573-E-00 - 54 - Receiver Status 0 Addr Register Name 07H Receiver status 0 QINT AUTO CINT UNLCK VRX STC AUDION PAR R/W RD RD RD RD RD RD RD RD Default PAR: Parity Error or Bi-phase Error Status 0: No Error 1: Error This bit goes to “1”, if a Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0: No detect 1: Detect This bit goes to “1” when either the FS3-0 or PEM bit changes. VRX: Validity of channel status for RX 0: Valid 1: Invalid UNLCK: PLL Lock Status 0: Lock 1: Unlock CINT: Channel Status Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when C-bit stored in register addresses 0CH to 24H changes. AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when Q-subcode stored in register addresses 40H to 49H changes. STC, QINT, CINT and PAR bits are initialized when 07H is read.
[AK4115] MS0573-E-00 - 55 - Receiver Status 1 Addr Register Name 08H Receiver status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM R/W RD RD RD RD RD RD RD RD Default NPCM: Non-PCM Bit Stream Auto Detection 0: No detect 1: Detect DTSCD: DTS-CD Bit Stream Auto Detection 0: No detect 1: Detect DAT: DAT Start ID Detect 0: No detect 1: Detect DAT bit is initialized when 08H is read. PEM: Pre-emphasis Detect 0: OFF 1: ON This bit is made by encoding channel status bits. FS3-0: Sampling Frequency detection (See Table 14) Receiver Status 1 Addr Register Name 09H Receiver status 1 QCRC CCRC R/W RD RD RD RD RD RD RD RD Default CCRC: Cyclic Redundancy Check for Channel Status 0: No error 1: Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit. QCRC: Cyclic Redundancy Check for Q-subcode 0: No error 1: Error
[AK4115] MS0573-E-00 - 56 - Clock Control Addr Register Name 0AH Clock Control TX1NE MCK1E MCK1E ASYNC WSYNC XSEL PSEL R/W R/W RD R/W R/W R/W R/W R/W R/W Default PSEL: Setting of PLL reference clock (See Table 1) XSEL: Setting of X’tal oscillator (See Table 12) WSYNC: Synchronization between the biphase signal and ELRCK 0: Disable (Default) 1: Enable ASYNC: Setting of synchronous / asynchronous mode for DIT/DIR 0: Synchronous mode (Default) 1: Asynchronous mode MCK1E: Setting of MCKO1 output 0: Disable. Output “L”. 1: Enable (Default) MCK2E: Setting of MCKO2 output 0: Disable. Output “L”. 1: Enable (Default) TX1NE: Setting of TXN1 pin. 0: Disable. Output “L”. This mode is useful for consumer. 1: Enable (Default) TX Control Addr Register Name 0BH TX Control MSEL ECKS1 ECKS0 EDIF1 EDIF0 CTRAN CCRE VTX R/W RD RD R/W R/W R/W R/W R/W R/W Default VTX: Setting of Validity bit for TX 0: Valid (Default) 1: Invalid CCRE: CCRC Enable at professional mode 0: CCRC data is not generated. 1: CCRC data is generated in professional mode. In consumer mode, CCRC data is not generated. (Default) CTRAN: Transfer mode of CR191-0 bits 0: Not transfer or finish to transfer (Default) 1: Transfer All CR191-0 bits is transferred to CT191-0 bits when CTRAN bit changes “0” to “1”. The transferred CT191-0 bits are valid after next block start signal is detected. CTRAN bit goes to “0” after finishing the transfer. EDIF1-0: Setting of audio interface mode in asynchronous mode. (See Table 30) ECK1-0: Setting of EMCK input frequency (See Table 31) MSEL: Master clock setting for TX in asynchronous mode (See Table 4)
[AK4115] MS0573-E-00 - 57 - Receiver Channel Status Addr Register Name 0CH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 23H RX Channel Status Byte 23 CR191 CR190 CR189 CR188 CR187 CR186 CR185 CR184 R/W RD Default Not initialized CR191-0: Receiver Channel Status Byte 23-0 Transmitter Channel Status Addr Register Name 24H TX Channel Status Byte 0 CT7 CT6 CT5 CT4 CT3 CT2 CT1 CT0 R/W R/W Default 25H TX Channel Status Byte 1 CT15 CT14 CT13 CT12 CT11 CT10 CT9 CT8 3BH TX Channel Status Byte 23 CT191 CT190 CT189 CT188 CT187 CT186 CT185 CT184 R/W R/W Default CT7-0: Transmitter Channel Status Byte 0 Default: “00000100” CT191-8: Transmitter Channel Status Byte 23-1 Default: “00000000” Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr Register Name 3CH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 3DH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 3EH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 3FH Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1
[AK4115] MS0573-E-00 - 58 - Q-subcode Buffer Addr Register Name 40H Q-subcode Address / Control 41H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 42H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 43H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 44H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 45H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 46H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 47H Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 48H Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 49H Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized Optional Control Addr Register Name 4AH Optional Control CTX R/W RD RD RD RD RD RD R/W RD Default CTX: Setting of channel status information for AES3 mode 0: Channel status information on DAUX is sent from TX (Default) 1: Channel status information in control registers (CTX191-0 bits) is sent from TX.
[AK4115] MS0573-E-00 - 59 - Burst Preambles in non-PCM Bitstreams 16 bits of bitstream 11 12 27 28 29 30 31 preamble Aux. LSB MSB V U C P sub-frame of IEC958 Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 50. Data structure in IEC60958
Contents
Table 32. Burst preamble words MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 bit stream number, shall be set to “0” Table 33. Fields of burst info Pc
Figure 53 shows the example of system connection diagram for 4-wire serial mode.
12 OVDD
13 OVSS
14 BICK
15 SDTO
16 LRCK
Figure 53. Typical Connection Diagram (4-wire serial mode)
- For setting of XTL0 and XTL1, refer the Table 13.
- “C” depends on the crystal.
- AVSS, BVSS, TVSS, OVSS and DVSS must be connected the same ground plane.
the clock jitter performance.
[AK4115] MS0573-E-00 - 62 - PACKAGE 10.0 12.0 ± 0.3 10.0 12.0 ± 0.3 0.22 ± 0.05 64pin LQFP(Unit:mm) 0.10 0.17 ± 0.05 1.40 0.10 ± 0.05 0° ∼ 10° 0.10 M 0.5 ± 0.2 0.5 +0.05 -0.05 1.70MAX Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder (Pb free) plate
[AK4115] MS0573-E-00 - 63 - MARKING AKM AK4115VQ XXXXXXX XXXXXXX: Date code identifier
Revision History
Date (YY/MM/DD) Revision Reason Page
[AK4115] MS0573-E-00 - 64 - IMPORTANT NOTICE
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