AK4113 AKM | Alldatasheet
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[AK4113] MS0349-E-01 - 1 - GENERAL DESCRIPTION The AK4113 is a 24-bit stereo digital audio receiver that supports sampling rates up to 216kHz. The channel status bits decoder supports both consumer and professional modes. The AK4113 automatically detects non-PCM bit streams such as Dolby Digital, MPEG etc. When combined with the multi channel codec (AK4626 or AK4628), the two chips provide a system solution for Dolby Digital applications. Control of AK4113 is achieved though a µP or pin strapping (parallel mode). It is packaged in a space-saving 30-pin VSOP. * Dolby Digital is a trademark of Dolby Laboratories.
FEATURES
AES/EBU, IEC60958, S/PDIF, EIAJ CP1201 Compatible Low Jitter Analog PLL PLL Lock Range: 8k ∼ 216kHz Clock source: PLL or X'tal 6-channel Receiver Input and 1-channel Transmission Output (Through output) Auxiliary Digital Input De-emphasis for 32kHz, 44.1kHz and 48kHz Detection Functions - Non-PCM Bit Stream Detection - DTS-CD Bit Stream Detection - Sampling Frequency Detection (8kHz, 11.025kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz, 64kHz, 88.2kHz, 96kHz, 176.4kHz and 192kHz) - Unlock & Parity Error Detection - Validity Detection - DAT Start ID Detection Up to 24bit Audio Data Format Audio Interface: Master or Slave Mode 40-bit Channel Status Buffer Burst Preamble bit Pc and Pd Buffer for Non-PCM bit stream Q-subcode Buffer for CD bit stream Serial µP Interface: I2C (max. 400kHz) or 4-wire Two Master Clock Outputs: 64fs/128fs/256fs/512fs Operating Voltage: 2.7 to 3.6V with 5V Logic Tolerance Small Package: 30pin VSOP Ta: - 40 ∼ 85°C 192kHz 24bit DIR with 6:1 Selector AK4113
[AK4113] MS0349-E-01 - 3 - Ordering Guide AK4113VF -40 ~ +85 °C 30pin VSOP (0.65mm pitch) AKD4113 Evaluation board for AK4113 PIN Layout DVDD DVSS V/TX TVDD XTI XTO PDN R Top View AVDD AVSS RX1 RX2/DIF0 RX3/DIF1 RX4/DIF2 CM0/CDTO/CAD1 CM1/CDTI/SDA OCKS1/CCLK/SCL OCKS0/CSN/CAD0 MCKO1 MCKO2 DAUX BICK SDTO LRCK INT0 FS96/I2C P/SN INT1 RX5 IPS/RX6
[AK4113] MS0349-E-01 - 4 - PIN/FUNCTION No. Pin Name I/O Function DVDD Digital Power Supply Pin, 3.3V DVSS Digital Ground Pin TVDD Input Buffer Power Supply Pin, 3.3V or 5V V O Validity Flag Output Pin in Parallel control mode TX O Transmit channel (Through data) Output Pin in serial control mode XTI I X'tal Input Pin XTO O X'tal Output Pin PDN I Power-Down Mode Pin When “L”, the AK4113 is powered-down and reset. R External Resistor Pin This pin must be connected to AVSS via 15kΩ ±5% resistor. AVDD Analog Power Supply Pin AVSS Analog Ground Pin RX1 I Receiver Channel #1 Pin (Internal Biased Pin) DIF0 I Audio Data Interface Format #0 Pin in parallel control mode RX2 I Receiver Channel #2 Pin in serial control mode (Internal Biased Pin) DIF1 I Audio Data Interface Format #1 Pin in parallel control mode RX3 I Receiver Channel #3 Pin in serial control mode (Internal Biased Pin) DIF2 I Audio Data Interface Format #2 Pin in parallel control mode RX4 I Receiver Channel #4 Pin in serial control mode (Internal Biased Pin) RX5 I Receiver Channel #5 Pin (Internal Biased Pin) IPS I Input Channel Select Pin in parallel control mode RX6 I Receiver Channel #6 Pin (Internal Biased Pin) Interrupt #1 Pin (when BCU bit = “0”) U-bit Output Pin (when BCU bit = “1”, UCE bit = “0”) INT1 O C-bit Output Pin (when BCU bit = “1”, UCE bit = “1”) P/SN I Parallel/Serial Select Pin “L”: Serial control mode, “H”: Parallel control mode FS96 O 96kHz Sampling Detect Pin in parallel control mode This function is enabled when the input frequency of XTI is 24.576MHz. “L”: fs=54kHz or less, “H”: fs=64kHz or more I2C I I2C Select Pin in Serial control mode. “L”: 4-wire Serial, “H”: I2C INT0 I Interrupt #0 Pin LRCK I/O Output Channel Clock Pin SDTO O Audio Serial Data Output Pin BICK I/O Audio Serial Data Clock Pin DAUX I Auxiliary Audio Data Input Pin Master Clock #2 Output Pin (when BCU bit = “0”) MCKO2 O Block Start Signal Output Pin (when BCU bit = “1”) MCKO1 O Master Clock #1 Output Pin OCKS0 I Output Clock Select #0 Pin in parallel control mode CSN I Chip Select Pin in serial control mode, I2C pin = “L” CAD0 I Chip Address #0 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins expect internal biased pins (RX1-6 pins) to float.
[AK4113] MS0349-E-01 - 5 - No. Pin Name I/O Function OCKS1 I Output Clock Select #1 Pin in parallel control mode CCLK I Control Data Clock Pin in serial control mode, I2C pin = “L” SCL I Control Data Clock Pin in serial control mode, I2C pin = “H” CM1 I Master Clock Operation Mode #1 Pin in parallel control mode CDTI I Control Data Input Pin in serial control mode, I2C pin = “L” SDA I/O Control Data Pin in serial control mode, I2C pin = “H” CM0 I Master Clock Operation Mode #0 Pin in parallel control mode CDTO O Control Data Output Pin in serial control mode CAD1 I Chip Address #1 Pin in serial control mode, I2C pin = “H” Note 1. Do not allow digital input pins expect internal biased pins (RX1-6 pins) to float. Handling of Unused Pin The unused I/O pin should be processed appropriately as below. Classification Pin Name Setting RX1, RX2/DIF0, RX3/DIF1, RX4/DIF2, RX5, RX6/IPS These pins should be open in serial control mode. Analog Input RX1, RX5 These pins should be open in parallel control mode. Digital Input DAUX, XTI These pins should be connected to DVSS. V/TX, XTO, INT0, INT1, MCKO1, MCKO2 These pins should be open. I2C/FS96 This pin should be open in parallel control mode. Digital Output CAD1/CDTO/CM0 This pin should be open in serial control mode and 4-wire mode (I2C pin = “L”).
[AK4113] MS0349-E-01 - 6 - Compare AK4112B with AK4113 1. Function Function AK4112B AK4113 Serial control mode 4ch 6ch RX Input Channel Parallel control mode 1ch 2ch PLL Lock Range 22kHz to 108kHz 8kHz to 216kHz Resistor value for R pin 18k ± 1% 15k ± 5% PLL Lock Time ≤ 20ms FAST bit =“0”: ≤ (15ms+384/fs) FAST bit =“1”: ≤ (15ms+1/fs) DTS-CD Bit Stream Detection Not available Available DAT Start ID Detection Not available Available Q-subcode Buffer for CD bit Stream Not available Available fs Detection in serial control mode ≤ 54kHz ≥or ≥88.2kHz 8k / 11.025k / 16k / 22.05k / 24k/ 32k / 44.1k / 48k / 64k / 88.2k / 96k / 176.4k / 192kHz Serial µP Interface 4-wire 4-wire/I2C (max.400kHz) Error Handling Pins AUTO, ERF, FS96 INT0, INT1 Master Clock Output Frequency 128fs/256fs/512fs 64fs/128fs/256fs/512fs Channel Status Bit 32bit 40bit MCKO2 Clock Source in serial control mode Depend on CM1-0 bits Depend on CM1-0, XMCK and BCU bits Audio I/F at Reset in serial control mode Master Mode Slave Mode Package 28pin VSOP 30pin VSOP
[AK4113] MS0349-E-01 - 7 - 2. Pin Layout Note: 1) Light gray highlights indicate the difference between AK4112B and AK4113. 2) The inside of “( )” indicates the pin name of AK4112B. 3. Control register Control registers of between AK4112B and AK4113 are not compatible. DVDD DVSS V/TX TVDD XTI XTO PDN R Top View AVDD AVSS RX1 RX2/DIF0 RX3/DIF1 RX4/DIF2 CM0/CDTO/CAD1 CM1/CDTI/SDA OCKS1/CCLK/SCL OCKS0/CSN/CAD0 MCKO1 MCKO2 DAUX BICK SDTO LRCK INT0 (ERF) FS96/I2C (FS96) P/SN INT1 (AUTO) (None) RX5 IPS/RX6 (None) AK4112B AK4113
[AK4113] MS0349-E-01 - 8 - ABSOLUTE MAXIMUM RATING (AVSS, DVSS=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog Digital Input Buffer |AVSS-DVSS| (Note 3) AVDD DVDD TVDD ∆GND -0.3 -0.3 -0.3 4.6 4.6 6.0 0.3 V V V V Input Current (Any pins except supplies) IIN ±10 mA Input Voltage VIN -0.3 TVDD+0.3 V Ambient Temperature (Power applied) Ta -40 Storage Temperature Tstg -65 150 Note 2. All voltage with respect to ground. Note 3. AVSS and DVSS must be connected to the same ground. WARING: Operation at or beyond these limits may result in permanent damage to the device Normal operation is not guaranteed at these extremes. RECOMMEND OPERATIONG CONDITIONS (AVSS, DVSS=0V; Note 2) Parameter Symbol min typ max Units Power Supplies: Analog Digital Input Buffer Difference AVDD DVDD TVDD AVDD - DVDD 2.7 2.7 DVDD -0.3 3.3 3.3 3.3 3.6 3.6 5.5 0.3 V V V V Note 2. All voltage with respect to ground S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol min typ max Units Input Resistance Zin kΩ Input Voltage VTH 350 mVpp Input Hysteresis VHY 185 mV Input Sample Frequency fs 216 kHz
[AK4113] MS0349-E-01 - 9 - DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation: PDN pin = “H” (Note 4) Power down: PDN pin = “L” (Note 5) 100 mA µA High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD DVSS - 0.3 TVDD 30%DVDD V V High-Level Output Voltage (Except TX pin: Iout=-400µA) Low-Level Output Voltage (Except TX and SDA pins: Iout=400µA) ( SDA pin: Iout= 3mA) VOH VOL VOL DVDD-0.4 0.4 0.4 V V V TX Output Level (Note 6) VTXO 0.4 0.5 0.6 V Input Leakage Current (Except RX1-6, XTI pins) Iin ± 10 µA Note 4. AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=216kHz, X'tal=24.576MHz, Clock Operation Mode 2, OCKS1 bit = “1”, OCKS0 bit = “1”. TX circuit = Figure 19, Master Mode; AVDD=5mA (typ), DVDD=21mA (typ), TVDD=0.1µA (typ). Note 5. RX inputs are open and all digital input pins are held DVDD or DVSS. Note 6. By using Figure 19 SWITCHING CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty fECLK dECLK 11.2896 24.576 MHz MCKO1 Output Frequency Duty fMCK1 dMCK1 1.024 27.648 MHz MCKO2 Output Frequency Duty fMCK2 dMCK2 0.512 27.648 MHz PLL Clock Recover Frequency (RX1-6) fpll 216 kHz LRCK Frequency Duty Cycle fs dLCK 216 kHz Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 7) BICK “↑” to LRCK Edge (Note 7) LRCK to SDTO (MSB) BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tDXH tDXS ns ns ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “↓” to LRCK BICK “↓” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -15 64fs Hz ns ns ns ns Note 7. BICK rising edge must not occur at the same time as LRCK edge.
[AK4113] MS0349-E-01 - 10 - SWITCHING CHARACTERISTICS (Continued) (Ta=25°C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Control Interface Timing (4-wire serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Control Interface Timing (I2C Bus mode): SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low Time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 8) SDA Setup Time from SCL Rising Rise Time of Both SDA and SCL Lines Fall Time of Both SDA and SCL Lines Setup Time for Stop Condition Capacitive load on bus Pulse Width of Spike Noise Suppressed by Input Filter fSCL tBUF tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO Cb tSP 1.3 0.6 1.3 0.6 0.6 0.1 0.6 400 0.3 0.3 400 kHz µs µs µs µs µs µs µs µs µs µs pF ns Reset Timing PDN Pulse Width tPW 150 ns Note 8. Data must be held for sufficient time to bridge the 300ns transition time of SCL. Note 9. I2C is a registered tradmark of Philips Semiconductors. Purchase of Asahi Kasei Microsystems Co., Ltd I2C components conveys a license under the Philips I2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips.
consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the NPCM bit to “1”. detects both the 14-bit sync word and the 16-bit sync word. lock when the received sync interval is incorrect. Figure 12. PLL Lock Time (fs: Sampling Frequency)
frequency of X’tal is different from the recovered frequency from PLL. Note: When the X’tal is not used as clock comparison for fs detection (i.e. XTL1-0 bit = “11”), the X’tal is OFF. Table 1. Clock Operation Mode Select operate when the sampling frequency is 192kHz. Table 2. Master Clock Output Frequency the CM1-0 bits and OCKS1-0 bits. Table 3. Select output frequency of MCKO2
The AK4113 has two methods for detecting the sampling frequency.
- Clock comparison between the recovered clock and X’tal oscillator
- Sampling frequency information on channel status
The method is selected by the XTL1-0 bits. The detected frequency is available on the FS3-0 bits. detected frequency is available on the FS3-0 bits. In parallel control mode, XTL1-0 bits are fixed to “10”. Table 4. Reference X’tal frequency than 8kHz, FS3-0 bits may indicate “0001” or “1101”. Note 11. In consumer mode, Byte3 Bit3-0 are copied to FS3-0 bits. Note 12. In professional mode, FS3-0 bit indicates “0001” except for frequency shown by Table 5. Table 5. fs Information
default. It can be switched to channel 2 by the CS12 bit in control register. Table 6. PEM in Consumer Mode Table 7. PEM in Consumer Mode de-emphasis filter is bypassed and the recovered data is available without any change if the de-emphasis mode is OFF. When the PEM bit is “0”, the internal de-emphasis filter is always bypassed. Table 8. De-emphasis Auto Control at DEAU bit = “1” (Default) Table 9. De-emphasis Manual Control at DEAU bit = “0”
[AK4113] MS0349-E-01 - 20 - System Reset and Power-Down The AK4113 has a power-down mode for all circuits using the PDN pin or it can be partially powerd-down with the PWN bit. The RSTN bit initializes the register and resets the internal timing. In parallel control mode, only control by the PDN pin is enabled. The AK4113 should be reset once by bringing PDN pin = “L” upon power-up. PDN Pin: All analog and digital circuits are placed in power-down and reset mode by bringing PDN pin = “L”. All the registers are initialized, and clocks are stopped. Reading/Witting to the registers are disabled. RSTN Bit (Address 00H; D0): All the registers except PWN and RSTN bits are initialized by bringing RSTN bit = “0”. The internal timings is also initialized. Writing to registers is not available except the PWN and RSTN bits. Reading from the registers is disabled. PWN Bit (Address 00H; D1): The clock recovery is initialized by bringing PWN bit = “0”. In this case, the clocks are stopped. The registers are not initialized and the mode settings are maintained. Writing and reading to the registers are enabled.
Table 10. Recovery Data Select at serial control mode Table 11. Recovery Data Select at parallel control mode Table 12. B, C, U output pins select
- The block signal goes high at the start of frame 0 and remains high until the end of frame 39.
Figure 16. B, C, U, V Output Timing
control mode, the bi-phase loop-through output can not be outputted. Table 13. Output Data Select
[AK4113] MS0349-E-01 - 25 - Error Handing The following nine events cause the INT0 and INT1 pins to show the status of the interrupt condition. When the PLL is OFF (Clock Operation Mode 1), INT0 and INT1 pins go to “L”. 1. UNLCK : PLL unlock state detect “1” when the PLL loses lock. The AK4113 loses lock when the distance between two preamble is not correct or when those preambles are not correct. 2. PAR : Parity error or bi-phase coding error detection “1” when parity error or bi-phase coding error is detected, updated every sub-frame cycle. 3. AUTO : Non-Linear PCM or DTS-CD Bit Stream detection The OR function of NPCM and DTSCD bits is available at the AUTO bit. 4. V : Validity flag detection “1” when validity flag is detected. Updated every sub-frame cycle. 5. AUDION : Non-audio detection “1” when the “AUDION” bit in recovered channel status indicates “1”. Updated every block cycle. 6. STC : Sampling frequency or pre-emphasis information change detection When either FS3-0 bit or PEM bit is changed, it maintains “1” during 1 sub-frame. 7. QINT : U-bit Sync flag “1” when the Q-subcode differs from the old one. Updated every sync code cycle for Q-subcode. 8. CINT : Channel status sync flag “1” when received C bit differs from the old one. Updated every block cycle. 9. DAT : DAT Start ID detect “1” when the category code indicates “DAT” and “DAT Start ID” is detected. When DCNT bit is “1”, it does not indicate “1” even if “DAT Start ID” is detected again within “3841 x LRCK”. When “DAT Start ID” is detected again after “3840 x LRCK” passed, it indicates “1”. When DCNT bit is “0”, it indicates “1” every “DAT Start ID” detection.
events are removed. Table 14 shows the state of each output pins when the INT0/1 pin is “H”. Note 13. INT1 pin outputs “L” or “H” in accordance with the ORed signal between AUTO and AUDION. Note 14. INT0 pin outputs “L” or “H” in accordance with the ORed signal between UNLCK and PAR. Note 16. V pin outputs “L” or “Normal operation” in accordance with the ORed signal between PAR and UNCLK. Table 14. Error Handling in parallel control mode (x: Don’t care) QINT, CINT and DAT bits goes to “1”, it stays “1” until the register is read. Table 15. Error Handling in serial control mode (x: Don’t care)
Figure 23. INT0/1 pin Timing
Figure 24. Error Handling Sequence Example 1
Figure 25. Error Handling Sequence Example (for Q/CINT)
Master Mode of Mode 4 and 5. In Slave mode, LRCK and BICK should be synchronized with MCKO1/2. Figure 26. Bit configuration Table 16. Audio Data Format Note 17. This frequency must not exceed a maximum BICK frequency that is defined in “Switching Characteristics”.
- 4-wire serial control mode (I2C pin = “L”)
of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the registers to their default values. Figure 31. 4-wire Serial Control I/F Timing
[AK4113] MS0349-E-01 - 37 - Register Map Addr Register Name 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN 01H Format & De-em Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 02H Input/ Output Control 0 XTL1 XTL0 UCE TXE OPS2 OPS1 OPS0 03H Input/ Output Control 1 EFH1 EFH0 FAST XMCK DIV IPS2 IPS1 IPS0 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD1 MPAR1 06H DAT Mask & DTS Detect DCNT DTS16 DTS14 MDAT1 MDAT0 07H Receiver status 0 QINT AUTO CINT UNLCK V STC AUDION PAR 08H Receiver status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM 09H Receiver status 2 QCRC CCRC 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 13H Q-subcode Address/Control 14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 Note: When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”. For addresses from 1DH to 1FH, data must not write.
[AK4113] MS0349-E-01 - 38 - Register Definitions Reset & Initialize Addr Register Name 00H CLK & Power Down Control CS12 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN R/W R/W R/W R/W R/W R/W R/W R/W R/W Default RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation (Default) PWN: Power Down 0: Power Down 1: Normal Operation (Default) OCKS1-0: Master Clock Frequency Select (See Table 2) CM1-0: Master Clock Operation Mode Select (See Table 1) BCU: Block start (B) , C, U Output Mode (See Table 12) 0: Disable (Default) 1: Enable CS12: Channel Status Select 0: Channel 1 (Default) 1: Channel 2 Select which channel status is used to derive C-bit buffer, AUDION, PEM, FS3-0, Pc and Pd. The de-emphasis filter is controlled by channel 1 in the parallel control mode. Format & De-emphasis Control Addr Register Name 01H Format & De-em Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 R/W R/W R/W R/W R/W R/W R/W R/W RD Default DEM1-0: 32, 44.1, 48kHz De-emphasis Control (See Table 9) DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable (Default) DIF2-0: Audio Data Format Control (See Table 16; Default: “110”) V/TX: V/TX Output Select 0: Validity Flag Output. (Default) This output is updated every fs cycle. 1: TX
[AK4113] MS0349-E-01 - 39 - Input/Output Control Addr Register Name 02H Input/ Output Control 0 XTL1 XTL0 UCE TXE OPS2 OPS1 OPS0 R/W RD R/W R/W R/W R/W R/W R/W R/W Default OPS2-0: Output Through Data Select for TX pin (See Table 13; Default: “000”) TXE: TX pin Output Enable 0: Disable. TX pin outputs “L”. 1: Enable (Default) UCE: C-bit, U-bit output setting (See Table 12, Default: “0”) XTL1-0: Reference X’tal frequency Select (See Table 4, Default: 00) Addr Register Name 03H Input/ Output Control 1 EFH1 EFH0 FAST XMCK DIV IPS2 IPS1 IPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default IPS2-0: Input Recovery Data Select (See Table 10; Default: “000”) DIV: MCKO2 Output Frequency Select at X’tal Mode (See Table 3) 0: x 1 (Default) 1: x 1/2 XMCK: MCKO2 pit output select (See Table 3) 0: Depends on CM1-0 bits and OCKS1-0 bits (Default) 1: Fixed to X’tal Mode FAST: PLL Lock Time Select 0: ≤ (15ms + 384/fs) (Default) 1: ≤ (15ms + 1/fs) EFH1-0: INT0 pin Hold Time Select 00: 512/fs 01: 1024/fs (Default) 10: 2048/fs 11: 4096/fs
[AK4113] MS0349-E-01 - 40 - Mask Control for INT0 Addr Register Name 04H INT0 MASK MQIT0 MAUT0 MCIT0 MULK0 MV0 MSTC0 MAUD0 MPAR0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MPAR0: Mask enable for PAR bit 0: Mask disable (Default) 1: Mask enable MAUD0:Mask enable for AUDION bit 0: Mask disable 1: Mask enable (Default) MSTC0: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV0: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK0:Mask enable for UNLCK bit 0: Mask disable (Default) 1: Mask enable MCIT0: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT0: Mask enable for AUTO bit 0: Mask disable 1: Mask enable (Default) MQIT0: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT0 pin operation.
[AK4113] MS0349-E-01 - 41 - Mask Control for INT1 Addr Register Name 05H INT1 MASK MQIT1 MAUT1 MCIT1 MULK1 MV1 MSTC1 MAUD MPAR1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default MPAR1: Mask enable for PAR bit 0: Mask disable 1: Mask enable (Default) MAUD1: Mask enable for AUDION bit 0: Mask disable (Default) 1: Mask enable MSTC1: Mask enable for STC bit 0: Mask disable 1: Mask enable (Default) MV1: Mask enable for V bit 0: Mask disable 1: Mask enable (Default) MULK1: Mask enable for UNLCK bit 0: Mask disable 1: Mask enable (Default) MCIT1: Mask enable for CINT bit 0: Mask disable 1: Mask enable (Default) MAUT1: Mask enable for AUTO bit 0: Mask disable (Default) 1: Mask enable MQIT1: Mask enable for QINT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, corresponding event does not affect INT1 pin operation. DAT Mask & DTS Detect Addr Register Name 06H DAT Mask & DTS Detect DCNT DTS16 DTS14 MDAT1 MDAT0 R/W RD RD RD R/W R/W R/W R/W R/W Default MDAT0: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, DAT event does not affect INT0 pin operation. MDAT1: Mask enable for DAT bit 0: Mask disable 1: Mask enable (Default) When mask is set to “1”, DAT event does not affect INT1 pin operation. DTS14: DTS-CD 14bit Sync Word Detect 0: Disable 1: Enable (Default) DTS16: DTS-CD 16bit Sync Word Detect 0: Disable 1: Enable (Default) DCNT: DAT Start ID Counter 0: Disable 1: Enable (Default)
[AK4113] MS0349-E-01 - 42 - Receiver Status 0 Addr Register Name 07H Receiver status 0 QINT AUTO CINT UNLCK V STC AUDION PAR R/W RD RD RD RD RD RD RD RD Default PAR: Parity Error or Bi-phase Error Status 0: No Error 1: Error This bit goes to “1”, if a Parity Error or Biphase Error is detected in the sub-frame. AUDION: Audio Bit Output 0: Audio 1: Non Audio This bit is made by encoding channel status bits. STC: Sampling Frequency or Pre-emphasis Information Change Detection 0: No detect 1: Detect This bit goes to “1” when either the FS3-0 or PEM bit changes. V: Validity of channel status 0: Valid 1: Invalid UNLCK: PLL Lock Status 0: Lock 1: Unlock CINT: Channel Status Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when C-bit stored in register addresses 0AH to 0EH changes. AUTO: Non-PCM Auto Detect 0: No detect 1: Detect QINT: Q-subcode Buffer Interrupt 0: No change 1: Changed This bit goes to “1” when Q-subcode stored in register addresses 13H to 1CH changes. STC, QINT, CINT and PAR bits are initialized when 07H is read.
[AK4113] MS0349-E-01 - 43 - Receiver Status 1 Addr Register Name 08H Receiver status 1 FS3 FS2 FS1 FS0 PEM DAT DTSCD NPCM R/W RD RD RD RD RD RD RD RD Default NPCM: Non-PCM Bit Stream Auto Detection 0: No detect 1: Detect DTSCD: DTS-CD Bit Stream Auto Detection 0: No detect 1: Detect DAT: DAT Start ID Detect 0: No detect 1: Detect DAT bit is initialized when 08H is read. PEM: Pre-emphasis Detect 0: OFF 1: ON This bit is made by encoding channel status bits. FS3-0: Sampling Frequency detection (See Table 5) Receiver Status 1 Addr Register Name 09H Receiver status 1 QCRC CCRC R/W RD RD RD RD RD RD RD RD Default CCRC: Cyclic Redundancy Check for Channel Status 0: No error 1: Error This bit is enabled only in professional mode and only for the channel selected by the CS12 bit. QCRC: Cyclic Redundancy Check for Q-subcode 0: No error 1: Error
[AK4113] MS0349-E-01 - 44 - Receiver Channel Status Addr Register Name 0AH RX Channel Status Byte 0 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 0BH RX Channel Status Byte 1 CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8 0CH RX Channel Status Byte 2 CR23 CR22 CR21 CR20 CR19 CR18 CR17 CR16 0DH RX Channel Status Byte 3 CR31 CR30 CR29 CR28 CR27 CR26 CR25 CR24 0EH RX Channel Status Byte 4 CR39 CR38 CR37 CR36 CR35 CR34 CR33 CR32 R/W RD Default Not initialized CR39-0: Receiver Channel Status Byte 4-0 All 40 bits are updated at the same time every bock (192 frames) cycle. Burst Preamble Pc/Pd in non-PCM encoded Audio Bitstreams Addr Register Name 0FH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 10H Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 11H Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 12H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD Default Not initialized PC15-0: Burst Preamble Pc Byte 0 and 1 PD15-0: Burst Preamble Pd Byte 0 and 1 Q-subcode Buffer Addr Register Name 13H Q-subcode Address / Control 14H Q-subcode Track Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 15H Q-subcode Index Q25 Q24 Q23 Q22 Q21 Q20 Q19 Q18 16H Q-subcode Minute Q33 Q32 Q31 Q30 Q29 Q28 Q27 Q26 17H Q-subcode Second Q41 Q40 Q39 Q38 Q37 Q36 Q35 Q34 18H Q-subcode Frame Q49 Q48 Q47 Q46 Q45 Q44 Q43 Q42 19H Q-subcode Zero Q57 Q56 Q55 Q54 Q53 Q52 Q51 Q50 1AH Q-subcode ABS Minute Q65 Q64 Q63 Q62 Q61 Q60 Q59 Q58 1BH Q-subcode ABS Second Q73 Q72 Q71 Q70 Q69 Q68 Q67 Q66 1CH Q-subcode ABS Frame Q81 Q80 Q79 Q78 Q77 Q76 Q75 Q74 R/W RD Default Not initialized Q2-81: Q-subcode (Figure 20 and Figure 21 ) All 80 bits are updated at the same time every sync code cycle for Q-subcode.
[AK4113] MS0349-E-01 - 45 - Burst Preambles in non-PCM Bitstreams 16 bits of bitstream 11 12 27 28 29 30 31 preamble Aux. LSB MSB V U C P sub-frame of IEC60958 Pa Pb Pc Pd Burst_payload stuffing repetition time of the burst Figure 41. Data structure in IEC60958
Contents
Table 17. Burst preamble words MPEG-1 Layer2 or 3 data or MPEG-2 without extension MPEG-2 data with extension MPEG-2 AAC ADTS MPEG-2, Layer1 Low sample rate MPEG-2, Layer2 or 3 Low sample rate reserved DTS type I DTS type II DTS type III ATRAC ATRAC2/3 reserved ≤4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 reserved, shall be set to “0” error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 bit stream number, shall be set to “0” Table 18. Fields of burst info Pc
[AK4113] MS0349-E-01 - 48 - PACKAGE Detail A NOTE: Dimension "*" does not include mold flash. 0.22±0.1 0.65 *9.7±0.1 1.5MAX A 30pin VSOP (Unit: mm) 5.6±0.1 7.6±0.2 0.45±0.2 -0.05 +0.10 0.3 0.15 0.12 M 0.08 1.2±0.10 0.10 +0.10 -0.05 Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb Free)
[AK4113] MS0349-E-01 - 49 - MARKING AKM AK4113VF XXXBYYYYC XXXBYYYYC: Date code identifier XXXB: Lot number (X : Digit number, B : Alpha character ) YYYYC: Assembly date (Y : Digit number C : Alpha character)
Revision History
Date (YY/MM/DD) Revision Reason Page 3, 5, 7 Pin Name: #14; RX4/IPS2 Æ RX4/DIF2 IMPORTANT NOTICE
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