AK4112

AK4112A AKM | Alldatasheet

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ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 1 - GENERAL DESCRIPTION The AK4112A is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status decoding supports both consumer and professional modes. The AK4112A can automatically detect a Non-PCM bit stream. When combined with an AK4527 multi channel codec, the two chips provide a system solution for AC-3 applications. The dedicated pins or a serial uP I/F can control the mode setting. The small package, 28pin VSOP saves the board space. *AC-3 is a trademark of Dolby Laboratories.

FEATURES

o Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201 o Low jitter Analog PLL o PLL Lock Range : 22k~108kHz o Clock Source: PLL or X'tal o 4 channel Receivers input and 1 through transmission output o Auxiliary digital input o De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz o Dedicated Detect Pins

• Non-PCM Bit Stream Detect Pin
• Validity Flag Detect Pin
• 96kHz Sampling Detect Pin
• Unlock & Parity Error Detect Pin o Supports up to 24bit Audio Data Format o Audio I/F: Master or Slave Mode o 32bits Channel Status Buffer o Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream o Serial µP I/F o Two Master Clock Outputs:128fs/256fs/512fs o Operating Voltage: 2.7 to 3.6V with 5V tolerance o Small Package: 28pin VSOP o Ta: -40~85°C High Feature 96kHz 24bit DIR AK4112A

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 2 - nnnn Compatibility with AK4110 AK4110 AK4112A Ambient Temperature -20 ~ 85°C -40 ~ 85 °C AVDD, DVDD 3.0 ~ 3.6V 2.7 ~ 3.6V fs 32kHz ~ 96kHz 22kHz ~ 108kHz Crystal resonator (max) 12.288MHz 24.576MHz Clock Operation Mode 3 X O Parallel Control Mode X O TX output X O 512fs output X O 384fs output O X Burst Preamble Pc, Pd buffers X O (0DH ~ 10H) FS96 output select in X’tal Mode X O (11H D0; XFS96) ERF hold time fixed (1028/fs) selectable (512, 1024, 2048, 4096/fs) (11H D2, D1; ERH1, ERH0) Input data format of DAUX Mode5 and 7 not available I 2S Pin #7 R PDN Pin #8 DAUX R Pin #22 PDN DAUX Resistor on R pin 9.1kW 18kW Capacitor on R pin No need No need (£100pF) O: Available, X: Not available

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 3 - Input Selector System Control Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect Error Detect DEM µp I/F Audio I/F 96kHz Detect X'tal Oscillator RX1 RX2 RX3 RX4 V/TX DVDD DVSS PDN AUTO ERF P/S="L" TVDD LRCK BICK SDTO DAUX FS96 XTOXTIMCKO2MCKO1RAVDDAVSS CDTI CDTO CCLK CSN Serial Control Mode System Control Clock Recovery Clock Generator DAIF Decoder AC-3/MPEG Detect Error Detect DEM Audio I/F 96kHz Detect X'tal OscillatorRX1 V DVDD DVSS AUTO ERF P/S="H" TVDD LRCK BICK SDTO DAUX FS96 XTOXTIMCKO2MCKO1RAVDDAVSS CM1 CM0 OCKS1 OCKS0 OCKS0 PDN OCKS1 CM0 CM1 DIF0 DIF1 DIF2 Parallel Control Mode

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 4 - n Ordering Guide AK4112A VF -40 ~ +85 °C 28pin VSOP (0.65mm pitch) nnnn Pin Layout 1DVDD DVSS V/TX TVDD XTI XTO PDN 7 R 8 Top View 9AVDD AVSS RX1 11 RX2/DIF0 12 RX3/DIF1 RX4/DIF2 CM0/CDTO CM1/CDTI OCKS1/CCLK OCKS0/CSN MCKO1 MCKO2 DAUX BICK SDTO LRCK ERF FS96 P/SN AUTO

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 5 - PIN/FUNCTION No. Pin Name I/O Function 1 DVDD - Digital Power Supply Pin, 3.3V

2 DVSS - Digital Ground Pin

3 TVDD - Input Buffer Power Supply Pin, 3.3V or 5V V O Validity Flag Output Pin in Parallel Mode

4 TX O Transmit channel (through data) Output Pin in Serial Mode

5X T I I X ' t a l I n p u t P i n

6 XTO O X'tal Output Pin

7P D N I Power-Down Mode Pin When “L”, the AK4112A is powered-down and reset. 8R - External Resistor Pin 18kW +/-1% resistor to A VSS externally.

9 A VDD - Analog Power Supply Pin

10 A VSS - Analog Ground Pin

11 RX1 I Receiver Channel 1

This channel is selected in Parallel Mode or default of Serial Mode. DIF0 I Audio Data Interface Format 0 Pin in Parallel Mode12 RX2 I Receiver Channel 2 in Serial Mode DIF1 I Audio Data Interface Format 1 Pin in Parallel Mode13 RX3 I Receiver Channel 3 in Serial Mode DIF2 I Audio Data Interface Format 2 Pin in Parallel Mode14 RX4 I Receiver Channel 4 in Serial Mode

15 AUTO O Non-PCM Detect Pin

“L”: No detect, “H” : Detect

16 P/S I Parallel/Serial Select Pin

“L”: Serial Mode, “H”: Parallel Mode

17 FS96 O

(RX Mode) “H” : fs=88.2kHz or more, “L” fs=54kHz or less. (X’tal Mode) “H” : XFS96=1, “L” : XFS96=0.

18 ERF O Unlock & Parity Error Output Pin

“L”: No Error, “H”: Error

19 LRCK I/O Output Channel Clock Pin

20 SDTO O Audio Serial Data Output Pin

21 BICK I/O Audio Serial Data Clock Pin

22 DAUX I Auxiliary Audio Data Input Pin

23 MCK02 O Master Clock #2 Output Pin

24 MCK01 O Master Clock #1 Output Pin

OCKS0 I Output Clock Select 0 Pin in Parallel Mode25 CSN I Chip Select Pin in Serial Mode OCKS1 I Output Clock Select 1 Pin in Parallel Mode26 CCLK I Control Data Clock Pin in Serial Mode CM1 I Master Clock Operation Mode Pin0 in Parallel Mode27 CDTI I Control Data Input Pin in Serial Mode CM0 I Master Clock Operation Mode Pin1 in Parallel Mode28 CDTO O Control Data Output Pin in Serial Mode Note 1: All input pins except internal pull-down pins should not be left floating.

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 6 - ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 2) Parameter Symbol min max Units Power Supplies: Analog Digital Input Buffer |AVSS-DVSS| (Note 3) AVDD DVDD TVDD D GND -0.3 -0.3 -0.3 4.6 4.6 6.0 0.3 V V V V Input Current , Any Pin Except Supplies IIN - –10 mA Input Voltage (Except XTI pin) Input Voltage (XTI pin) VIN VINX -0.3 -0.3 TVDD+0.3 DVDD+0.3 V V Ambient Temperature (power applied) Ta -40 85 °C Storage Temperature Tstg -65 150 °C Note 2: All voltages with respect to ground. Note 3: A VSS and DVSS must be connected to the same ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS=0V;Note 2) Parameter Symbol min typ max Units Power Supplies: Analog Digital Input Buffer AVDD DVDD TVDD 2.7 2.7 DVDD 3.3 3.3 3.3 3.6 AVDD 5.5 V V V Note 2: All voltages with respect to ground. S/PDIF RECEIVER CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V) Parameter Symbol min typ max Units Input Resistance Zin 10 k W Input Voltage VTH 350 mVpp Input Hysteresis VHY - 130 mV Input Sample Frequency fs 22 - 108 kHz DC CHARACTERISTICS (Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified) Parameter Symbol min typ max Units Power Supply Current Normal operation : PDN = “H” (Note 4) Power down: PDN = “L” (Note 5) 100 mA mA High-Level Input Voltage (Except XTI pin) High-Level Input Voltage (XTI pin) Low-Level Input Voltage VIH VIH VIL 70%DVDD 70%DVDD DVSS-0.3 TVDD DVDD 30%DVDD V V V High-Level Output Voltage (Iout=-400mA) Low-Level Output Voltage (Iout=400mA) VOH VOL DVDD-0.4 0.4 V V Input Leakage Current Iin - - – 10 mA Note 4: A VDD, DVDD=3.3V , TVDD=5.0V , CL=20pF, fs=96kHz, X'tal=12.288MHz, Clock Operation Mode 2, OCKS1=1, OCKS0=0. A VDD=8mA(typ), DVDD=12mA(typ), TVDD=10 mA(typ) Note 5: RX inputs are open and all digital input pins are held DVDD or DVSS.

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 7 - SWITCHING CHARACTERISTICS (Ta=25°C; DVDD, A VDD2.7~3.6V , TVDD=2.7~5.5V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Crystal Resonator Frequency fXTAL 11.2896 24.576 MHz External Clock Frequency Duty fECLK dECLK 11.2896 40 50 24.576 MHz MCKO1 Output Frequency Duty fMCK1 dMCK1 5.632 40 50 27.648 MHz MCKO2 output Frequency Duty fMCK2 dMCK2 2.816 40 50 27.648 MHz PLL Clock Recover Frequency (RX1-4) fpll 22 - 108 kHz LRCK Frequency D u t y C y c l e fs dLCK 48 108 kHz Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “›” (Note 6) BICK “›” to LRCK Edge (Note 6) LRCK to SDTO (MSB) BICK “fl” to SDTO DAUX Hold Time DAUX Setup Time tBCK tBCKL tBCKH tLRB tBLR tLRM tBSD tDXH tDXS 140 ns ns ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “fl” to LRCK BICK “fl” to SDTO DAUX Hold Time DAUX Setup Time fBCK dBCK tMBLR tBSD tDXH tDXS -20 64fs Hz ns ns ns ns Control Interface Timing C C L K P e r i o d C C L K P u l s e W i d t h L o w P u l s e W i d t h H i g h C D T I S e t u p T i m e C D T I H o l d T i m e C S N “ H ” T i m e C D T O D e l a y C S N “›” to CDTO Hi-Z tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 150 ns ns ns ns ns ns ns ns ns ns Reset Timing P D N P u l s e W i d t h t P W 1 5 0 n s Note 6: BICK rising edge must not occur at the same time as LRCK edge.

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 8 - n Timing Diagram tLRB LRCK BICK SDTO tBSD tBLR tBCKL tBCKH tLRM 50%DVDD 50%DVDD 50%DVDD DAUX 50%DVDD tDXS tDXH Serial Interface Timing (Slave Mode) LRCK BICK SDATA tBSD tMBLR 50%DVDD 50%DVDD 50%DVDD DAUX tDXH 50%DVDD tDXS Serial Interface Timing (Master Mode) tCCKL CSN CCLK tCDS CDTI tCDH tCSS C0 A4 tCCKH CDTO Hi-Z R/WC0 50%DVDD 50%DVDD 50%DVDD WRITE/READ Command Input Timing

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 9 - tCSW CSN CCLK CDTI D2 D0 tCSH CDTO Hi-Z D1D3 50%DVDD 50%DVDD 50%DVDD WRITE Data Input Timing CSN CCLK tDCD CDTO D7 D6 CDTI A1 A0 D5Hi-Z 50%DVDD 50%DVDD 50%DVDD 50%DVDD READ Data Output Timing 1 CSN CCLK tCCZ CDTO D2 D1 CDTI D0D3 tCSW tCSH 50%DVDD 50%DVDD 50%DVDD 50%DVDD READ Data Input Timing 2 tPW PDN 30%DVDD Power Down & Reset Timing

FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect. OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2. Table 1. Master clock frequencies select clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.

0 ON ON PLL RFS96 RX21 0 1 ON ON X'tal XFS96 DAUX

Table 2. Clock Operation Mode select

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 11 - nnnn Clock Source The following circuits are available to feed the clock to XTI pin (#5 pin) of AK4112A. 1) X’tal Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF) 2) External clock Note: Input clock must not exceed DVDD. 3) Fixed to the Clock Operation Mode 0 XTI XTO AK4112A XTI XTO AK4112A External Clock XTI XTO AK4112A

by CS12 bit in control register. Table 3. fs information in Consumer Mode

01 R e s e r v e d 0 0

Table 4. fs information in Profession Mode

1 ON 0X100

Table 5. PEM in Consumer Mode

1 ON 110

Table 6. PEM in professional Mode

by sampling frequency and pre-emphasis information in the channel status. The AK4112A goes this mode at default. status bits in channel 1. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is “0”.

001 O F F

100 O F F

101 O F F

111 O F F

Table 7. De-emphasis Auto Control at DEAU=“1” and PEM=“1”

001 O F F D e f a u l t

Table 8. De-emphasis Manual Control at DEAU=“0” and PEM=“1”

RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled. The AK4112A should be reset once by bringing PDN pin = “L” upon power-up. registers are initialized, and clocks are stopped. Reading/Witting to the register are diabled. are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled. source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit “0”.

00 R X 1 D e f a u l t

01 R X 2

10 R X 3

11 R X 4

Table 9. Recovery data select Table 10. Output data select

it is “L” when the PLL is OFF (Clock Operation Mode 1).

1. Unlock Error : “H” when the PLL goes UNLOCK state.
2. Parity Error : Updated every sub-frame cycle.
3. Biphase Error : Updated every sub-frame cycle
4. Frame length Error : Updated every sub-frame cycle
5. STC (Status Change) flag=“1” : Holds “1” until reading 03H.

when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect. When unlock state, the channel status bits are not updated and the previous data is maintained. Table 11. Error handling (Parallel Mode) previous data is maintained. Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 17 - Command ERF MCKO, BICK, LRCK SDTO STC bit V READ 03H Reset (ch. status ) (state B)(state A ) (status change ) ERF Hold Time Hold “1” ERF pin timing at Status Change error(UNLOCK, PAR, BIP , FRERR) ERF SDTO(UNLOCK) Vpin (UNLOCK) MCKO,BICK,LRCK (UNLOCK) Vpin (except UNLOCK) Previous Data register (UNOCK, PAR, BIP , FRERR) Hold ”1” Command READ 04H MCKO,BICK,LRCK (except UNLOCK) (fs: around 20kHz) SDTO (except UNLOCK) ERF Hold Time Reset (error) ERF pin timing at UNLOCK, PAR, BIP, FRERR error

Figure 4. Error handling sequence Example

last 4LSBs are auxiliary data (see Figure 5). in Clock Operation Mode 1, 3 and unlock state of Mode 2. Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2. Figure 5. Bit configuration Table 13. Audio data format

should be reset by PDN= “L”. Figure 10. Control I/F Timing

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 22 - n Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Clock & Power down Control 0 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN 01H Input/Output Control MPAR MSTC CS12 TXE IPS1 IPS0 OPS1 OPS0 02H Format & De-emphasis Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS 03H Receiver status 1 ERF 0 AUDION AUTO PEM FS1 FS0 RFS96 04H Receiver status 2 CV STC CRC UNLOCK V FRERR BIP PAR 05H Channel A Status Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 06H Channel A Status Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 07H Channel A Status Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 08H Channel A Status Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 09H Channel B Status Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0AH Channel B Status Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 0BH Channel B Status Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 0CH Channel B Status Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 11H Count Control 0 0 0 0 0 EFH1 EFH0 XFS96 Notes: For addresses from 12H to 1FH, data must not be written. When PDN pin goes “L”, the registers are initialized to their default values. When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values. All data can be written to the register even if PWN bit is “0”.

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 23 - nnnn Register Definitions Reset & Initialize Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Clock & Power down Control 0 BCU CM1 CM0 OCKS1 OCKS0 PWN RSTN R/W RD R/W R/W R/W R/W R/W R/W R/W d e f a u l t 00000011 RSTN: Timing Reset & Register Initialize 0: Reset & Initialize 1: Normal Operation PWN: Power Down 0: Power down 1: Normal Operation OCKS1-0: Master Clock frequency Select CM1-0: Master Clock Operation Mode Select BCU: Block start & C/U output Mode When BCU=1, the 3 output pins change another function. MCKO2 pin fi B; block start signal AUTO pin fi C bit FS96 pinfi U bit The block signal goes high at the start of frame 0 and remains high until the end of frame 31. (B, C, U, V output timing at RX mode, Master mode) B C (or U,V) LRCK C(L0) C(R0) C(L1) C(R31)C(L31) C(L32)C(R191) 1/4fs SDTO (except I2S) L191 R191 L0 R30 R31L31 SDTO ( I2S) L191 R191 L30 L31R30L0R190

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 24 - Input/Output Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 01H Input/Output Control MPAR MSTC CS12 TXE IPS1 IPS0 OPS1 OPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W d e f a u l t 10010000 OPS1-0: Output Through Data Select IPS1-0: Input Recovery Data Select TXE: TX Output Enable 0: Disable. TX output pin is placed in a high impedance state. 1: Enable CS12: Channel Status Select 0: Channel 1 1: Channel 2 Selects which channel status is used to derive AUDION, PEM, FS1 and FS0. The de-emphasis filter, however, is always controlled by channel 1 in the Parallel Mode. MSTC: Status change flag mask bit This bit is low to mask status change from being reported by ERF. MPAR: Parity mask bit This bit is low to mask Parity Error, Biphase Error and Frame Length Error from being reported by ERF. Format & De-emphasis Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Format & De-emphasis Control V/TX DIF2 DIF1 DIF0 DEAU DEM1 DEM0 DFS R/W R/W R/W R/W R/W R/W R/W R/W R/W d e f a u l t 01001010 V/TX: V/TX Output Select 0: Validity Flag Output. This output is updated every fs cycle. 1: TX DFS: 96kHz De-emphasis Control DEM1-0: 32, 44.1, 48kHz De-emphasis Control DEAU: De-emphasis Auto Detect Enable 0: Disable 1: Enable DIF2-0: Audio Data Format Control

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 25 - Receiver Status 1 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Receiver status 1 ERF 0 AUDION AUTO PEM FS1 FS0 RFS96 R / W R DR DR DR DR DR DR DR D d e f a u l t 00000000 RFS96: 96kHz Sampling Detect at Recovery Mode. 0: fs=54kHz or less. 1: fs=88.2kHz or more FS1-0: Sampling Frequency Output PEM: Pre-emphasis Output 0: OFF 1: ON This bit is made by encoding channel status bits. AUTO: Non-PCM Auto Detect 0: No detect 1: Detect This function is the same as AUTO pin. AUDION: Audio bit Output 0: Audio 1: Non Audio ERF: Unlock or Parity Error or Status change 0: No Error or No change 1: Error or Change This function is the same as ERF pin. This bit goes “1” when Unlock Error, Parity Error, Biphase Error, Frame Length Error or Status Change occurs. If MPAR=0 & MSTC=0, only an unlock error is reported. Receiver Status 2 Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Receiver status 2 CV STC CRC UNLOCK V FRERR BIP PAR R / W R DR DR DR DR DR DR DR D d e f a u l t 00000000 PAR: Parity Status (0:No Error, 1:Error) It is high if Parity Error is detected in the sub-frame. PAR is unaffected by the state of MPAR. BIP: Biphase Status (0:No Error, 1:Error) FRERR: Frame Error Status (0:No Error, 1:Error) V: Validity bit (0:No Error, 1:Error) UNLOCK: PLL Lock status (0:Lock, 1:Unlock) CRC: Cyclic Redundancy Check (0:No Error, 1:Error on either channel) STC: Status change flag of Receiver status 1 (0:No change, 1:change) This flag goes “H” when the latest value of D5-0 in Receiver Status 1(03H) is different from the previous value. This comparison is made at every fs cycle. This bit returns to “L” by reading Receiver Status 1(03H). The flag is disabled during the first block after Reset. CV: Channel Status Validity (0:Valid, 1:Not Valid, data is updating) This signal goes “H” at the start of frame 0 and maintains “H” until the end of frame 31.

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 26 - Channel Status Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Channel A Status Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 06H Channel A Status Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 07H Channel A Status Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 08H Channel A Status Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 09H Channel B Status Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 0AH Channel B Status Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 0BH Channel B Status Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 0CH Channel B Status Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 R/W RD default Not initialized CA31-0: Channel A Status Byte 4-1 CB31-0: Channel B Status Byte 4-1 Bit definition changes depending upon PRO bit setting. When CV=1, these bits are updating and may be invalid. Burst Preamble Pc/Pd in non-PCM encoded Audio bitstreams Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0DH Burst Preamble Pc Byte 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 0EH Burst Preamble Pc Byte 1 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 0FH Burst Preamble Pd Byte 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 10H Burst Preamble Pd Byte 1 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 R/W RD default Not initialized PC15-0: Burst Preamble Pc Byte 1, 0 PD15-0: Burst Preamble Pd Byte 1, 0 Count Control Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 1 1 H C o u n t C o n t r o l 00000 E F H 1 E F H 0 X F S 9 6 R / W R DR DR DR DR D R / W R / W R / W d e f a u l t 00000010 XFS96: FS96 output select at X’tal Mode (clock Operation Mode1, Mode3 and Unlock state of Mode2) 1: FS96pin=“H” 0: FS96pin=“L” EFH1-0: Error Flag Hold Count Select 00: 512 LRCK 01: 1024 LRCK 10: 2048 LRCK 11: 4096 LRCK

Pc 16 bits Burst info see Table 15. Table 14. Burst preamble words Table 15. Fields of burst info Pc

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 28 - nnnn Non-PCM Bitstream timing 1) When Non-PCM preamble is not coming within 4096 frames, Pa Pc1 Pd1Pb Pa Pc2 Pd2Pb Pa Pc3 Pd3Pb “0” Pc1 Pc2 “0” Pd1 Pd2 Pd3 Pc3 PDN pin Bit stream AUTO Pc Register Pd Register Repetition time >4096 frames 2) When Non-PCM bitstream stops Pa Pc1 Pd1Pb Stop Pa Pcn PdnPb Pc0 Pc1 Pd0 Pd1 Pdn Pcn ERF pin Bit stream AUTO Pc Register Pd Register ERF hold time 2~3 Syncs (B,M or W) <20mS (Lock time) <Repetition time

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 30 - PACKAGE 1.0 0.1–0.1 0-10° Detail A Seating Plane NOTE: Dimension "*" does not include mold flash. 0.10 *9.8–0.2 1.25 –0.2 A 1 14 1528 28pin VSOP (Unit: mm) *5.6–0.2 7.6–0.2 0.5–0.2 +0.1 0.675 nnnn Material & Lead finish Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate

ASAHI KASEI [AK4112A] MS0020-E-00 2000/3 - 31 - MARKING AKM AK4112AVF XXXB YYYYC XXXXBYYYYC: Date code identifier XXXB: Lot number (X : Digit number, B : Alpha character ) YYYYC: Assembly date (Y : Digit number C : Alpha character) IMPORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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