AK4101A AKM | Alldatasheet
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ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 1 - GENERAL DESCRIPTION The AK4101A is a four outputs digital audio transmitter (DIT) which supports data rate up to 192kHz sample rate operation. The AK4101A supports AES3, IEC60958, S/PDIF & EIAJ CP1201 interface standards. The AK4101A accepts a udio data and auxiliary information data and etc, which is then biphase-encoded and driven on to a cable. The audio serial port supports eight formats.
FEATURES
o Sampling Rate up to 192kHz o Support AES3, IEC60958, S/PDIF & EIAJ CP1201 professional and consumer formats o Generates CRCC codes and parity bits o Four on-chip RS422 line drivers o 64-byte on-chip buffer memory for Channel Status and User bits o Supports synchronous/asynchronous access to Channel Status and User bits o Supports multiple clock frequencies: 128fs, 256fs, 384fs and 512fs o Supports Left/Right justified and I2S audio formats o Easy to use 4 wire, Serial Host Interface o Audio Routing Mode (Transparent Mode) o Power supply: 4.75 to 5.25V o TTL level I/F o Small Package: 44pin LQFP o Temperature range of - 40 to 85 °C Quad Outputs 192kHz 24-Bit DIT AK4101A
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 2 - n Block Diagram Host Serial Interface Audio Serial Interface BICK LRCK SDTI1 TXP1 MUX CRCC Generator Prescaler RS422 Line Drivers Biphase Encoder SDTI2 SDTI3 SDTI4 DIF2 Drivers DIF1 Drivers DIF0 Drivers CKS1 Drivers CKS0 MCLK BLS TRANS VSS Drivers VDD Drivers TXN1 TXP2 TXN2 TXP3 TXN3 TXP4 TXN4 V12 V34 FS0 FS1 FS2 FS3 Register CSN CCLK CDTI CDTO ANS PDN
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 3 - n Ordering Guide AK4101AVQ 40 ∼ +85°C 44pin LQFP (0.8mm pitch) n Pin Layout PDN TRANS MCLK 2 SDTI1 3 SDTI2 4 SDTI3 5 SDTI4 6 VDD 7 VSS 8 BICK 9 LRCK 10 FS0/CSN 11 V34 V12 DIF2 DIF1 VDD DIF0 FS1/CDTI FS2/CCLK FS3/CDTO ANS BLS CKS0 VSS TXP1 TXN1 TXP2 TXN2 VSS VDD TXP3 TXN3 TXP4 TXN4 CKS1 AK4101AVQ Top View n Comparison AK4101 with AK4101A Function AK4101 AK4101A Ambient Temperature -10 ~ 70°C -40 ~ 85°C CRCC generation by FS3-0 pins Synchronous mode X O CRCC generation by FS3-0 bits Asynchronous mode X O O: Input data is reflected to CRCC. X: Input data is ignored for CRCC.
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 4 - PIN/FUNCTION No. Pin Name I/O Function
1 PDN I Power Down & Reset Pin (Pull -up Pin)
When “L”, the AK4101A is powered-down, TXP/N pins are “L” and the control registers are reset to default values.
2 MCLK I Master Clock Input Pin
3 SDTI1 I Audio Serial Data Input 1 Pin
4 SDTI2 I Audio Serial Data Input 2 Pin (Pull-down Pin)
5 SDTI3 I Audio Serial Data Input 3 Pin (Pull -down Pin)
6 SDTI4 I Audio Serial Data Input 4 Pin (Pull -down Pin)
7 VDD - Power Supply Pin, 4.75V∼5.25V
8 VSS - Ground Pin, 0V
9 BICK I/O Audio Serial Data Clock Input/Output Pin
Serial Clock for SDTI pins which can be configured as an output based on the DIF2-0 inputs.
10 LRCK I/O Input/Output Channel Clock Pin
Indicates left or right channel, and can be configured as an output based on the DIF2-0 inputs. FS0 I Sampling Frequency Select 0 Pin at Synchronous mode (Pull-down Pin) CSN I Host Interface Chip Select Pin at Asynchronous mode (Pull-down Pin) AKMODE I AK4112B Mode Pin at Audio routing mode (Pull-down Pin) 0: Non-AKM receivers mode, 1: AK4112B mode FS1 I Sampling Frequency Select 1 Pin at Synchronous mode (Pull-down Pin) 12 CDTI I Host Interface Data Input Pin at Asynchronous mode (Pull-down Pin) FS2 I Sampling Frequency Select 2 Pin at Synchronous mode (Pull-down Pin) 13 CCLK I Host Interface Bit Clock Input Pin at Asynchronous mode (Pull-down Pin) FS3 I Sampling Frequency Select 3 Pin at Synchronous mode (Pull-down Pin) 14 CDTO O Host Interface Data Output Pin at Asynchronous mode (Pull-down Pin)
15 C1 I Channel Status Bit Input Pin for Channel 1
16 C2 I Channel Status Bit Input Pin for Channel 2 (Pull-down Pin)
17 C3 I Channel Status Bit Input Pin for Channel 3 (Pull-down Pin)
18 C4 I Channel Status Bit Input Pin for Channel 4 (Pull-down Pin)
19 ANS I Asynchronous/Synchronous Mode Select Pin (Pull-up Pin)
0: Asynchronous mode, 1: Synchronous mode
20 BLS I/O Block Start Input/Output Pin (Pull -down Pin)
In normal mode, the channel status block output is “H” for the first four bytes. In audio routing mode, the pin is configured as an input. When PDN pin = “L”, BLS pin goes “H” at Normal mode.
21 CKS0 I Clock Mode Select 0 Pin (Pull -up Pin)
22 VSS - Ground Pin, 0V
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 5 - No. Pin Name I/O Description
23 CKS1 I Clock Mode Select 1 Pin (Pull-down Pin)
24 TXN4 O Negative Differential Output Pin for Channel 4
25 TXP4 O Positive Differential Output Pin for Channel 4
26 TXN3 O Negative Differential Output Pin for Channel 3
27 TXP3 O Positive Differential Output Pin for Channel 3
28 VDD - Power Supply Pin, 4.75V∼5.25V
29 VSS - Ground Pin, 0V
30 TXN2 O Negative Differential Output Pin for Channel 2
31 TXP2 O Positive Differential Output Pin for Channel 2
32 TXN1 O Negative Differential Output Pin for Channel 1
33 TXP1 O Positive Differential Output Pin for Channel 1
34 DIF0 I Audio Serial Interface Select 0 Pin (Pull -down Pin)
35 VDD - Power Supply Pin, 4.75V∼5.25V
36 DIF1 I Audio Serial Interface Select 1 Pin (Pull -down Pin)
37 DIF2 I Audio Serial Interface Select 2 Pin (Pull -down Pin)
38 U1 I User Data Bit Input Pin for Channel 1 (Pull-down Pin)
39 U2 I User Data Bit Input Pin for Channel 2 (Pull-down Pin)
40 U3 I User Data Bit Input Pin for Channel 3 (Pull-down Pin)
41 U4 I User Data Bit Input Pin for Channel 4 (Pull-down Pin)
42 V12 I Validity Bit Input Pin for Channel 1 & Channel 2
43 V34 I Validity Bit Input Pin for Channel 3 & Channel 4 (Pull-down Pin)
44 TRANS I Audio Routing Mode (Transparent Mode) Pin at Synchronous mode
0: Normal mode, 1: Audio routing mode (Transparent mode) Notes: 1. Internal pull-up and pull-down resistors are connected on-chip. The value of the resistors is 43kΩ (typ). 2. All input pins except internal pulldown/pull-up pins should not be left floating.
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 6 - ABSOLUTE MAXIMUM RATINGS (VSS=0V; Note 3) Parameter Symbol min max Units Power Supply VDD -0.3 6.0 V Input Current (All pins except supply pins) IIN - ±10 mA Input Voltage VIN -0.3 VDD+0.3 V Ambient Operating Temperature Ta -40 85 °C Storage Temperature Tstg -65 150 °C Notes: 3. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS=0V; Note 1) Parameter Symbol min typ max Units Power Supply VDD 4.75 5.0 5.25 V *AKM assumes no responsibility for the usage beyond the conditions in this datasheet. DC CHARACTERISTICS (Ta=25°C; VDD=4.75~5.25V) Parameter Symbol min typ max Units Power Supply Current (fs=108kHz, Note 4) IDD 10 20 mA High-Level Input Voltage Low-Level Input Voltage VIH VIL 2.4 0.8 V V High-Level Output Voltage (Except TXP/N pins : Iout=-400µA) (TXP/N pins: Iout= -8mA) Low-Level Output Voltage (Except TXP/N pins: I out= 400µA) (TXP/N pins: Iout= 8m A) VOH VOH VOL VOL VDD-1.0 VDD-0.8 0.4 0.6 V V V V Input Leakage Current Iin - - ±10 µA Notes: 4. Power supply current (IDD) is 4mA(typ)@fs=48kHz and 12mA(typ)@fs=192kHz. IDD increases by 20mA(typ) per channel with professional output driver circuit. IDD is 90mA(typ) if all four channels have professional output driver circuit. IDD is 150µA(typ) if PDN pin = “L”, TRANS pin = “H” and all other input pins except internal pull-up/pull-down pins are held to VSS.
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 7 - SWITCHING CHARACTERISTICS (Ta=25°C; VDD=4.75~5.25V; CL=20pF) Parameter Symbol min typ max Units Master Clock Timing Frequency Duty Cycle fCLK dCLK 3.584 27.648 MHz LRCK Timing Frequency Duty Cycle at Slave Mode Duty Cycle at Master Mode fs dLCK 192 kHz Audio Interface Timing Slave Mode BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK “↑” (Note 5) BICK “↑” to LRCK Edge (Note 5) SDTI Hold Time SDTI Setup Time tBCK tBCKL tBCKH tLRB tBLR tSDH tSDS ns ns ns ns ns ns ns Master Mode BICK Frequency BICK Duty BICK “↓” to LRCK SDTI Hold Time SDTI Setup Time fBCK dBCK tMBLR tSDH tSDS -20 64fs Hz ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CDTO Delay CSN “↑” to CDTO Hi-Z (Note 6) tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tDCD tCCZ 200 520 ns ns ns ns ns ns ns ns ns ns Power-down & Reset Timing PDN Pulse Width tPDW 150 ns Notes: 5. BICK rising edge must not occur at the same time as LRCK edge. 6. CDTO pin is internally connected to a pull-down resistor.
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 8 - n Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL dCLK = tCLKH x fCLK x 100 = tCLKL x fCLK x 100 VIH LRCK VIL 1/fs tBCK tBCKL VIH tBCKH BICK VIL Clock Timing tLRB LRCK VIH BICK VIL tSDS VIH SDTI VIL tSDH VIH VIL tBLR Audio Interface Timing (Slave Mode) LRCK BICK tMBLR 50%VDD 50%VDD SDTI tSDHtSDS VIH VIL Audio Interface Timing (Master Mode)
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 9 - tCCKL CSN CCLK tCDS CDTI tCDH tCSS C0 * tCCKH CDTO Hi-Z (with pull-down resistor) * C1 VIH VIL VIH VIL VIH VIL WRITE/READ Command Input Timing tCSW CSN CCLK CDTI D2 D0 tCSH CDTO D1D3 VIH VIL VIH VIL VIH VIL Hi-Z (with pull-down resistor) WRITE Data Input Timing CSN CCLK tDCD CDTO CDTI A1 A0 Hi-Z (with pull-down resistor) 50%VDD VIH VIL VIH VIL VIH VIL D7 D6 D5 READ Data Output Timing 1
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 10 - CSN CCLK tCCZ CDTO D2 D1 CDTI D0D3 tCSW tCSH 50%VDD VIH VIL VIH VIL VIH VIL READ Data Output Timing 2 tPDW PDN VIL Power-down & Reset Timing
MCLK should be synchronized with LRCK but the phase is not critical. following frequencies are supported for MCLK. Table 1. MCLK Frequency
- Asynchronous Mode (software controlled)
control for mute, reset, audio format selection, clock frequency settings and output enables, via the serial host interface.
- Synchronous Mode (hardware controlled)
and driven through an RS422 line driver. The four set of channels have individual channel status and user data pins. Table 2. Mode setting Figure 1. Audio routing mode timing (AKMODE pin = “0”)
and bits 6-3 of Channel Status Byte 4 in professional mode can be set by FS3-0 pins.
0001 Not Indicated 0001
0101 Reserved 0101
0111 Reserved 0111
1001 Reserved 1001
1011 Reserved 1011
1101 Reserved 1101
1111 Reserved 1111
Table 4. Sampling frequency setting (Consumer mode)
0000 Not Defined 00 0000
0100 Not Defined 00 0000
0101 Not Defined 00 0000
0110 Not Defined 00 0000
0111 Not Defined 00 0000
1000 For vectoring 00 1000
1111 Not Defined 00 1111
Table 5. Sampling frequency setting (Professional mode)
Table 7. Register Map (1) In stereo mode, A indicates Left Channel and B indicates Right Channel. (2) In asynchronous mode, the DIF2-0 and CKS1-0 bits are logically “ORed” with the DIF2-0 and CKS1-0 pins. (3) For addresses from 42H to FFH, data is not written. (4) The PDN pin = “L” resets the registers to their default values.
0: Resets the internal frame and bit counters. Control registers are not initialized. TXP pin is “H” and TXN pin is “L”. In normal mode, BLS pin is “H”. MUTEN: Power Down and Mute for Asynchronous Mode. 0: Power Down Command. Control registers are not initialized. TXP and TXN pins are “L”. In normal mode, BLS pin is “H”. CKS1-0 bits are logically ORed with CKS1-0 pins. DIF2-0 bits are logically ORed with DIF2-0 pins. CRCE: CRCC Enable at professional mode. V1-4: Validity Flag for each channel. Table 8. V bit setting at asynchronous mode
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 24 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 02H Ch 1 A-channel C-bit buffer for Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 06H Ch 1 B-channel C-bit buffer for Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 12H Ch 2 A-channel C-bit buffer for Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 16H Ch 2 B-channel C-bit buffer for Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 22H Ch 3 A-channel C-bit buffer for Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 26H Ch 3 B-channel C-bit buffer for Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 32H Ch 4 A-channel C-bit buffer for Byte 0 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 36H Ch 4 B-channel C-bit buffer for Byte 0 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 1 0 0 C0-7: Channel Status Byte 0 Default: “00100000” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H Ch 1 A-channel C-bit buffer for Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 07H Ch 1 B-channel C-bit buffer for Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 13H Ch 2 A-channel C-bit buffer for Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 17H Ch 2 B-channel C-bit buffer for Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 23H Ch 3 A-channel C-bit buffer for Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 27H Ch 3 B-channel C-bit buffer for Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 33H Ch 4 A-channel C-bit buffer for Byte 1 CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 37H Ch 4 B-channel C-bit buffer for Byte 1 CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 C8-15: Channel Status Byte 1 Default: “00000000”
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 25 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 04H Ch 1 A-channel C-bit buffer for Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 14H Ch 2 A-channel C-bit buffer for Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 24H Ch 3 A-channel C-bit buffer for Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 34H Ch 4 A-channel C-bit buffer for Byte 2 CA23 CA22 CA21 CA20 CA19 CA18 CA17 CA16 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 1 0 0 0 0 CA16-23: Channel Status Byte 2 for A-channel Default: “00001000” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H Ch 1 B-channel C-bit buffer for Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 18H Ch 2 B-channel C-bit buffer for Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 28H Ch 3 B-channel C-bit buffer for Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 38H Ch 4 B-channel C-bit buffer for Byte 2 CB23 CB22 CB21 CB20 CB19 CB18 CB17 CB16 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 1 0 0 0 0 0 CB16-23: Channel Status Byte 2 for B-channel Default: “00000100” Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Ch 1 A-channel C-bit buffer for Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 09H Ch 1 B-channel C-bit buffer for Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 15H Ch 2 A-channel C-bit buffer for Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 19H Ch 2 B-channel C-bit buffer for Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 25H Ch 3 A-channel C-bit buffer for Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 29H Ch 3 B-channel C-bit buffer for Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 35H Ch 4 A-channel C-bit buffer for Byte 3 CA31 CA30 CA29 CA28 CA27 CA26 CA25 CA24 39H Ch 4 B-channel C-bit buffer for Byte 3 CB31 CB30 CB29 CB28 CB27 CB26 CB25 CB24 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 1 0 C24-31: Channel Status Byte 3 Default: “01000000”
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 26 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH- 0DH Ch 1 A-channel U-bit buffer for Byte 0-3 UA7 UA31 UA0 UA24 0EH- 11H Ch 1 B-channel U-bit buffer for Byte 0-3 UB7 UB31 UB0 UB24 1AH- 1DH Ch 2 A-channel U-bit buffer for Byte 0-3 UA7 UA31 UA0 UA24 1EH- 21H Ch 2 B-channel U-bit buffer for Byte 0-3 UB7 UB31 UB0 UB24 2AH- 2DH Ch 3 A-channel U-bit buffer for Byte 0-3 UA7 UA31 UA0 UA24 2EH- 31H Ch 3 B-channel U-bit buffer for Byte 0-3 UB7 UB31 UB0 UB24 3AH- 3DH Ch 4 A-channel U-bit buffer for Byte 0-3 UA7 UA31 UA0 UA24 3EH- 41H Ch 4 B-channel U-bit buffer for Byte 0-3 UB7 UB31 UB0 UB24 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 U0-31: User Data Default: all “0”
Table 9. Default Values of Control Register
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 28 - PACKAGE 0.15 0.17±0.050.37±0.10 10.00 1.70max 1 11 2333 44pin LQFP (Unit: mm) 10.00 12.80±0.30 0.80 12.80±0.30 0∼0.2 0°∼10° 0.60±0.20 n Package & Lead frame material Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate (Pb free)
ASAHI KASEI [AK4101A] MS0250-E-00 2003/07 - 29 - MARKING AK4101AVQ XXXXXXX 1) Pin #1 indication 2) Date Code: XXXXXXX(7 digits) 3) Marking Code: AK4101AVQ 4) Asahi Kasei Logo IMPORTANT NOTICE
- These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
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