AK2540

AK2540 AKM | Alldatasheet

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ASAHI KASEI [AK25 40] MS0012-E-00 2000 /11 AK2540 Quad T1 Transceiver FEATURE - 4ch short haul T1 transceiver with jitter attenuator - Jitter Tolerance: Compliant with GR-499 Category I,II and TR 62411 - Transmitter Pulse Shape: Compliant with GR-499 and ANSI T1.102 (1993) - Loss of Signal Detection - Local/Remote Loopback Mode - Driver Failure Monitor - Current limiter in transmit drivers for short circuits protection - Hardware/Host Control Mode - Single 3.3V±5% or 5.0V±5% Operation - Low Power Consumption - Package: 144LQFP BLOCK DIAGRAM Quad T1 Transceiver Block Diagram TRANSCEIVER 1 TRANSCEIVER 2-4 CLOCK &DATA RECOVER Y CLKGEN MCLK RTIP1 RRING1 RCLK1 RPOS1 RNEG1 LOS1 RCLK2-4 RPOS2-4 RNEG2-4 TCLK2-4 TPOS2-4 TNEG2-4 PULSE SHAPER TTIP1 TRING1TNEG1 TPOS1 TCLK1 CONTROL DFM2-4 TTIP2-4 TRING2-4 RTIP2-4 RRING2-4 LOS2-4 Local Loopback Remote Loopback LOS JITTER ATT D F M DFM1 TAOS MCLKSEL

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /12 GENERAL DESCRIPTIONS The AK2540 is the quad short haul T1 transceiver for asynchronous applications, such as M13 MUX, etc. It includes Transmitter, Clock and Data Recovery, Jitter Attenuator, LOS Detector, Driver Failure Monitor, Control Circuit s, etc. in one LQFP-144 package. Internally generated transmit pulse provides the appropriate pulse shape for line length ranging from 0 to 655 feet from a DSX-1 cross connect. PIN ASSIGNMENTS DFM1 AIS1 TPOS1 TNEG1 TCLK1 LOS1 RPOS1 RNEG1 NC RCLK1 DFM2 AIS2 NC NC TAVDD2 TAVSS2 NC DVSS DVDD DAVSS1 NC TPOS2 TNEG2 TCLK2 NC LOS2 RPOS2 RNEG2 RCLK2 NC JASELT JASELR NC RAVDD RAVSS NC 108 107 106 105 104 103 102 101 100 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 DFM3 AIS3 T POS3 TNEG3 TCLK3 LOS3 RPOS3 RNEG3 NC RCLK3 DFM4 AIS4 TAVDD1 NC TAVSS1 TPOS4 TNEG4 TCLK4 LOS4 RPOS4 RNEG4 RCLK4 DAVSS2 NC IOVDD IOVSS NC NC AD0_LENG21 AD1_LENG11 AD2_LENG01 AD3_ LENG22 AD4_LENG12 AD5_LENG02 AD6_LENG23 AD7 _ LENG13 NC NC NC LLOOP4 RLOOP4 TTIP4 TVSS4 TVDD4 TRING4 AVSS4 NC LLOOP3 RLOOP3 TTIP3 TVSS3 TVDD3 TRING3 AVSS3 NC LLOOP2 RLOOP2 TTIP2 TVSS2 TVDD2 TRING2 AVSS2 NC NC LLOOP1 RLOOP1 TTIP1 TVSS1 TVDD1 TRING1 AVSS1 NC NC R/ W ( WR ) _LENG03 AS ( ALE ) _LENG24 DS ( RD ) _LENG14 CS_LENG04 BTS_AIS1SEL INT _LOMC HWMODE RESET SEL5V CLKE TEST8 RRING4 RTIP4 TEST7 TEST6 RRING3 RTIP3 TEST5 PVSS NC MCLK MCLKSEL PVDD BVDD BGREF BVSS TEST4 RRING2 RTIP2 TEST3 TEST2 RRING1 RTIP1 TEST1 NC (TOP VIEW)

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /13 PIN CONDITION Pin # Pin Name I/O Pin Type AC Load DC Load Comments

1 DFM3 O CMOS ≤15pF

2 AIS3 I CMOS Note2 )

3 TPOS3 I CMOS

4 TNEG3 I CMOS

5 TCLK3 I CMOS

6 LOS3 O CMOS ≤15pF

7 RPOS3 O CMOS ≤15pF

8 RNEG3 O CMOS ≤15pF

10 RCLK3 O CMOS ≤15pF

11 DFM4 O CMOS ≤15pF

12 AIS4 I CMOS Note2 )

13 TAVDD1 I Power

15 TAVSS1 I Power

16 TPOS4 I CMOS

17 TNEG4 I CMOS

18 TCLK4 I CMOS

19 LOS4 O CMOS ≤15pF

20 RPOS4 O CMOS ≤15pF

21 RNEG4 O CMOS ≤15pF

22 RCLK4 O CMOS ≤15pF

23 DAVSS2 I Power

25 IOVDD I Power

26 IOVSS I Power

29 AD0_LENG21 I/O CMOS ≤50pF

30 AD1_LENG11 I/O CMOS ≤50pF

31 AD2_LENG01 I/O CMOS ≤50pF

32 AD3_LENG22 I/O CMOS ≤50pF

33 AD4_LENG12 I/O CMOS ≤50pF

34 AD5_LENG02 I/O CMOS ≤50pF

35 AD6_LENG23 I/O CMOS ≤50pF

36 AD7_LENG13 I/O CMOS ≤50pF

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /14 Pin # Pin Name I/O Pin Type AC Load DC Load Comments 37 NC

38 R/W ( WR ) _LENG03 I CMOS

39 AS ( ALE ) _LENG24 I CMOS

40 DS ( RD ) _LENG14 I CMOS

41 CS _LENG04 I CMOS

42 BTS_AIS1SEL I CMOS

43 INT _LOMC O Open drain PMOS

44 HWMODE I CMOS

45 RESET I CMOS

46 SEL5V I CMOS

47 CLKE I CMOS

48 TEST8 I CMOS Note1 )

49 RRING4 I Analog

50 RTIP4 I Analog

51 TESE7 I CMOS Note1 )

52 TEST6 I CMOS Note1 )

53 RRING3 I Analog

54 RTIP3 I Analog

55 TEST5 I CMOS Note1 )

56 PVSS I Power

58 MCLK I CMOS

59 MCLKSEL I CMOS

60 PVDD I Power

61 BVDD I Power

62 BGREF O Analog 12k Ω ± 1% accuracy

63 BVSS I Power

64 TEST4 I CMOS Note1 )

65 RRING2 I Analog

66 RTIP2 I Analog

67 TEST3 I CMOS Note1 )

68 TEST2 I CMOS Note1 )

69 RRING1 I Analog

70 RTIP1 I Analog

71 TEST1 I CMOS Note1 )

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /15 Pin # Pin Name I/O Pin Type AC Load DC Load Comments 73 NC

74 RAVSS I Power

75 RAVDD I Power

77 JASELR I CMOS Note2 )

78 JASELT I CMOS Note2 )

80 RCLK2 O CMOS ≤15pF

81 RNEG2 O CMOS ≤15pF

82 RPOS2 O CMOS ≤15pF

83 LOS2 I CMOS ≤15pF

85 TCLK2 I CMOS

86 TNEG2 I CMOS

87 TPOS2 I CMOS

89 DAVSS1 I Power

90 DVDD I Power

91 DVSS I Power

93 TAVSS2 I Power

94 TAVDD2 I Power

97 AIS2 I CMOS Note2 )

98 DFM2 O CMOS ≤15pF

99 RCLK1 O CMOS ≤15pF

101 RNEG1 O CMOS ≤15pF

102 RPOS1 O CMOS ≤15pF

103 LOS1 O CMOS ≤15pF

104 TCLK1 I CMOS

105 TNEG1 I CMOS

106 TPOS1 I CMOS

107 AIS1 I CMOS Note2 )

108 DFM1 O CMOS ≤15pF

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /16 Pin # Pin Name I/O Pin Type AC Load DC Load Comments 109 NC

110 AVSS1 I Power

111 TRING1 O Analog driver output

112 TVDD1 I Power

113 TVSS1 I Power

114 TTIP1 O Analog driver output

115 RLOOP1 I CMOS Note2 )

116 LLOOP1 I CMOS Note2 )

119 AVSS2 I Power

120 TRING2 O Analog driver output

121 TVDD2 I Power

122 TVSS2 I Power

123 TTIP2 O Analog driver output

124 RLOOP2 I CMOS Note2 )

125 LLOOP2 I CMOS Note2 )

127 AVSS3 I Power

128 TRING3 O Analog driver output

129 TVDD3 I Power

130 TVSS3 I Power

131 TTIP3 O Analog driver output

132 RLOOP3 I CMOS Note2 )

133 LLOOP3 I CMOS Note2 )

135 AVSS4 I Power

136 TRING4 O Analog driver output

137 TVDD4 I Power

138 TVSS4 I Power

139 TTIP4 O Analog driver output

140 RLOOP4 I CMOS Note2 )

141 LLOOP4 I CMOS Note2 )

Note1 )Should be connected to VSS externally. Note2 )Should be connected to VSS externally in host mode. Note3 )All NC pins are recommended to connected to VSS externally.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /17 PIN DESCRIPTIONS Pin Name I/O Function Comments T1 Transceiver TTIP1-4 TRING1-4 O O Transmit Tip/Ring Output pins Bipolar output over transmit transformer TPOS1-4 TNEG1-4 I I Transmit Positive/Negative Data Input pins Input on the falling edge of TCLK TCLK1-4 I Transmit Clock Input pins RTIP1-4 RRING1-4 I I Receive Tip/Ring Input pins Bipolar Input over receive transformer RPOS1-4 RNEG1-4 O O Receive Positive/Negative Data Output pins Output on the rising/falling edge of RCLK (determined by CLKE pin) RCLK1-4 O Receive Clock Output recovered from receive data input pins RLOOP1-4 I Remote Loopback Control input pins Note1) LLOOP1-4 I Local Loopback Control input pins Note1) LENG01-04 I Line Length Control 0 input pins Note1) LENG11-14 I Line Length Control 1 input pins Note1) LENG21-24 I Line Length Control 2 input pins Note1) AIS1-4 I Transmit AIS Enable input pins Note1) AIS1SEL I Transmit All Ones/Zero Selection input pins when AIS is enabled Note1) JASELR I Jitter Attenuator Select input pin, placed at Receiver Note1) JASELT I Jitter Attenuator Select input pin, placed at Transmitter Note1) DFM1-4 O Driver Failure Monitor output pins LOS1-4 O Loss of signal output pins Output “high” when detect loss of signal LOSx output is not masked by MLOSx register. TVDD1-4 Positive Power Supply for the Transmit Driver TVSS1-4 Negative Power Supply for the Transmit Driver AVSS1-4 Analog ground. Common Block MCLK I 1.544MHz or 24.704MHz External Reference Clock input pin LOMC O Loss of master clock output pin. Output “high” when detect loss of master clock LOMC output is not masked by MLOMC register. Note1) AS(ALE) I Address Select(Address Latch Enable) input pin Note2) INT O Interrupt Output pin(PMOS open drain), Active High, INT output goes “high” when the alarm is reported to any one of LOSx, LOTCx or LOMC registers. This pin can be masked by MLOSx, MLOTCx or MLOMC registers. Note2) DS(RD) I Data Strobe(Read Enable) input pin Note2) R/W (WR) I Read/Write(Write Enable) input pin Note2)

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /18 Pin Name I/O Function Comments Common block (Cont.) CS I Chip Select input pin Note2) BTS I Bus Type Select input pin BTS= ”H” : Motorola Mode BTS= ”L” : Intel Mode Note2) AD0-AD7 I/O Address/Data Input/Output pins Used for read/write internal registers. Note2) MCLKSEL I MCLK Select input pin CLKSEL= ”H”:1.544MHz CLKSEL= ”L”:24.704MHz HWMODE I Hardware/ Host Mode Select input pin HWMODE= ”H”: Hardware Mode HWMODE= ”L”: Host Mode SEL5V I 5.0V /3.3V VDD Select input pin SEL5V= ”H”: 5V operation SEL 5V=”L”: 3.3V operation CLKE I RCLK clock edge select input pin RESET I Reset Input pin Active “High” input pulse over 200ns initializes the internal circuit and forces RPOSx/RNEGx output “low” and LOSx output “high”. TEST1 - 8 I Factory Use. Should be connected to “VSS” externally. TAVDD1,2 Positive Power Supply for the analog circuitry in the transmitters TAVSS1,2 Negative Power Supply for the analog circuitry in the transmitters RAVDD Positive Power Supply for the digital circuitry in the transmitters RAVSS Negative Power Supply for the digital circuitry in the transmitters DVDD Positive Power Supply for Digital DVSS Negative Power Supply for Digital DAVSS1,2 Ground for Digital IOVDD Positive Power Supply for I/O IOVSS Negative Power Supply for I/O BVDD Positive Power Supply for Reference Circuit BVSS Negative Power Supply for Reference Circuit PVDD Positive Power Supply for PLL PVSS Negative Power Supply for PLL BGREF Bandgap Reference Output pin 12kΩ ±1% external register should be connected across this pin and VSS. Note1) Hardware Mode Note2) Host Mode

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /19 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Typ Max Units Conditions DC Supply VDD -0.3 6.5 V VIN1 -0.3 VDD+0.3 V Apply to except for RTIPx, RRINGx Input Voltage VIN2 -3.2 VDD+0.3 V Apply to RTIPx,RRINGx Input Current IIN 10 mA All Pins Storage Temperature Tstg -55 130 °C RECOMMENDED OPERATING COMDITIONS Parameter Symbol min typ max Units Conditions DC Supply 1 V+1 3.135 3.3 3.465 V 3.3V± 5% DC Supply 2 V+2 4.75 5.0 5.25 V 5.0V± 5% Ambient Operating Temperature Ta -40 25 +85 °C

ELECTRICAL CHARACTERISTICS

Parameter Symbol min typ max Units Conditions Power Consumption(/ch) PD 106 260 mW Note1 Power Consumption(/ch) PD 130 280 mW Note2 Digital High-Level Output Voltage VOH 0.9VDD V IOH=-500µA Digital Low-Level Output Voltage VOL 0.4 V IOL=500µA Digital High-Level Input Voltage VIH 0.7VDD V Digital Low-Level Input Voltage VIL 0.3VDD V Input Leak Current Ii 10 µA Output Current (VOH=VDD-0.5) IOH 2.0 mA INT pin PMOS Open Drain Note 1: typ: 50% mark, Room temp., VDD 3.3V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD in all range, line length 655feet, Load 100ohm Any other loads (ex. external pull up register, etc.) is not included except lines. Note 2: typ: 50% mark, Room temp., VDD 5.0V, line length 399feet, Load 100ohm max: 100% mark, Temp./VDD in all range, line length 655feet, Load 100ohm Any other loads (ex. external pull up register, etc.) is not included except lines.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /110 RECEIVER Receiver characteristics are guaranteed under the conditions shown below. VDD=3.3V±5% or 5.0V±5%, VSS=0V, GND=0V, Ta=-40 - 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm, AMI input data rate:1.544bps±130ppm(reference input level: 3V0p±20%) Parameter Symbol Min Typ Max Units Conditions Sensitivity -6 dB Note 1 Loss of Signal Threshold 0.35 0.5 0.7 V0p Note 2 Jitter Tolerance GR-499 CategoryI,II, ATT TR 62411 Consecutive Zeros before Loss of Signal 170 175 180 Note 3 Input Impedance 20 kohm Note 4 Note 1: Relative value to the reference level. Compare at 772kHz with all mark pattern. Note 2: Level at the line side of transformer. Loss of signal is logical OR between an analog loss of signal, which monitors input level , and a digital loss of signal , which check s recovered data stream. Note 3: The device will tolerate consecutive zeros until loss of signal is reported with QRSS (PN20 Modified) pattern. Note 4: It is not subject to be tested for the production. Guaranteed by design. JITTER TOLERANCE JITTER TOLERANCE 0.1 100 1000 1 10 100 1000 10000 100000 Jiiter Frequency(Hz) Jitter Amplitude(UIpp) TR62411

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /111 TRANSMITTER Transmitter characteristics are guaranteed under the conditions shown below. VDD=3.3V±5% or 5.0V±5%, VSS=0V, GND=0V, Ta=-40 - 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm Parameter Symbol Min Typ Max Units Conditions Output Pulse Shape GR-499,Note1 Output Pulse Amplitude 2.5 3.0 3.5 V0p Note1, Note2 Output Pulse Imbalance 0.4 dB Output Jitter 10Hz-8kHz 10Hz-40kHz 8kHz-40kHz Broad Band 0. 02 0.025 0.025 0.05 UIpp Power Levels @772kHz 12.6 15 17.9 dBm Note3 Power Levels @1.544MHz -29 dB Note3, Note4 Consecutive Zeros before DPM Alarm 320 Note 1: Measured at the DSX terminated with 100ohm. Note 2: Turns Ratio and DCR of transmission transformer are recommended value. Note 3: Measured in a 2kHz bandwidth about the specified frequency. Transmit all mark pattern. Note 4: Referenced to the power at 772kHz. ISOLATED PULSE MASK (GR-499) Normalized Amplitude -0.5 0.5 1.5 Time, in Unit Intervals

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /112 JITTER ATTENUATOR Jitter Attenuator characteristics are guaranteed under the conditions shown below. VDD=3.3V±5% or 5.0V±5%, VSS=0V, GND=0V, Ta=-40 - 85°C, MCLK frequency: 1.544MHz±100ppm, 24.704MHz±100ppm Parameter Symbol Min Typ Max Units Conditions Jitter attenuator curve corner frequency 6 Hz Jitter attenuation @ 10kHz 50 dB Input Jitter: 1 UIpp Attenuator input jitter tolerance before FIFO overflow/underflow protection

43 UIpp

Intrinsic Jitter 0.03 0.06 UIpp

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /113 AC CHARACTERISTICS(Clock/Data) Parameter Symbol Min Typ Max Units Conditions Clock Frequency MCLK1 MCLK2 fci1 fci2 1.543846 24.70153 1. 544000 24.70400 1.544154 24.70647 MHz ±100ppm Note 1 MCLK1 324 ns Refer to Fig.4 1.544MHz Clock Pulse Width MCLK2 tpwhi tpwli 20 ns Refer to Fig.4 24.704MHz Clock Pulse Width TCLK tpwhi tpwli 324 ns Refer to Fig.2 Clock Pulse Width RCLK tpwho tpwlo 324 ns Refer to Fig.1 Note 3 Duty Cycle RCLK TCLK 50 % Note 2 Note 3 Setup/Hold Time RCLK RPOS RNEG tsu1 th1 150 ns Refer to Fig.1 Setup/Hold Time TCLK TPOS TNEG tsu2 th2 50 ns Refer to Fig.2 Rise Time RCLK, TCLK RPOS, TOPS RNEG, TNEG tr 50 ns Refer to Fig.3 Note3 Fall Time RCLK, TCLK RPOS, TPOS RNEG, TNEG tf 50 ns Refer to Fig.3 Note3 Note 1: All AK2540 specifications are to be within the limit with ±100ppm MCLK. However, MCLK needs to be within ±32ppm range in order to transmit AIS of ±32 ppm accuracy during the loss of TCLK. Note 2: Duty Cycle:(tpwho/( tpwho + tpwlo)) × 100% Note 3: Drive 15pF Load Capacitance

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /114 When CLKE = 1 When CLKE=0 Fig. 1 Receiver Timing Fig. 2 Transmitter Timing Fig. 3 Rise and Fall Times (RCLK,RPOS,RNEG,TCLK,TPOS,TNEG,) Fig.4 Master Clock Timing tr tf 10% 10% 90% 90% tsut tht tpwhi tpwli 50% 50%50% 50% TCLK TPOS/TNEG tsur thr 50% 50% tpwho tpwlo tsur thr RCLK RPOS/RNEG 50%50% 50% 50% tpwhi tpwli MCLK 50%50% 50%

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /115 AC CHARACTERISTICS(Parallel Port) Parameter Symbol Min Typ Max Units Conditions Motrola Mode Address Setup Time t1 10 - - ns Address Hold Time t2 10 - - ns AS→ DS Delay Time t3 20 - - ns DS→ AS Delay Time t4 20 - - ns Read Data Delay Time t5 - - 40 ns Read Data Hold Time t6 - - 20 ns R/W Setup Time t7 10 - - ns R/W Hold Time t8 10 - - ns CS Setup Time t9 10 - - ns CS Hold Time t10 15 - - ns Write Data Setup Time t11 40 - - ns Write Data Hold Time t12 20 - - ns DS Pulse Width t13 100 - - ns AS Pulse Width t14 20 - - ns Address Invalid→ DS Delay Time t15 10 - - ns Intel Mode Address Setup Time t21 10 - - ns Address Hold Time t22 10 - - ns ALE→ WR Delay Time t23 20 - - ns WR→ ALE Delay Time t24 20 - - ns RD→ ALE Delay Time t25 20 - - ns Read Data Delay Time t26 - - 40 ns Read Data Hold Time t27 - - 20 ns CS Setup Time t28 10 - - ns CS Hold Time t29 15 - - ns Write Data Setup Time t30 40 - - ns Write Data Hold Time t31 20 - - ns RD Pulse Width t32 100 - - ns WR Pulse Width t33 100 - - ns ALE Pulse Width t34 20 - - ns Address Invalid→ RD Delay Time t35 10 - - ns Notes: CL= 50pF on AD0-AD7. All of the timing is specified at 50%VDD.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /116 Motorola Mode(READ) CS DS AS AD7-0 R/W Address Data t1 t2 t13 t9 t10 CS DS AS AD7-0 R/W Address Data t1 t2 t13 t12 t9 t10 Motorola Mode(WRITE) t14 t11 t14 t15

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /117 Intel Mode(READ) CS WR ALE AD7-0 RD Address Data t21 t22 t34 t26 t27 t28 t29 CS WR ALE AD7-0 RD Address Data t21 t22 t31 t28 t29 t30 Intel Mode(WRITE) t33 t24 t32 t25 t34 t23 t35

after through parallel interface. registers and hard flag pins show the current status regardless of the mask register setting. Length control pins LENG0x through LENG2x as shown in Table 1. Table 1. Line Length Control

Attenuators are to be placed at the same place in channel 1 through channel 4. Table 2. Jitter Attenuator Place Selection Table 3. AIS Control

Local Loopback (LLOOP) in channel x is selected when LLOOPx is “high” and RLOOPx is “low”. and TOPS/TNEG) are looped back and output at RCLK and RPOS/RNEG. The transmitter circuits are unaffected by LLOOP. Remote Loopback (RLOOP) in channel x is selected when RLOOPx is “high” and LLOOPx is “low”. by the RLOOP and continue to output the data and clock signals received from the line. Table 4. Loopback mode Selection current status regardless of the MDPMx status. DPMx returns to “low”, when a mark is detected. However, DPMx is to be kept “high” for 320 TCLK cycle after the first detection of the event.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /121 Driver Failure Monitor (Hardware Mode and Host Mode) Driver Failure Monitor asserts the detection of consecutive space or line short. When DPMx is set “high” or line short circuit in channel x is detecte d, DFMx(Driver Failure Monitor) register is set “high” and DFMx pin becomes “high”. INT pin becomes “high” when DFMx is set “high” if MDFMx is “low”. DFMx registers and DFMx pins represent the current status regardless of the MDFMx status. Loss of signal (Hardware Mode and Host Mode) The receiver will indicate loss of signal upon receiving 175 consecutive zeros (DLOS) or detecting input level being below the threshold (ALOS). LOSx returns to “low” when the received signal returns to 12.5% ones density and not including 100 consecutive zeros. (GR-820) When Loss of Signal is detected in channel x , LOSx register is set “high” and LOSx pin becomes “high”. When LOSx is set “high”, interrupt will be issued on INT pin if MLOSx is “low”. LOSx pin becomes high regardless of MLOSx status. MLOSx is active-high and masks LOSx interrupt. LOSx register s and LOSx pins represent the current status of received signal regardless of the MLOSx status. There are also ALOSx registers and the current status of each channel is available. Loss of TCLK (Host Mode Only) Loss of TCLKx is reported by setting LOTCx “high”. When LOTCx is set “high”, INT output becomes “high” if MLOTCx is “low”. MLOTCx is active-high and masks LOTCx interrupt. LOTCx represents the current status of TCLKx and can be read regardless of MLOTCx status. When Loss of TCLKx is detected, TTIPx/TRINGx will be forced to “0”(except Remote loopback and AIS), and AIS in channel x is sent synchronized with MCLK if AISx is selected. INT_LOMC output (Hardware Mode and Host Mode) In Host Mode, INT_LOMC(Interrupt Output) output becomes “high” when the alarm is reported at any one of ALOSx, LOSx, LOTCx, DFMx or DPMx registers. INT_LOMC pin can be masked by MALOSx, MLOSx, MLOTCx, MDFM or MDPM registers. In Hardware Mode, INT_LOMC pin assert LOMC(Loss of MCLK alarm).

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /122 REGISTER DESCRIPTIONS REGISTER MAP *A7-A4=”0” Address Function A3 A2 A1 A0 Bit7 <AD7> Bit6 <AD6> Bit5 <AD5> Bit4 <AD4> Bit3 <AD3> Bit2 <AD2> Bit1 <AD1> Bit0 <AD0> Status Register (READ ONLY) 0 0 0 0 DPM4 (0) DPM3 (0) DPM2 (0) DPM1 (0) DFM4 (0) DFM3 (0) DFM2 (0) DFM1 (0) 0 0 0 1 LOTC4 (1) LOTC3 (1) LOTC2 (1) LOTC1 (1) - - - LOMC (1) 0 0 1 0 ALOS4 (1) ALOS3 (1) ALOS2 (1) ALOS1 (1) LOS4 (1) LOS3 (1) LOS2 (1) LOS1 (1) Mask Control Register (WRITE/READ) 0 0 1 1 MDPM4 (1) MDPM3 (1) MDPM2 (1) MDPM1 (1) MDFM4 (1) MDFM3 (1) MDFM2 (1) MDFM1 (1) 0 1 0 0 MLOTC4 (1) MLOTC3 (1) MLOTC2 (1) MLOTC1 (1) - - - - 0 1 0 1 MALOS4 (1) MALOS3 (1) MALOS2 (1) MALOS1 (1) MLOS4 (1) MLOS3 (1) MLOS2 (1) MLOS1 (1) 0 1 1 0 MSK4 (1) MSK3 (1) MSK2 (1) MSK1 (1) - - - MLOMC (1) Channel Control Register (WRITE/READ) 0 1 1 1 LENG21 (0) LENG11 (0) LENG01 (1) RLOOP1 (0) LLOOP1 (0) AIS1 (0) - PD1 (1) 1 0 0 0 LENG22 (0) LENG12 (0) LENG02 (1) RLOOP2 (0) LLOOP2 (0) AIS2 (0) - PD2 (1) 1 0 0 1 LENG23 (0) LENG13 (0) LENG03 (1) RLOOP3 (0) LLOOP3 (0) AIS3 (0) - PD3 (1) 1 0 1 0 LENG24 (0) LENG14 (0) LENG04 (1) RLOOP4 (0) LLOOP4 (0) AIS4 (0) - PD4 (1) Global Control Register (WRITE/READ) 1 0 1 1 JASELR (0) JASELT (0) POL (1) RDEN (0) AIS1SEL (1) - - - * The other addresses are reserved. * Initial value is in ( ). * “<>” shows I/O pin name. Address A0-A3 should be input via AD0-AD3 pins.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /123 STATUS REGISTER Symbol Description LOSx (x=1 to 4) Loss of signal alarm for channel x. Read only register. When the loss of signal is detected, LOSx is set High. LOTCx (x=1 to 4) Loss of TCLK alarm for channel x. Read only register. When the loss of TCLKx is detected, LOTCx is set High. DPMx (x=1 to 4) Driver Performance Monitor alarm for channel x. Read only register. When 320 bits of consecutive space is detected in channel x , DPMx is set high. DFMx (x=1 to 4) Driver Failure Monitor alarm for channel x. Read only register. When DPM or short circuit is detected in channel x , DFMx is set high. ALOSx (x=1 to 4) Analog loss of signal alarm for channel x. Read only register. When the analog loss of signal is detected, ALOSx is set High. LOMC Loss of MCLK alarm. Read only register. When the loss of MCLK is detected, LOMC is set High. MASK CONTROL REGISTER Symbol Description MLOSx (x=1 to 4) Mask loss of signal alarm for channel x (LOSx). MLOSx is active-high and prevents LOSx from setting INT output “high”. LOSx register can be read regardless of the MLOSx status. Initial value is “high”. MLOTCx (x=1 to 4) Mask loss of TCLK alarm for channel x (LOTCx). MLOTCx is active high and prevent s LOTCx from setting INT output “high”. LOTCx register can be read regardless of the MLOTCx status. Initial value is “high”. MDPMx (x=1 to 4) Mask DPM alarm for channel x (DPMx). MDPMx is active high Initial value is “high”. MDFMx (x=1 to 4) Mask DFM alarm for channel x (DFMx). MDFMx is active high Initial value is “high”. MSKx (x=1 to 4) MSKx is active-high and prevent s LOSx, LOTCx, DFMx and DPMx in channel x from setting INT output “high”. Initial value is “high”. MALOSx (x=1 to 4) Mask analog loss of signal alarm for channel x (ALOSx). MALOSx is active-high and prevent s ALOSx from setting INT output “high”. ALOSx register can be read regardless of the MALOSx status. Initial value is “high”. MLOMC Mask loss of MCLK alarm (LOMC). MLOMC is active high and prevents LOMC from setting INT output “high”. LOMC register can be read regardless of the MLOMC status. Initial value is “high”.

register as shown below in Table 5. registers as shown below in Table 6. AISx AISx is active-high to transmit AIS in the corresponding channel. TTIPx and TRINGx goes “low”. LOSx goes “high” in power down mode. Jitter Attenuator is placed by these resisters as shown is Table 7. POL This register as shown in Table 8 controls TIP/RING output polarity. transmitted as AIS when AIS1SEL is “low”. Table 5. Line Length Control

Table 6. Loopback mode Selection Table 7. Jitter Attenuator Place Selection Table 8. TIPx/RINGx Polarity Control

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /126 OUTPUT CONTROL * : don’t care LOS: LOSx output and LOSx register Reset, Loss of MCLK, Power down (Host Mode) LoopbackRESET MCLK PD Local Remote POL RDEN CLKE TTIP TRING RCLK RPOS RNEG LOS DFM 1 * * * * * * * High- Z ( Note1 ) 0 0 1 0 0 loss * * * 1 * * 0 0 0 1 0 0 loss * * * 0 * * 0 0 1 1 0 0 clocked 1 * * 1 0 * High-Z ( Note1 ) 0 0 1 0 0 clocked 1 * * 1 1 0 High-Z ( Note1 ) 0 0 1 0 0 clocked 1 * * 1 1 1 High-Z ( Note1 ) 1 0 1 0 0 clocked 1 * * 0 0 * High-Z ( Note1 ) 0 1 1 0 0 clocked 1 * * 0 1 0 High-Z ( Note1 ) 0 1 1 0 0 clocked 1 * * 0 1 1 High-Z ( Note1 ) 1 1 1 0 Reset, Loss of MCLK (Hardware Mode) LoopbackRESET MCLK Local Remote CLKE TTIP TRING RCLK RPOS RNEG LOS DFM 1 * * * * 0 0 0 1 0 0 loss * * * 0 0 0 1 0 In Hardware Mode, POL is fixed to ”1” and RDEN is fixed to ”0”.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /127 Normal Operation(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked TPOS TNEG RCLK RTIP RRING 0 active 1 0 clocked loss TPOS TNEG 0 0 1 active 1 * loss clocked 0 RCLK RTIP RRING 0 0 1 0 loss loss 0 0 0 1 0 1 1 clocked loss TPOS TNEG RCLK RTIP RRING 1 active 1 1 loss loss 0 RCLK RTIP RRING 1 0 0 * clocked clocked TPOS TNEG RCLK RTIP RRING 0 active 0 0 clocked loss TPOS TNEG 0 1 1 active 0 * loss clocked 0 RCLK RTIP RRING 0 0 0 0 loss loss 0 0 1 1 0 0 1 clocked loss TPOS TNEG RCLK RTIP RRING 1 active 0 1 loss loss 0 RCLK RTIP RRING 1 0 Normal Operation: Transmit all space (RESET=0, AIS=1,AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked 0 RCLK RTIP RRING 0 0 1 0 clocked loss 0 0 0 1 0 1 * loss clocked 0 RCLK RTIP RRING 0 0 1 0 loss loss 0 0 0 1 0 1 1 clocked loss 0 RCLK RTIP RRING 1 0 1 1 loss loss 0 RCLK RTIP RRING 1 0 0 * clocked clocked 0 RCLK RTIP RRING 0 0 0 0 clocked loss 0 0 1 1 0 0 * loss clocked 0 RCLK RTIP RRING 0 0 0 0 loss loss 0 0 1 1 0 0 1 clocked loss 0 RCLK RTIP RRING 1 0 0 1 loss loss 0 RCLK RTIP RRING 1 0

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /128 Normal Operation: Transmit all mark (RESET=0, AIS=1,AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked All Mark RCLK RTIP RRING 0 active 1 0 clocked loss All Mark 0 0 1 active 1 * loss clocked All Mark ( Note2 ) RCLK RTIP RRING 0 active 1 0 loss loss All Mark ( Note2 ) 0 0 1 active 1 1 clocked loss All Mark RCLK RTIP RRING 1 active 1 1 loss loss All Mark ( Note2 ) RCLK RTIP RRING 1 active 0 * clocked clocked All Mark RCLK RTIP RRING 0 active 0 0 clocked loss All Mark 0 1 1 active 0 * loss clocked All Mark ( Note2 ) RCLK RTIP RRING 0 active 0 0 loss loss All Mark ( Note2 ) 0 1 1 active 0 1 clocked loss All Mark RCLK RTIP RRING 1 active 0 1 loss loss All Mark ( Note2 ) RCLK RTIP RRING 1 active Remote Loopback (RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * * clocked RTIP RRING RCLK RTIP RRING 0 active 1 0 * loss RTIP RRING 0 0 1 active 1 1 * loss RTIP RRING RCLK RTIP RRING 1 active 0 * * clocked RTIP RRING RCLK RTIP RRING 0 active 0 0 * loss RTIP RRING 0 1 1 active 0 1 * loss RTIP RRING RCLK RTIP RRING 1 active

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /129 Remote Loopback: Transmit all space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * * clocked 0 RCLK RTIP RRING 0 0 1 0 * loss 0 0 0 1 0 1 1 * loss 0 RCLK RTIP RRING 1 0 0 * * clocked 0 RCLK RTIP RRING 0 0 0 0 * loss 0 0 1 1 0 0 1 * loss 0 RCLK RTIP RRING 1 0 Remote Loopback: Transmit all mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=0, RLOOP=1) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * * clocked All Mark RCLK RTIP RRING 0 active 1 0 * loss All Mark 0 0 1 active 1 1 * loss All Mark RCLK RTIP RRING 1 active 0 * * clocked All Mark RCLK RTIP RRING 0 active 0 0 * loss All Mark 0 1 1 active 0 1 * loss All Mark RCLK RTIP RRING 1 active Local Loopback(RESET=0, AIS=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked TPOS TNEG TCLK ( Note4 ) TPOS TNEG 0 active 1 * clocked loss TPOS TNEG TCLK ( Note4 ) TPOS TNEG 1 active 1 * loss clocked 0 0/1 ( Note3 ) 0 0 0 1 * loss loss 0 0 /1 ( Note3 ) 0 1 0 0 * clocked clocked TPOS TNEG TCLK ( Note4 ) TPOS TNEG 0 active 0 * clocked loss TPOS TNEG TCLK ( Note4 ) TPOS TNEG 1 active 0 * loss clocked 0 0/1 ( Note3 ) 0 0 0 0 * loss loss 0 0/1 ( Note3 ) 0 1 0

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /130 Local Loopback: Transmit all space (RESET=0, AIS=1, AIS1SEL=0, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked 0 TCLK ( Note4 ) TPOS TNEG 0 0 1 * clocked loss 0 TCLK ( Note4 ) TPOS TNEG 1 0 1 * loss clocked 0 0/1 ( Note3 ) 0 0 0 1 * loss loss 0 0/1 ( Note3 ) 0 1 0 0 * clocked clocked 0 TCLK ( Note4 ) TPOS TNEG 0 0 0 * clocked loss 0 TCLK ( Note4 ) TPOS TNEG 1 0 0 * loss clocked 0 0/1 ( Note3 ) 1 0 0 0 * loss loss 0 0/1 ( Note3 ) 1 1 0 Local Loopback: Transmit all mark (RESET=0, AIS=1, AIS1SEL=1, MCLK:clocked, PD=0, LLOOP=1, RLOOP=0) POL RDEN TCLK Receive signal TTIP TRING RCLK RPOS RNEG LOS DFM 1 * clocked clocked All Mark TCLK ( Note4 ) TPOS TNEG 0 active 1 * clocked loss All Mark TCLK ( Note4 ) TPOS TNEG 1 active 1 * loss clocked All Mark ( Note2 ) ( Note3 ) 0 0 active 1 * loss loss All Mark ( Note2 ) ( Note3 ) 0 1 active 0 * clocked clocked All Mark TCLK ( Note4 ) TPOS TNEG 0 active 0 * clocked loss All Mark TCLK ( Note4 ) TPOS TNEG 1 active 0 * loss clocked All Mark ( Note2 ) ( Note3 ) 1 0 active 0 * loss loss All Mark ( Note2 ) ( Note3 ) 1 1 active Note1) The impedance between TTIP and TRING is 30kohm(typ) Note2) Transmit signal synchronize with MCLK Note3) When CLKE is “1”, RCLK is fixed to “1”. Note4) The phase of the TCLK satisfy receive output timing.

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /131 RECOMMENDED EXTERNAL CIRCUITS Transmit Circuit Received Circuit Recommended Transformer Specification VDD = 3.3V DCR (Max) Turns Ratio (Typ) Primary Inductance (Min) Leakage Inductance (Max) Interwinding Capacitance (Max) pri sec Tx 1:2 1.5mH 0.3uF 30pF 0.6ohms 0.6ohms Rx 1:2(CT) 1.5mH 0.3uF 30pF 0.6ohms 0.6ohms VDD = 5V DCR (Max) Turns Ratio (Typ) Primary Inductance (Min) Leakage Inductance (Max) Interwinding Capacitance (Max) pri sec AK2540 TTIPx TRINGx C1=0.47µF R1=R2= 50ohms (3.3V) 154ohms (5V) Rp=100ohms(Protection resistance, Example value) VDD VDD 1:2 (3.3V) 1:1.14 (5V) AK2540 RTIPx RRINGx Rp Rp 1:1 (3.3V) 1:0.57 (5V)

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /132 Reference current circuit To determine input reference current, connect 12kohm±1% resistor. R1 is recommended to connect to AK2540 as short as possible to avoid noise. Power Supply To attenuate the power supply noise, connect capacitors between VDD and VSS respectively. The value of the capacitance AK2540 need depend on the condition of the power supply line. Please decide the value of the capacitance after your evaluation. C1 is recommended to connect to AK2540 as short as possible to avoid noise. Pin name C1 RAVDD-RAVSS, BVDD-BVSS, TAVDD1-TAVSS1, TAVDD2-TAVSS2 1uF TVDD1-TVSS1, TVDD2-TVSS2, TVDD3-TVSS3, TVDD4-TVSS4, IOVDD-IOVSS, DVDD-DVSS, PVDD-PVSS 0.01uF Recommended Transformers Selection Power Supply Turns Ratio Manufacturer Part Number Description TDK WBTT-0425B Single, SMT,1.5kV3.3V Operation 1:1.14 Pulse Engineering T1104 Octal, SMT,1.5kV TDK WBTT-0425 Single, SMT,1.5kV Pulse Engineering T1105 Octal, SMT,1.5kV Operation 1:2 JPC 4101 Single, SMT,1.5kV BGREF AK2540 R1=12kohm±1% VDDAK2540

ASAHI KASEI [AK25 40] MS0012-E-00 2000 /133 PACKAGE 144pin LQFP Outline Dimensions 22.0 1 36 73108 109 144 20.0 0.50 0.20 0 ∼ 10 ° 0.17 ±0.04 0.07 22.0 20.0

1.70 Max

1.40 0.50 ±0.1 0.10 0.10 0.10 M AK2540 XXXXXXX JAPAN