AK2500

AK2500B AKM | Alldatasheet

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ASAHI KASEI [AK2500 B] MS0005- E - 00 - 1 - 199 9 /12 AK2500B DS3/STS-1 Analog Line Receiver GENERAL DESCRIPTION The AK2500B is a DSP based line receiver. It provides the analog receive line interface functions for a 44.736 MHz DS3 or 51.84 MHz STS-1 interface. The device operates from a single +3.3 Volt supply and is transparent to the framing format. PACKAGE - 24 pin SOP FEATURE - “ Robust ” DSP based line receiver - AK2500B Provides Complete Analog Line Receiver for DS3 and STS-1 Applications - Pr ovides Line Equalization, and Clock and Data Recovery Functions

APPLICATIONS

• Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX- 3 cross connect. - Interfacing customer premises equipment to a line. BLOCK DIAGRAM GAIN and LINE EQUALIZATION DATA RECOVERY LOS LOGIC CLOCK RECOVERY RPDATA RNDATA RCLK RLOS RIN RLOL VDDA VDDD VDDC VSSC VSSD VSSA TREF BREF EXCLK LOSTHR IREF MODE2 MODE1 RESET

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 2 - 199 9 /12 PIN LOCATION 24IREF LOSTHR RLOL RIN VDDA VDDA RESET BREF TREF VSSA VSSD RLOS MODE2 MODE1 VSSA VSSA VSSC RPDATA RNDATA RCLK VDDC VDDA VDDD EXCLK AK2500B

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 3 - 199 9 /12 PIN CONDITION No. Pin Name I/O Pin Type Maximum AC load Minimum DC load Status on Reset Remarks

1 IREF O Analog Note 1

2 LOSTHR I Analog

3 RLOL O CMOS 15pF “ H ”

4 RIN I Analog Note 2

5 VDDA -

6 VDDA -

7 RESET I CMOS Note 3

8 B REF O Analog

9 T REF O Analog

1 2 RLOS O CMOS 15pF “ H ”

13 EXCLK I CMOS

14 VDDD -

15 VDDA -

16 VDDC -

17 RCLK O CMOS 15pF “ L ”

18 RNDATA O CMOS 15pF “ L ”

19 RPDATA O CMOS 15pF “ L ”

20 VSSC -

21 VSSA -

22 VSSA -

23 MODE1 I Analog

24 MODE2 I Analog

Note: 1 )External resister 4.9 kohm is connected between IREF and VSS. 2 )Input impedance of RIN is more than 5kohm. 3 )Pulled up to VDD with internal register. ( typical 50k ohm)

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 4 - 199 9 /12 PIN DESCRIPTION No. Pin Name I/O Function

1 IREF O

Current reference output determined by the external resister. External resistance 4.9 kohm (+/-1%) should be connected between this pin and VSSA.

2 LOSTHR I

Loss of Signal Threshold Control The voltage forced on this pin controls the input loss-of-signal threshold. Three settings are provided by forcing GND, VDD/2, or VDD at LOSTHR (see Table 6 ).

3 RLOL O

Active High alarm. If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High.

4 RIN I

Unbalanced analog receive input. The B3ZS receive signal is input to this pins. Data and clock are recovered and output on RPDATA, RNDATA and RCLK. Power Supply for the analog part. +3.3 volts . 7 RESET I Active low RESET. Pulled up to VDD with internal resister.

8 B R EF O

Bottom voltage reference level output. An external capacitor (0.1 uF±20%) should be connected between this pin and VSS A .

9 TREF O

Top voltage reference level output. An external capacitor (0.1 uF±20%) should be connected between this pin and VSS A . 1 0 VSSA - Ground for the analog part. 0 volts. 1 1 VSSD - Ground for the digital part. 0 volts. 1 2 RLOS O Receive Loss-of-Signal. This pin is set high on loss of the incoming signal at RIN.

13 EXCLK I

External Reference Clock. A valid DS3 or STS-1 clock must be provided at this input. The duty cycle of EXCLK, referenced to VDD/2 levels, must be 40% - 60%. The EXCLK frequency determines the operating frequency of the device. 14 VDDD - Power Supply for the digital part. +3.3 volts 15 VDDA - Power Supply for the analog part. +3.3 volts . 16 VDDC - Power Supply for the output buffer. +3.3 volts . 17 RCLK O Recovered Clock. 18 RNDATA O Receive Negative Data. 19 RPDATA O Receive Positive Data. 20 VSSC - Ground for the output buffer. 0 volts. Ground for the analog part. 0 volts.

23 MODE1 I

24 MODE2 I

Mode Control. Equalizer enable/bypass mode, Test mode are selectable as shown in Table 4.

The AK2500B provides the basic receiver functions of a high-speed line card as shown in Fig .7 . The receiver extracts data and clock from a B3ZS coded signal and outputs clock and synchronized data. Pulse characteristics are specified at the DSX-3. Table 1. DS3 Interface Specification Table 2. STS-1 Interface Specification attenuated by 0 - 450 feet of 728A cable. Table 3. DS3/STS-1 Cable Specification

(50mVpk - 1000mVpk for DS3/STS-1). Table 4. Mode Control

1 Equalizer Bypass

application of device power and error-free operation is typically 20 ms. Table 5. PLL Lock Acquisition Time

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 7 - 199 9 /12 Output Jitter Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Jitter Transfer Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Jitter Tolerance Compliance with GR-499-CORE, GR-253-CORE, ITU-T G.752, G.824 Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS (page.11). Loss-of-Lock Detection If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High. External Reference Clock An external reference clock EXCLK is used to set the frequency of the PLL. The frequency of EXCLK should be within the ideal clock ± 100ppm. Reset AK2500B/01B goes into RESET status if RESET input is low. O utput pins status is as follows during the low input on RESET . RLOS, RLOL : High RPDATA, RNDATA, RCLK : Low

Analog loss detector operates as follows.

• Analog loss detector monitors the peak level of the incoming signal.
• I f the peak level falls below Alarm set threshold as shown in Table 6 , output pins status is as follows.

Table 6. Analog Loss-of-Signal thresholds

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 9 - 199 9 /12 Digital Loss of Signal(DLOS) Digital loss detector operates as follows. - A digital loss detector monitors consecutive 0s and 1s density in recovered data. - RLOS is set high if 175 ± 5 consecutive 0s is detected. - RPDATA ,RNDATA are set low if ALOS is detected. - RLOS is set low if 33% 1 s density (58 1s in 175 consecutive bits) and no consecutive 100 bits of 0s are detected . 175 +/- 5 bits of consecutive 0s in the incoming data Normal Operation RCLK : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS : Low DLOS RCLK : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS : High ALOS RCLK : Recovered from EXCLK RPDATA : Low RNDATA : Low RLOS : High 175bits of the incoming data includes the following data. 1) 58bits of 1s (33% 1s density) 2) No 100bits of consecutive 0s Clear Alarm Threshold Level Set Alarm Threshold Level Peak level of the incoming data Peak level of the incoming data Fig. 2 Loss of Signal state diagram

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 10 - 199 9 /12 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units DC Supply (referenced to GND) (Note 1 ) V+ -0.3 4.6 V Input Voltage, Any Pin Vin GND-0.3 (V+)+0.3 V Input Current, Any Pin (Note 2 ) Iin - 10 mA Ambient Operating Temperature TA -40 85 °C Storage Temperature tstg -65 150 °C Power Dissipation PD - 1 W WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Note; 1.GND=VSSA=VSSC=VSSD=0V 2.Transient currents of up to 100 mA will not cause SCR latch up. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min Typ Max Units DC Supply (referenced to GND) V+ 3.0 3.3 3.6 V Ambient Operating Temperature TA -40 25 85 °C Supply Current: DS3 STS-1 IS PN20 PN20 100 105 110 mA mA EXCLK Frequency DS3 STS-1 44.736 - 100ppm 51.84 - 100ppm 44.736 51.84 44.736 + 100ppm 51.84 + 100ppm MHz MHz

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 11 - 199 9 /12 ANALOG SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V ±0.3V; GND = 0V) Parameter Condition Min Typ Max Units Jitter Transfer with repetitive 100 pattern (Note 4) 3dB Bandwidth Peaking 205 0.05 0.1 kHz dB Jitter Tolerance (Including cable loss) (Note 4, 5) 5kHz 10kHz 60kHz 300kHz

1 MHz

1.5 0.4 0.3 UIpp UIpp UIpp UIpp UIpp Signal Noise Immunity (Note 6) - 11 - dB Output Jitter with Jitter-Free Input (Note4) All one's pattern Repetitive 10 0 0 pattern 1.4 1.8 nsp-p nsp-p Output Clock Duty Cycle (Note4) 45 - 55 % Receiver Input Range 50 - 1000 mV pk DLOS detection 170 175 180 bits RIN to RPDATA Delay Time 8 bits Note; 4. Measured with repetitive input at nominal DSX-3 level with (V+)=3.3V, TA=25°C 5. Typical performance is shown in Fig. 3. 6. Measured with sinusoidal noise, peak amplitude of noise is 11dB down from peak amplitude of signal. The noise frequency is 22MHz ± 22kHz(DS3), 26MHz± 26kHz(STS-1). Fig. 3 Jitter Tolerance(STS-1) 0.05UIpp G.752 3.2k, 14UIpp GR-499 Category I GR-499 Category II 300k, 0.3UIpp 0.01 0.1 100 0.01 0.1 1 10 100 1000 10000 Jitter Frequency [kHz] Jitter Amplitude [UIpp] AK2500B Typical performance

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 12 - 199 9 /12 DS3 SWITCHING SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V ± 0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V + ) Parameter Symbol Min Typ Max Units RCLK Pulse Width (Note 10, 11) tpwh tpwl 10.1 10.1 11.177 11.177 12.2 12.2 ns ns EXCLK Duty Cycle ( EXCLK Min Rise/Fall time : 5ns) tpwh1 40 - 60 % Rise Time, RCLK (Note 11) tr - - 3.5 ns Fall Time, RCLK (Note 11) tf - - 3.5 ns Delay time from RCLK rising to RDATA (Note 12) tdcrd 0 - 3.5 ns Setup time from RCLK falling to RDATA (Note 12) tscrd 5.0 - - ns Hold time from RCLK falling to RDATA (Note 12) thcrd 8.4 - - ns STS-1 SWITCHING SPECIFICATIONS (TA = Tmin to Tmax; V+ = 3.3V ± 0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V + ) Parameter Symbol Min Typ Max Units RCLK Pulse Width (Note 11, 13) tpwh tpwl 8.7 8.7 9.645 9.645 10.6 10.6 ns ns EXCLK Duty Cycle ( EXCLK Min Rise/Fall time : 5ns) tpwh1/tpw 40 - 60 % Rise Time, RCLK (Note 11) tr - - 3.5 ns Fall Time, RCLK (Note 11) tf - - 3.5 ns Delay time from RCLK rising to RDATA (Note 12) tdcrd 0 - 3.5 ns Setup time from RCLK falling to RDATA (Note 12) tscrd 5.0 - - ns Hold time from RCLK falling to RDATA (Note 12) thcrd 7.0 - - ns Note; 10. Assumes PLL is locked to 44.736 MHz signal. 11. The sum of the pulse widths must always meet the frequency specifications. 12. At max load of 10 pF. 13. Assumes PLL is locked to 51.84 MHz signal. DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; V+ = 3.3V ±0.3V; GND = 0V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (Note 14) VIH (V+) x 0.7 - (V+) V Low-Level Input Voltage (Note 14) VIL GND - 0.5 V High-Level Output Voltage (Note 15,16) IOUT=-40 u A VOH (V+) x 0.8 - (V+) V Low-Level Output Voltage IOUT=1.6mA (Note 15), 0.4mA (Note 16) VOL GND - 0.4 V Input Leakage Current (Note 17) ± 10 u A Note; 14. Pins RESET 1 6. Pins RLOS, RLOL 15. Pins RCLK, RPDATA, RNDATA 17. Except RESET

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 13 - 199 9 /12 RCLK 10% 10% 90% 90% tr tf Fig. 4 Signal Rise and Fall Characteristics RCLK tpwh tpwl RPDATA RNDATA tdcrd tscrd thcrd Fig. 5 Recovered Clock and Data Switching Characteristics EXCLK tpwh1 tpw VDD/2 Fig. 6 EXCLK Duty Cycle Requirements

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 14 - 199 9 /12 Application Circuit Example Fig. 7 Application circuit example Board Layout Consideratons The recommended power supply de - coupling circuit is illustrated in Figure 7. Good quality high-frequency, low lead-inductance capacitors should be used. If the performance of Jitter Tolerance or S/X is not good, please try to use smaller de-coupling capacitors such as 0.01uF. These performances are affected by the power supply noise which depends on the customer ’ s board circuit and layout. All capacitors should be as close to the device as possible . 3.3V 5, 6, 15 10, 21, 22 0.1uF RPDATA RNDATA RCLK RLOS RIN RLOL VSSC VDDA VSSD VSSA VDDD VDDC BREF TREF EXCLK LOSTHR IREF MODE2 MODE1 RESET 0.1uF 0.1uF 0.01uF 75ohm B3ZS CODER/ DECODER FRAMER CONTROL LOGIC AK2500B COAX 0.1uF CLOCK SOURCE 8 9 1 4.9kohm 0.1uF

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 15 - 199 9 /12 Marking (1)Pin #1 indication (2)Date Code: 7digits XXXXYZZ (3)Marketing Code: AK2500B (4)Country of Origin: JAPAN (5)Asahi Kasei Logo AKM AK2500B XXXXYZZ JAPAN

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 16 - 199 9 /12 Outline Dimensions

ASAHI KASEI [AK2500 B] MS0005 - E -0 0 - 17 - 199 9 /12 IM PORTANT NOTICE

• These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability.
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