ADC0802 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • 80C48 and 80C80/85 Bus Compatible - No Interfacing Logic Required
  • Conversion Time < 100µs
  • Easy Interface to Most Microprocessors
  • Will Operate in a “Stand Alone” Mode
  • Differential Analog Voltage Inputs
  • Works with Bandgap Voltage References
  • TTL Compatible Inputs and Outputs
  • On-Chip Clock Generator
  • 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
  • No Zero-Adjust Required

Description

The ADC0802 family are CMOS 8-Bit, successive-approxi- mation A/D converters which use a modified potentiometric ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good common- mode-rejection and permits offsetting the analog zero-input- voltage value. In addition, the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution.

Ordering Information

PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE ( oC) PACKAGE PKG. NO ADC0802LCN ±1/2 LSB V REF /2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 ADC0802LCD ±3/4 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0802LD ±1 LSB -55 to 125 20 Ld CERDIP F20.3 ADC0803LCN ±1/2 LSB V REF /2 Adjusted for Correct Full Scale Reading 0 to 70 20 Ld PDIP E20.3 ADC0803LCD ±3/4 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0803LCWM ±1 LSB -40 to 85 20 Ld SOIC M20.3 ADC0803LD ±1 LSB -55 to 125 20 Ld CERDIP F20.3 ADC0804LCN ±1 LSB V REF /2 = 2.500VDC (No Adjustments) 0 to 70 20 Ld PDIP E20.3 ADC0804LCD ±1 LSB -40 to 85 20 Ld CERDIP F20.3 ADC0804LCWM ±1 LSB -40 to 85 20 Ld SOIC M20.3 Pinout ADC0802, ADC0803, ADC0804 (PDIP, CERDIP) TOP VIEW Typical Application Schematic WR RD CS CLK IN INTR VIN (-) VIN (+) DGND VREF /2 AGND V+ OR VREF CLK R DB 0 (LSB) DB 1 DB 2 DB 3 DB 4 DB 5 DB 6 DB 7 (MSB) WR RD CS DB 6 DB 7 INTR DB 3 DB 4 DB 5 DB 0 DB 1 DB 2 CLK IN CLK R VIN (-) VIN (+) DGND VREF /2 AGND ANY µPROCESSOR 8-BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE DIFF INPUTS 10K 150pF VREF /2 µP BUS +5V August 1997 ADC0802, ADC0803 ADC0804 8-Bit, Microprocessor- Compatible, A/D Converters File Number 3094.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

VIN (-) VIN (+) DGND VREF /2 AGND (VREF ) DAC VOUT COMP CLK GEN CLKS CLK A RESET START F/F LADDER AND DECODER SUCCESSIVE APPROX. REGISTER AND LATCH 8-BIT SHIFT REGISTER D RESET SET CONV .COMPL. THREE-STATE OUTPUT LATCHES DIGITAL OUTPUTS THREE-STATE CONTROL “1” = OUTPUT ENABLE DFF2 CLK A XFER G2 Q

8 X 1/f

R Q INTR F/F IF RESET = “0” D DFF1 Q D Q CLK B START CONVERSION MSB LSB Q “1” = RESET SHIFT REGISTER “0” = BUSY AND RESET STATE RESET READ SET3 CLK IN MSB CLK LSB INPUT PROTECTION FOR ALL LOGIC INPUTS INPUT TO INTERNAL BV = 30V CIRCUITS ADC0802, ADC0803, ADC0804

Absolute Maximum Ratings Thermal Information Operating Conditions Temperature Range Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications(Notes 1, 7) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS CONVERTER SPECIFICATIONS V+ = 5V, TA = 25oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0802 V REF /2 = 2.500V - - ±1/2 LSB ADC0803 V REF /2 Adjusted for Correct Full Scale Reading -- ±1/2 LSB ADC0804 V REF /2 = 2.500V - - ±1 LSB VREF /2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Ω Analog Input Voltage Range (Note 2) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/16 ±1/8 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB CONVERTER SPECIFICATIONS V+ = 5V, 0oC to 70oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0802 V REF /2 = 2.500V - - ±1/2 LSB ADC0803 V REF /2 Adjusted for Correct Full Scale Reading -- ±1/2 LSB ADC0804 V REF /2 = 2.500V - - ±1 LSB VREF /2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Ω Analog Input Voltage Range (Note 2) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/8 ±1/4 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB CONVERTER SPECIFICATIONS V+ = 5V, -25oC to 85oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0802 V REF /2 = 2.500V - - ±3/4 LSB ADC0803 V REF /2 Adjusted for Correct Full Scale Reading -- ±3/4 LSB ADC0804 V REF /2 = 2.500V - - ±1 LSB VREF /2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Ω Analog Input Voltage Range (Note 2) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/8 ±1/4 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/16 ±1/8 LSB ADC0802, ADC0803, ADC0804

CONVERTER SPECIFICATIONS V+ = 5V, -55oC to 125oC and fCLK = 640kHz, Unless Otherwise Specified Total Unadjusted Error ADC0802 V REF /2 = 2.500V - - ±1 LSB ADC0803 V REF /2 Adjusted for Correct Full Scale Reading -- ±1 LSB VREF /2 Input Resistance Input Resistance at Pin 9 1.0 1.3 - k Ω Analog Input Voltage Range (Note 2) GND-0.05 - (V+) + 0.05 V DC Common-Mode Rejection Over Analog Input Voltage Range - ±1/8 ±1/4 LSB Power Supply Sensitivity V+ = 5V ±10% Over Allowed Input Voltage Range - ±1/8 ±1/4 LSB AC TIMING SPECIFICATIONS V+ = 5V, and TA = 25oC, Unless Otherwise Specified Clock Frequency, fCLK V+ = 6V (Note 3) 100 640 1280 kHz V+ = 5V 100 640 800 kHz Clock Periods per Conversion (Note 4), t CONV 62 - 73 Clocks/Conv Conversion Rate In Free-Running Mode, CR INTR tied toWR withCS = 0V, fCLK = 640kHz - - 8888 Conv/s Width ofWR Input (Start Pulse Width), tW(WR)I CS = 0V (Note 5) 100 - - ns Access Time (Delay from Falling Edge ofRD to Output Data Valid), tACC C L = 100pF (Use Bus Driver IC for Larger CL) - 135 200 ns Three-State Control (Delay from Rising Edge ofRD to Hl-Z State), t1H , t0H C L = 10pF, RL= 10K (See Three-State Test Circuits) - 125 250 ns Delay from Falling Edge ofWR to Reset ofINTR, tWI, tRI - 300 450 ns Input Capacitance of Logic Control Inputs, CIN -5- p F Three-State Output Capacitance (Data Buffers), COUT -5- p F DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX , Unless Otherwise Specified CONTROL INPUTS (Note 6) Logic “1“ Input Voltage (Except Pin 4 CLK IN), VINH Logic “0“ Input Voltage (Except Pin 4 CLK IN), VINL CLK IN (Pin 4) Positive Going Threshold Voltage, V+CLK 2.7 3.1 3.5 V CLK IN (Pin 4) Negative Going Threshold Voltage, V-CLK 1.5 1.8 2.1 V CLK IN (Pin 4) Hysteresis, VH 0.6 1.3 2.0 V Logic “1” Input Current (All Inputs), IINHI VlN = 5V - 0.005 1 µΑ Logic “0” Input Current (All Inputs), IINLO VlN = 0V -1 -0.005 - µA Supply Current (Includes Ladder Current), I+ fCLK = 640kHz,TA = 25oC and CS = Hl - 1.3 2.5 mA DATA OUTPUTS AND INTR Logic “0” Output Voltage, VOL lO = 1.6mA, V+ = 4.75V - - 0.4 V Electrical Specifications(Notes 1, 7) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ADC0802, ADC0803, ADC0804

FIGURE 8. OUTPUT CURRENT vs TEMPERATURE FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE

1 TO 8 x 1/fCLK INTERNAL T C

The device may be operated in the free-running mode by con- necting INTR to the WR input with CS = 0. To ensure start-up under all possible conditions, an external WR pulse is required during the first power-up cycle. A conversion-in-pro- cess can be interrupted by issuing a second start command. Digital Operation The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting “1” level resets the 8-bit shift register, resets the Interrupt (INTR) F/F and inputs a “1” to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then trans- fer this “1” to the Q output of DFF1. The AND gate, G1, com- bines this “1” output with a clock signal to provide a reset signal to the start F/F . If the set signal is no longer present (either WR or CS is a “1”), the start F/F is reset and the 8-bit shift register then can have the “1” clocked in, which starts the conversion process. If the set signal were to still be present, this reset pulse would have no effect (both outputs of the start F/F would be at a “1” level) and the 8-bit shift register would continue to be held in the reset mode. This allows for asyn- chronous or wide CS and WR signals. After the “1” is clocked through the 8-bit shift register (which completes the SAR operation) it appears as the input to DFF2. As soon as this “1” is output from the shift register, the AND gate, G2, causes the new digital word to transfer to the Three-State output latches. When DFF2 is subsequently clocked, the Q output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the INTR output signal. When data is to be read, the combination of bothCS and RD being low will cause the INTR F/F to be reset and the three- state output latches will be enabled to provide the 8-bit digital outputs. Digital Control Inputs The digital control inputs (CS, RD, and WR) meet standard TTL logic voltage levels. These signals are essentially equiva- lent to the standard A/D Start and Output Enable control sig- nals, and are active low to allow an easy interface to microprocessor control busses. For non-microprocessor based applications, the CS input (pin 1) can be grounded and the standard A/D Start function obtained by an active low pulse at the WR input (pin 3). The Output Enable function is achieved by an active low pulse at the RD input (pin 2). Analog Operation The analog comparisons are performed by a capacitive charge summing circuit. Three capacitors (with precise ratioed values) share a common node with the input to an auto-zeroed comparator. The input capacitor is switched between V lN(+) and VlN(-), while two ratioed reference capaci- tors are switched between taps on the reference voltage divider string. The net charge corresponds to the weighted dif- ference between the input and the current total value set by the successive approximation register. A correction is made to offset the comparison by 1/2 LSB (see Figure 11A). Analog Differential Voltage Inputs and Common-Mode Rejection This A/D gains considerable applications flexibility from the ana- log differential voltage input. The VlN(-) input (pin 7) can be used to automatically subtract a fixed voltage value from the input reading (tare correction). This is also useful in 4mA - 20mA cur- rent loop conversion. In addition, common-mode noise can be reduced by use of the differential input. The time interval between sampling V IN(+) and VlN(-) is 41/2 clock periods. The maximum error voltage due to this slight time difference between the input voltage samples is given by: where: ∆VE is the error voltage due to sampling delay, VPEAK is the peak value of the common-mode voltage, fCM is the common-mode frequency. For example, with a 60Hz common-mode frequency, fCM , and a 640kHz A/D clock, fCLK , keeping this error to1/4 LSB (~5mV) would allow a common-mode voltage, VPEAK , given by: or The allowed range of analog input voltage usually places more severe restrictions on input common-mode voltage levels than this. An analog input voltage with a reduced span and a relatively large zero offset can be easily handled by making use of the differential input (see Reference Voltage Span Adjust). Analog Input Current The internal switching action causes displacement currents to flow at the analog inputs. The voltage on the on-chip capaci- tance to ground is switched through the analog differential input voltage, resulting in proportional currents entering the V IN(+) input and leaving the VIN(-) input. These current tran- sients occur at the leading edge of the internal clocks. They rapidly decay and do not inherently cause errors as the on- chip comparator is strobed at the end of the clock perIod. Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the V IN(+) input voltage at full scale. For a 640kHz clock frequency with the VIN(+) input at 5V, this DC current is at a maximum of approximately 5µA. Therefore,bypass capacitors should not be used at the analog inputs or the V REF /2 pin for high resistance sources (>1kΩ ). If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to mini- mize capacitor size, the effects of the voltage drop across this input resistance, due to the average value of the input current, can be compensated by a full scale adjustment while the given source resistor and input bypass capacitor are both in place. This is possible because the average value of the input current is a precise linear function of the differential input voltage at a constant conversion rate. V E MAX()∆ V PEAK() 2π fCM() 4.5 fCLK V PEAK ∆V E MAX() fCLK() V PEAK ADC0802, ADC0803, ADC0804

NOTE: Pin numbers for 8228 System Controller: Others are 8080A. FIGURE 21. ADC0802 TO 8080A CPU INTERFACE

DIE DIMENSIONS: (101 mils x 93 mils) x 525µm x 25µm METALLIZATION: Type: Al Thickness: 10kÅ ±1kÅ PASSIVATION: Type: Nitride over Silox Nitride Thickness: 8kÅ Silox Thickness: 7kÅ Metallization Mask Layout ADC0802, ADC0803, ADC0804 WR RD CS CLK ININTRVIN (-) V IN (+) DGND VREF /2 AGND V+ OR VREF CLK R DB 0DB 1DB 2DB 3DB 4 DB 5 DB 6 DB 7 (MSB) V+ OR VREF ADC0802, ADC0803, ADC0804 All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com