ACT41000

ACT41000 QORVO | Alldatasheet

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Technical content

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator

Ordering Information

Figure 4. Part Numbering Structure

1. Standard product options are identified in this table. Contact local sales for custom options, minimum order quantity
2. This device is RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means

semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.

1. See the Factory Programming Options section for more information about CMI.

customer.support@qorvo.com for a status and availability. Also, see Factory Programming Options. Following devices are similar to the ACT41000 device. customer.support@qorvo.com for a status and availability. Also, see Factory Programming Options. minimum required quantity applies. minimum required quantity applies. minimum required quantity applies.

Figure 5. 32-pin QFN, 5 mm ×5 mm, 0.5 mm pitch, TOP VIEW

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Pin Functions PIN NAME DESCRIPTION 1 PGBIAS Power-good output of the Mini-buck Regulator and Auxiliary LDO. Open-drain and a pull-up resistor required. See PGBIAS Indicator Output. 2 VLDO Output voltage node of the Auxiliary LDO. Connect a good quality, fixed value 1 µF capacitor between this pin and the GND5V pin. See Auxiliary LDO. 3 V5V 5 V bias supply to the device and voltage feedback of the Mini-buck Regulator. Connect two good quality capacitors in parallel, two 10 µF and one 0.1 µF between this pin and the GND5V pin. Place the 0.1 µF capacitor with the minimum distance to the device. 4 GND5V Ground node for the Mini-buck Regulator. 5 SW5V Switching node of the Mini-buck Regulator. 6 VIN Power supply to the device. Connect a good quality 1 µF capacitor, at least, between this pin and the GND5V pin. On a PCB, tied to the PVIN pin. 7,8,17,18 PVIN Power supply to the Main-buck Regulator. Connect good quality two 22 µF capacitors, at least, between this pin and the PGND pins, also tie to the VIN pin. 9,10,15,16PGND Ground node for the Main-buck Regulator. 11,12,13 SW Switching node of the Main-buck Regulator. 14 BOOT Bootstrap capacitor node for the Main-buck Regulator. Connect a good quality, fixed value 0.1 µF capacitor between this pin and the SW pin. 19 PG Power-good output of the Main-buck Regulator. Open-drain and a pull-up resistor required. 20 CSN Current sense feedback input to the Main-buck Regulator. See Output Current Sensing. 21 FB_VO Voltage feedback input to the Main-buck Regulator. See Reference Voltage Input. 22 COMP Error amplifier output. Connect a compensation network between this pin and the AGND pin. See Main-buck Compensation Network. 23 AGND Ground node for analog blocks of the device. 24 DACOUT Reference voltage output from the DAC. Usually, short to the REFIN pin. See Output Voltage Reference 25 REFIN Reference voltage input to the Main-buck Regulator. See Reference Voltage Input. 26 ILIM Output current limit programming of the Main-buck Regulator. Connect a resistor between this pin and the AGND pin. See Output Current Reference. 27 ADDR I2C address selection. Connect a resistor between this pin and the ground. See I2C Address Selection. 28 FREQ Switching frequency programming of the Main-buck Regulator. Connect a resistor between this pin and the AGND pin. See Clock Generator. 29 EN Enable logic input for the Main-buck Regulator. See Main-buck Enable Control. 30 SYNC Clock synchronizing input/output for the Main-buck Regulator. See Clock Synchronizer. 31 SCL Clock port of the I2C Interface. Open-drain and a pull-up resistor required. 32 SDA Data port of the I2C Interface. Open-drain and a pull-up resistor required. Exposed PAD Substrate contact for power dissipation. Connect to the PGND pins with a broad pattern. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 4 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Absolute Maximum Ratings PARAMETER VALUE UNIT PVIN, VIN ‒ 0.3 to +48.0 V SW ‒ 0.3 to (PVIN + 1.0) V FB_VO, CSN ‒ 0.3 to +28.0 V Voltage difference between FB_VO and CSN ‒ 0.3 to +0.3 V SW5V ‒ 0.3 to (VIN + 1.0) V BOOT (VSW ‒ 0.3) to (VSW + 6.0) V EN, PG, PGBIAS, SYNC, REFIN, SDA, SCL, COMP, V5V (external supply) ‒ 0.3 to +6.0 V Operation Junction Temperature ( TJ ) ‒ 40 to +150 °C Storage Temperature ‒ 55 to +150 °C Lead Temperature (Soldering 10sec) up to +300 °C Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability. All voltage values are with respect to the ground voltage unless otherwise specified. Recommended Operating Conditions PARAMETER VALUE UNIT PVIN, VIN +4.2 to +40.0 V V5V (External Supply) +4.5 to +5.5 V EN, PG, PGBIAS, SYNC, REFIN, SDA, SCL, COMP ‒ 0.3 to +5.5 V Operation Junction Temperature (TJ) ‒ 40 to +125 °C Current Sensing Resistor (RCS ) 5 to 80 mΩ Frequency Programming Resistor (RFREQ ) 40 to 200 kΩ All voltage values are with respect to the ground voltage unless otherwise specified. Package Thermal Information PARAMETER VALUE UNIT Thermal Resistance, Junction to Ambient (Θ JA)[1] 24 °C/W [1] Reference number, based on a real measurement of a ACT41000 evaluation board. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 5 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator

Electrical Characteristics

PVIN = VIN = 12 V, V5V = 5 V (external supply), EN = 5 V, TA =25°C, unless otherwise specified PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT BIAS BLOCK VIN Mini-buck Consumption Current II(VIN) EN = 0 V, V5V = 5.25 V, mini-buck ON and no switching 235 µA V5V Quiescent Current IQ(V5V) EN = 0 V, V5V = 5.25 V, mini-buck ON and no switching 1.3 mA V5V Non-switching Current II(V5V) EN = 5 V, V5V = 5.25 V, main-buck ON and no switching 2.8 mA VIT(UVLO) VIN rising to release 4.25 4.5VIN Under-voltage Lock-out Threshold VIT(UVLO,fall) VIN falling to lock 4.1 V VIT(OVLO) VIN rising to lock 42 VIN Over-voltage Lock- out Threshold VIT(OVLO,fall) VIN falling to unlock 39 V V5V Regulation VO(V5V) V5V error comparator threshold 4.8 5.0 5.2 V V5V PG Threshold VIT(V5V) V5V rising 4.25 V V5V Under-voltage VUVP(V5V) V5V falling 3.95 4.15 V V5V Over-voltage VOVP(V5V) V5V rising 5.9 V VLDO Regulation VO(VLDO) IVLOD = 10mA Reg0D[5:0] = 0x30 3.14 3.3 3.47 V VLDO Under-voltage VUVP(VLDO) Reg0D[5:0] = 0x30 2.9 V PGBIAS Output Voltage VOL(PGBIAS) PGBIAS at logic-L, 1 mA Current into PGBIAS pin 0.3 V Mini-buck Over-current IOCP(V5V) 360 mA VLDO Over-current IOCP(VLDO) 20 mA TSD(HARD) Hard TSD, temperature rising 155 TSD(SOFT) Soft TSD, temperature rising 145 Thermal Protection TSD(OFF) TSD release, temperature falling 135 SIGNAL PINS II(FB_VO) 5 V target (DACOUT[10:0] = 0x190) 6 µA II(CSN) 6 µA Signal Pin Input Current II(SYNC) 1 µA Signal Pin Output Current IO(ADDR) R ADDR = 50 kΩ while PGBIAS=L 20 µA Signal Pin Output Voltage VO(FREQ) R FREQ = 40 kΩ 1.2 V EN Threshold VIT(EN) 1.15 1.25 V IO(EN,rise) VEN < VIT(EN) 1 EN Pin Pull-up Current IO(EN,fall) VEN > VIT(EN) 2 µA ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 6 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT SYNC Pin Input Threshold VIT(SYNC) SYNC pin in slave 0.55 1.4 V VOH(SYNC) SYNC pin in master, outputs logic-H 3.2 V5VSYNC Pin Output Voltage VOL(SYNC) SYNC pin in master, outputs logic-L 0 0.8 V I2C PINS Input Threshold VIT(I2C) SDA and SCL pins 0.55 1.25 V Leakage Current ILK(SDA) VSDA = 5 V 1 µA Output Voltage VOL(SDA) 5 mA Current into SDA pin 0.35 V Input Capacitance C I(I2C) SDA and SCL pins 10 pF MAIN-BUCK REGULATOR VDACOUT(24) 24 V target (DACOUT[10:0] = 0x780), 50 µA current DACOUT sourcing -0.5% 3.0 +0.5% VDACOUT(5) 5 V target (DACOUT[10:0] = 0x190), 50 µA current DACOUT sourcing -0.5% 0.625 +0.5% VDACOUT Accuracy ΔV DACOUT VDACOUT (n+1) - VDACOUT (n) 0 1.5625 mV FB_VO Accuracy VO W.r.t. VREFIN , VREFIN = 3 V -1% 24 1% V ILIM(100) 100% target (ILIM[7:0] = 0xFF) 98.5 101.5 ILIM(25) 25% target (ILIM[7:0] = 0x3F) 24.25 25.75 Output Current Limit Programming Accuracy ΔI LIM ILIM(n+1) - ILIM(n) 0 0.4 µA VCCMODE(100) Differential voltage (VFB_VO - VCSN ) at VLIM = 1.6 V 78.5 81.5Constant Current Operation Programming Accuracy VCCMODE(25) Differential voltage (VFB_VO - VCSN ) at VLIM = 0.4 V 19.3 20.7 mV PG Output Voltage VOL(PG) PG at logic-L, 1 mA Current into PG pin 0.3 V PG Threshold Upper Limit[1] VIH(VO) Threshold of Reg03[2], VO_FB w.r.t. VREFIN , VREFIN = 3 V +5% +8% PG Threshold Lower Limit[1] VIL(VO) Threshold of Reg03[2], VO_FB w.r.t. VREFIN , VREFIN = 3 V -8% -5% FB_VO Over-voltage VOVP VO_FB w.r.t. VREFIN , VREFIN = 3 V +8% V VUVP(CC) Reg0B[3] = logic-L, VO_FB w.r.t. VREFIN , VREFIN = 3 V 2.7 2.76FB_VO Under-voltage[2] VUVP(CV) Reg0B[3] = logic-H, VO_FB w.r.t. VREFIN , VREFIN = 3 V -8% V VIT(CC,rise) Enable CC loop, Reg09[3] = logic-H, VO_FB rising 2.3 2.5FB_VO Constant Current Activation Threshold VIT(CC,fall) Disable CC loop, Reg09[3] = logic-H, VO_FB falling 2.2 V IOCP(CBC,high) High-side FET limit to trigger 5.5 Main-buck Cycle-by- cycle Current Limit IOCP(CBC,low) Low-side FET limit to release 4.2 A ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 7 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT Discharge Resistance R DIS 1.2 kΩ [1] See Main-buck Power-Good for details. [2] See Under-Voltage Protection for details. Timing Requirements PARAMETER SYMBOL CONDiTION MIN TYP MAX UNIT I2C BLOCK SCL Clock Frequency fSCL (no internal time out) 0 1000 kHz tLOW(SCL) Logic-L level 0.5 SCL Pulse Width tHIGH(SCL) Logic-H level 0.26 µs SDA Set-up Time tSU(SDA) 50 ns SDA Hold Time tH(SDA) 0 ns START Set-up Time tSU(START) 260 ns STOP Set-up Time tSU(STOP) 260 ns EN pin INPUT EN Pulse Width tLOW(EN) Logic-L level 30 µs SYNC pin INPUT SYNC Frequency Range 20kΩ < RADDR < 50kΩ 400 2500 kHz SYNC Frequency Accuracy fSYNC 20kΩ < RADDR < 50kΩ, referring to the frequency setpoint by RFREQ 75% 125% SYNC Input Duty D IN(SYNC) 20kΩ < RADDR < 50kΩ 40% 60% Switching Characteristics PVIN = VIN = 12 V, V5V = 5 V (external supply), EN = 5 V, TA =25°C, unless otherwise specified PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT BIAS BLOCK Mini-Buck Switching Frequency fSW(V5V) 2.0 MHz Mini-Buck Spread- Spectrum Dithering Range [1] fSPSP(V5V) Frequency modulation range w.r.t. fSW(V5V) value ±7% Mini-Buck Spread- Spectrum Cycle N SPSP(V5V) Number of TON cycles 32 cycle Mini-Buck Soft-Start Time tSS(V5V) "VIN = VIT(UVLO)" to "V5V = VIT(V5V)" 0.5 ms Mini-Buck UVP Mask Timer tD(V5V,mask) 1 ms Wait Timer before Error Reset tD(RESET) 100 ms PGBIAS Delay tD(PGBIAS) "V5V = VIT(V5V)" to PGBIAS↑, target 3 ms (Reg08[4:3] = 11) -10% 3 10% ms ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 8 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT AUX LDO Soft-Start Time[2] tSS(LDO) Just for reference, Reg0D[5:0] = 0x31 100 µs I2C BLOCK SDA Fall Time tF(SDA) Pull-up to 5-V source via 10 kΩ 120 ns MAIN-BUCK REGULATOR fSW(MAIN)(min) R FREQ = 200 kΩ 400 450 500 kHzMain-Buck Switching Frequency fSW(MAIN)(max) R FREQ = 40 kΩ 2.0 2.25 2.5 MHz SYNC Output Duty Cycle D OUT(SYNC) 50% Δf SYNC(low) 40% SYNC Input WDT Error Detection Δf SYNC(high) 20kΩ < RADDR < 50kΩ, referring to the frequency setpoint by RFREQ 210% Main-Buck Spread- Spectrum Dithering Range [1] fSPSP(MAIN) Frequency modulation range w.r.t. fSW(MAIN) ±7% Main-Buck Spread- Spectrum Cycle N SPSP(MAIN) Number of TON cycles 64 cycle ON Time Control tON(min) 65 80 ns OFF Time Control tOFF(min) 65 80 ns Main-Buck Digital Servo Clock Period tW(SERVO) 8 µs Hiccup Timer tW(HICCUP) 100 ms tD(PG)(min) FB_VO > VIL(VO), 0 ms target (Reg08[7:6] = 00) 10 µsPG Delay tD(PG)(max) FB_VO > VIL(VO), 4 ms target (Reg08[7:6] = 11) -10% 4 10% ms [1] No production test [2] Not actively controlled, application board dependent ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 9 www.qorvo.com

anything on the EVK board (except tuning a potentiometer for a target output voltage setting). The device consists of following four major blocks.

• Main-buck regulator The Main-buck Regulator is a 4 A, synchronous, step-down DC-DC converter, featuring on-the-fly programming voltage and current-limit reference generators.
• Mini-buck regulator The Mini-buck Regulator is a 5 V output, 350 mA, always-ON, step-down DC-DC converter.
• Auxiliary (AUX) LDO regulator The Auxiliary LDO is a programmable output voltage, 20 mA low drop-out (LDO) linear regulator.
• Control Logic The Control Logic is a state-machine (STM) logic and I2C interface controller Functional Block Diagram

Figure 44. Functional Block Diagram

At a higher level, the STM consists of nine major status as shown in Table 1. Table 1. Major States in STM Main-buck ON Main-buck is up and running.

The STM controls the device by the State Diagram below. Figure 45. State Diagram

1. read various status bits of the device,
2. write various setting bits to control behaviors of the device and read back those setting bits.

The device complies with the I2C-bus specification (UM10204). The SCL and SDA pins are open-drain and a pair of pull-up resistors are required. See SCL/SDA Pull-up Resistance for the resistor value selection.

Figure 46. I2C Block address options, so to avoid address collisions when using multiple ACT41000 devices sharing one I2C bus. See Figure 46. pin" and "SYNC Polarity" in the Table 2 are there for the Clock Generator block. Table 2. I2C Address with Clock Role The I2C implementation of the device is explained in the Figure 47. size paper, for an ese of readability. (or from top to bottom in a landscape view), these sequences are shown.

1. "One byte WRITE" to a register
2. "Multi-byte WRITE" to registers
3. "one byte READ" from a register, plus another "one byte READ" without setting a target read register
4. (folded back, remaining portion of "3. one byte READ")
5. "Multi-byte READ" from registers

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator I2C One byte WRITE Writing one byte of data into a target register is completed by one 3-byte I2C WRITE command. The one byte WRITE command byte format is 1. I2C START 2. I2C ACT41000 (target) device address 3. One zero bit for "write" 4. I2C ACK from the ACT41000 (This is the end of the 1st byte.) 5. Target ACT41000 register address (See Table 6.)) 6. I2C ACK from the ACT41000 (This is the end of the 2nd byte.) 7. Register value to write 8. I2C ACK from the ACT41000 (This is the end of the 3rd byte.) 9. I2C STOP I2C Multi-byte WRITE Writing multi-byte of data into target registers is completed by one multi-byte I2C WRITE command. The multi-byte WRITE command byte format is 1. I2C START 2. I2C ACT41000 (target) device address 3. One zero bit for "write" 4. I2C ACK from the ACT41000 (This is the end of the 1st byte.) 5. The first/starting target ACT41000 register address, assume the address is "N" (See Table 6.)) 6. I2C ACK from the ACT41000 ⇒ See "Reg Pointer" that the device sets the target register to "N", at the timing of the ACK. (This is the end of the 2nd byte.) 7. Register value to write to the "N" register 8. I2C ACK from the ACT41000 ⇒ See "Reg Pointer" that the device automatically increments the target register at the timing of the ACK. So the next write data goes to "N+1". (This is the end of the 3rd byte.) 9. Register value to write to the "N+1" register 10. I2C ACK from the ACT41000 ⇒ Another "Reg Pointer" increment to "N+2" at the ACK. (This is the end of the 4th byte.) 11. Register value to write to the "N+2" register 12. I2C ACK from the ACT41000 ⇒ Another "Reg Pointer" increment to "N+3" at the ACK, though the "N+3" is not used in this example. (This is the end of the 5th byte.) 13. I2C STOP ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 21 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator I2C One byte READ Reading one byte of data from a target register is completed by a combination of a. one 2-byte I2C WRITE command and b. one 2-byte I2C READ command. The one byte READ command sequence is 1. I2C START 2. I2C ACT41000 (target) device address 3. One zero bit for "write" 4. I2C ACK from the ACT41000 (This is the end of the 1st byte in "WRITE".) 5. Target ACT41000 register address, assume the address is "N" (See Table 6.)) 6. I2C ACK from the ACT41000 ⇒ See "Reg Pointer" that the device sets the target register to "N", at the timing of the ACK. (This is the end of the "WRITE" command.) 7. I2C REPEATED START 8. I2C ACT41000 (target) device address 9. One high bit for "read" 10. I2C ACK from the ACT41000 (This is the end of the 1st byte in "READ".) 11. The ACT41000 device send out the requested register data from "N" ⇒ Note that at 5th SCL of this data sending action, the device increments the "Reg Pointer" value to "N+1". Whether this byte date is successfully sent out or not (like a case of the host cancel the communication by a sudden STOP), the pointer is incremented at the 5th SCL. 12. I2C NACK from the host device (This is the end of the "READ" command.) 13. I2C STOP (This is the end of one byte "READ" sequence.) ⇒ Now, see what happens just sending a "READ" command without a leading "WRITE" command setting a target register. There may be some commands on this bus where "other slave devices" involved (not this device). 14. I2C START 15. I2C ACT41000 (target) device address 16. One high bit for "read" 17. I2C ACK from the ACT41000 (This is the end of the 1st byte in "READ".) 18. The ACT41000 device send out the register data from "N+1" ⇒ Here is the key point in this example. The "Reg Pointer" stays at "N+1" from the step "11." So just sending a "READ" command without a "WRITE" command results in reading a "next register" from the last time. 19. I2C NACK from the host device (This is the end of the 2nd "READ" command.) 20. I2C STOP This example "14…20" illustrates that it requires a pair of WRITE and READ commands to access a certain register repeatedly. Because every time a READ action happens the device increments the "reg pointer", a WRITE command is required to reset the "reg pointer".ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 22 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator I2C Multi-byte READ Reading multi-byte of data from target registers is completed by a combination of a. one 2-byte I2C WRITE command and b. one multi-byte I2C READ command. When sending multiple bytes in a READ command, the device automatically increment the target register one-by-one at the timing of 5th SCL as explained in the I2C One byte READ section. The multi-byte READ command sequence is 1. I2C START 2. I2C ACT41000 (target) device address 3. One zero bit for "write" 4. I2C ACK from the ACT41000 (This is the end of the 1st byte in "WRITE".) 5. Target ACT41000 register address, assume the address is "N" (See Table 6.)) 6. I2C ACK from the ACT41000 ⇒ See "Reg Pointer" that the device sets the target register to "N", at the timing of the ACK. (This is the end of the "WRITE" command.) 7. I2C REPEATED START 8. I2C ACT41000 (target) device address 9. One high bit for "read" 10. I2C ACK from the ACT41000 (This is the end of the 1st byte in "READ".) 11. The ACT41000 device send out the requested register data from "N" ⇒ Because the "Reg Pointer" is "N" at the beginning of this byte, the device sends out data from "N". In parallel, the device increments the "Reg Pointer" to "N+1" at 5th SCL. 12. I2C ACK from the host device to continue reading data (This is the end of the 2nd byte in "READ".) 13. The ACT41000 device send out the "N+1" data ⇒ The "Reg Pointer" is "N+1" at the beginning of this byte, the device sends out data from "N+1". In parallel, the device increments the "Reg Pointer" to "N+2" at 5th SCL. 14. I2C ACK from the host device to continue reading data (This is the end of the 3rd byte in "READ".) 15. The ACT41000 device send out the "N+2" data ⇒ Another "Reg Pointer" increment. 16. I2C NACK from the host device (This is the end of the "READ" command.) 17. I2C STOP ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 23 www.qorvo.com

Figure 47. I2C Communication Waveforms (supports zoom in from a PDF viewer)

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Under-Voltage Lock-Out The Under-Voltage Lock-Out (UVLO) function prevents the ACT41000 device working under too low input voltage at the VIN pin. As the VIN pin is connected to the PVIN pin on a PCB, the UVLO monitors PVIN too. When the VIN pin voltage is below the VIT(UVLO) threshold, the device disables all the functions but this UVLO circuit. During this UVLO period, the device minimizes power consumption and wait for the VIN pin voltage rises into a valid range. When the VIN pin voltage exceeds the VIT(UVLO) threshold, the device starts working, by following the Control Logic state-machine. Once the UVLO released, the device keeps working as long as VIN pin voltage maintains higher than the VIT(UVLO,fall) threshold that has a hysteresis from the VIT(UVLO) value. Over-Voltage Lock-Out The Over-Voltage Lock-Out (OVLO) function prevents the ACT41000 device working from too high input voltage at the VIN pin. As the VIN pin is connected to the PVIN pin on a PCB, the OVLO monitors PVIN too. When the VIN pin voltage exceeds the VIT(OVLO) threshold, the device disables all the functions but this OVLO circuit. During this OVLO period, the device minimizes power consumption and wait for the VIN pin voltage decrease back into a valid range. When the VIN pin voltage gets back normal (under VIT(OVLO,fall)), the device starts working, by following the Control Logic. The Reg01[0] bit is set logic-H to indicate this error. This OVLO does not protect the device from any potential damage caused by over-voltage events. See Note of Absolute Maximum Rating. The OVLO is only intended to reduce a risk of a chain-reaction that the VIN/PVIN over-voltage event triggers by disabling all output rails of the device. Factory Programmed ROM The ACT41000 integrates a read-only memory (ROM) block and that is programmed at its factory test. The data contents of the ROM configure various behaviors of the device and also some of the contents are default values of I2C registers. When the Under-Voltage Lock-Out released, the Control Logic state-machine activates the ROM block as its first step and the STM configures itself according to the ROM values. See Factory Programming Options. BIAS Blocks The ACT41000 employs several bias voltage and bias current reference circuits those are necessary to maintain proper operations of regulator blocks. When the Under-Voltage Lock-Out released, the Control Logic state-machine activates these reference and bias circuits before starting the Mini-buck Regulator. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 25 www.qorvo.com

The mini-buck supplies up to 350 mA of output current by step-down converting power from the VIN pin. Figure 48. Mini-buck Regulator with an LC Output Filter full performance. A short event at the V5V pin may cause a potential damage. released. And the mini-buck keeps ON all the time. Reg09[1] to logic-L to save power loss from its switching. Whether the mini-buck is enabled or disabled, there is a voltage comparator monitoring the V5V pin to the VIT(V5V) target. See PGBIAS Indicator Output. The mini-buck supports a start-up into a pre-biased output without any huge discharge current from the output. than the pre-biased output by starting from 0%. device avoids the discharge event and achieves a smooth ramp up of the 5 V bias.

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Mini-buck Switching Operations Mini-buck Forced Continuous Conduction Operation By setting I2C Reg0F[5] to Logic-H, the device operates in a forced continuous conduction mode (FCCM). With this FCCM operation, the regulator maintains its switching frequency to meet the fSW(V5V) target. This fSW(V5V) parameter ensures that its operation frequency do not interfere with AM radio frequency by staying above the AM band. Mini-buck Pulse-skip Operation By setting I2C Reg0F[5] to Logic-L, the device operates in a pulse-skipping mode, or so-called, in a light-load efficiency mode. When its load current goes low, the inductor (coil) current starts flowing in reverse direction (negative current). As the regulator detects continuous reverse current flow cycles, it activates the pulse-skip operation by blocking the reverse current flow. By blocking a reverse current flow, an energy amount delivered during one switching period is bigger than the one period energy amount of FCCM operation and the output has a bigger ripple voltage. This bigger ripple results in less switching events to reduce power loss related to a switching action. So it improves its conversion efficiency. During this pulse-skip operation, its switching frequency may stay inside AM radio frequency band. Mini-buck 100% Duty Operation When the VIN pin voltage is close to the target output voltage VO(V5V), the mini-buck gets into 100% duty mode by setting I2C Reg0F[7]. Without this 100% duty mode (disabled), the device is designed to output a minimum OFF period at each cycle, even though its internal PWM comparator continuously demands more ON duty. This minimum OFF pulse helps to stay at its target switching frequency but it is not desirable when the input voltage is very close to the output as the output voltage starts dropping. When the 100% duty mode is enabled, the device stops forcing the minimum OFF pulse and the high-side FET maintains ON for multiple cycles without turning OFF as long as the PWM comparator indicates low feedback voltage. This 100% duty operation helps bringing the output voltage close to the input. Reg03[5] is set logic-H to indicate that the regulator is in 100% duty operation. This 100% duty operation lowers its switching frequency and may stay at AM radio frequency band. Mini-buck Spread-spectrum Operation The mini-buck provides a spread-spectrum switching frequency control by setting I2C Reg0F[6]. By activating the spread-spectrum function, the regulator modulates its switching frequency in the range of the fSPSP(V5V) parameter and it repeats this frequency dithering action by the NSPSP(V5V) times of switching period. The spread-spectrum operation improves its EMI performance by lowering noise peaks. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 27 www.qorvo.com

Figure 49. Mini-buck Regulator Spread-spectrum Operation the noise performance improves; faster transient rate improves the efficiency. Table 30 for the high-side gate available options and see Table 31 for the low-side date available options. devices. When the output current exceeds this threshold, the device triggers the over-current protection. The Reg02[2] is set logic-H to indicate this error. See Executing Protections for the execution of this protection. any reason, it exceeds the threshold, the device triggers the over-voltage protection. Reg02[1] is set logic-H to indicate this error. See Executing Protections for the execution of this protection. falls below the threshold, the device triggers the under-voltage protection. Reg02[0] is set logic-H to indicate this error. See Executing Protections for the execution of this protection. activates this under-voltage protection.

LDO is powered by the V5V pin and its output voltage is regulated at the VO(VLDO) target. Between the VLDO pin and the GND5V pin, an AUX LDO Output Capacitors is required. Figure 50. AUX LDO Regulator The AUX LDO is activated automatically when the V5V pin voltage exceeds the VIT(V5V) threshold. See Mini-buck Regulator. activated, it can trigger an "error" flow after the AUX LDO Soft-start operation completed. The output voltage of the AUX LDO is programmable from 0.9 V to 4.05 V in 50 mV step by the I2C Reg0D[5:0]. See Table 26 for a target code to program and this table is calculated by the Eq.(1). It’s default value is stored in the Factory Programmed ROM. See Factory Programming Options. AUX LDO Under-Voltage Protection. below the threshold, the device triggers the under-voltage protection. See Executing Protections for the execution of this protection.

resistor. See PGBIAS/PG Pull-up Resistance for its value selection. Figure 51. PGBIAS Block whether the device is ready to activate the Main-buck or not. And also the PGBIAS pin indicates the I2C Interface block is ready. rising edge so to adjust timing between the device and a host micro-controller. Reg08[4:3]. See Table 17 for available options. The PGBIAS pin is double purposed to output an interrupt signal to a host micro-controller. Bias Block Power-good signal.

1. Starting from PGBIAS is at logic-H (good).
2. Output 10 µs of logic-L pulse at the PGBIAS pin and return back to logic-H.
3. Start a 480 µs timer and waits for an I2C read command to the register, causing this interrupt, from an I2C host.
4. When a read command comes in, clear the

Reg01 and Reg02 and complete the interrupt sequence.

1. If there’s no read command, repeat "2."

This sequence is shown in Figure 52.

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Hard TSD In a case the TJ rises very quickly to hit the TSD(HARD) threshold just after passing TSD(SOFT) threshold, the device shuts down all the blocks by executing the Reset Sequence. Before hitting this "hard TSD", it is expected that the "soft TSD" prevents TJ rising by stopping the Main-buck Regulator because the TSD(HARD) is higher than the TSD(SOFT) . So only severe TJ rising event causes the "hard TSD" like a sudden output short while supplying the maximum current. The Reg01[3] bit is set logic-H to indicate this protection. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 32 www.qorvo.com

Switching Frequency Selector. directly assigned to a role as shown in Table 2. When choosing the I2C address, the role is decided too. used for this roles so to use the oscillator for its own switching timing. This role configures the SYNC Disabled. This role configures the SYNC to Output Clock. situations is typically in these 2 cases.

1. Multiple units of ACT41000 are on one PCB and there is a clock-master unit (, not this unit). This unit follows the
2. There is a stable system clock source, like a crystal oscillator, on a PCB. This unit follows the oscillator.

This role configures the SYNC to Input External Clock. not driving SYNC pin when a clock sharing is not needed. between the FREQ pin and the ground. placed between the FREQ pin and the AGND pin as close as possible with short PCB traces. Figure 54. Clock Generator Block with RFREQ compensation parameter is a function of the fSW(MAIN) .

When selecting a role with the Clock Synchronizer, use the Table 3 for a target fSW(MAIN) clock at the SYNC input pin. Table 3. Clock-slave, RFREQ Selection The Recommended R FREQ Range is between 40 kΩ and 200 kΩ. When selecting a role with the Clock Oscillator, follow the Table 4. And the Reg01[4] bit is set logic-H to indicate this error. See R FREQ Check Loop for the execution of this protection. A device of Clock-master or Stand-alone role activates this oscillator block. programmed between 450 kHz and 2.25 MHz by following Eq.(2). The Table 4 lists some calculation examples. Table 4. Clock-master, RFREQ Selection The Recommended R FREQ Range is between 40 kΩ and 200 kΩ. generated by the Clock Oscillator at the SYNC output pin as a clock-master. This output clock signal is used by slave devices. Note that the SYNC pin is a bi-directional input/output pin. See SYNC to Input External Clock.

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator SYNC Disabled A device of Stand-alone role disables the SYNC pin. See SYNC to Output Clock and SYNC to Input External Clock. Clock Synchronizer A device of Clock-slave role activates this synchronizer block. In applications where multiple ACT41000 devices are working together, each Clock Oscillator from multiple devices generate slightly different frequency of clock signals due to a unit-to-unit variations. This situation rises an EMI concern of low frequency beat. To solve this EMI concern, the clock synchronizer follows one master clock source so to make all the devices working (synchronized) at the timing of this master clock. The Clock-slave role paragraph explains two typical scenarios where a clock master is. SYNC to Input External Clock The external clock source signal to the synchronizer is applied at the SYNC input pin so to follow (synchronize to) an external clock master signal. Note that the SYNC pin is a bi-directional input/output pin. See SYNC to Output Clock. SYNC Input Polarity By synchronizing switching timings of multiple devices reduces the EMI concern, however, it causes multiple devices turning on at the same time to increase transient current noise. To relieve this "same time ON" situation, the device in the Clock-slave role can select clock edge to follow the master. The synchronizer is designed to follow either one of 1. a rising edge of the SYNC input (SYNC↑), or 2. a falling edge of the SYNC input (SYNC↓). This polarity selection is also done at the timing the I2C address is chosen from the I2C Address Selection. SYNC Input Watch Dog Timer In case an input signal at the SYNC pin is unstable, the main buck regulation becomes unstable. To avoid this sort of unreliable SYNC input situations, the device monitors frequency of the external clock source at the SYNC input pin. This circuit is a sort of watch dog timer (WDT) structure. This WDT circuit is based on the Table 3 setting. When the input external clock signal is out of range between Δf SYNC(low) and Δf SYNC(high), a "SYNC WDT Error" event is triggered. The Reg01[5] bit is set logic-H to indicate this error. And the Reg03[7] or Reg03[6] bit indicates whether the input clock is higher or lower the range. SYNC Input Error Hiccup Operation. By setting the Reg09[2] bit at logic-L, this WDT repeats a "wait" and "retry" cycle, that is so called a "hiccup" operation. At the first time a WDT event happens, the device disables its switching operation for the tW(HICCUP) of time period, and then the device tries to restart. If its SYNC input signal becomes stable, the main buck regulator continues working as normal; if the SYNC input is still unstable, the devices goes into another disabled state for another tW(HICCUP) period to repeat the hiccup operation. See Protection Level 4 for the execution of this protection. SYNC Input Error Latch-off Operation. By setting the Reg09[2] bit at logic-H, the main-buck regulator latches the OFF status at the first WDT event. See Protection Level 3 for the execution of this protection. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 35 www.qorvo.com

the Reference Voltage Input block and this DAC output is assigned at the DACOUT pin. Figure 55. Output Voltage Reference This DAC converts 11 bit data from Reg0A[7:0] and Reg0B[2:0] based on Eq.(3). See Table 21 for this bit to voltage conversion table. be enough for its full performance even though the device is fully functional. truncated as "0x780" to avoid an over-voltage condition. entire 11 bit without a timing gap. Reg05[1] bit. A logic-H to this bit triggers the DAC block loads new target value as 11 bit data. The DAC block only loads new target value at a trigger by this "load command" bit. Servo Reference Control and Figure 57.

signal, used by the Programmable Current Limit block and this iDAC current output is assigned at the ILIM pin. The iDAC converts 8 bit data from the Reg0C[7:0] bits based on Eq.(4). See Table 24 for this bit to current conversion table. Figure 56. Output Current Reference Output Current Reference blocks.

1. two digital comparators, 11 bit one for Output Voltage Reference and 8 bit one for Output Current Reference, and
2. two up/down counters, 11 bit one for Output Voltage Reference and 8 bit one for Output Current Reference, and
3. a servo clock source and a clock divider.

digital code as long as corresponding digital comparator results are not "A = B" by synchronized to the Servo Clock Divider. both references in servo, and vice versa. This servo block is used in the Main-buck Soft-start too. See Loading New DACOUT Value.

Figure 57. Servo Control Block is control by the Reg09[7:6] bits and see Table 19 for available options.

The main-buck is the main step-down switching regulator of the ACT41000 device. Figure 58. Main-buck Regulator the output voltage is fed back to the FB_VO input to close the regulator control loop. The main-buck block requires following external components.

• An output LC filter. See Main-buck LC Output Filter.
• A bootstrap capacitor. See Main-buck Bootstrap Capacitor.
• A compensation capacitor. See Main-buck Compensation Network.
• A current limit programming resistor. See Programmable Current Limit.
• A current sense register. See Output Current Sensing. Main-buck Enable Control The main-buck regulator is enabled and disabled by this enable control block. From the view point of power sequencing, the input of the main-buck is the iEN signal from this block and the output is the Main-buck Power-Good signal. Disable. When iEN is logic-L, the main-buck is disabled. The main-buck provides an active discharge function when the Reg09[4] bit is logic-H. During the active discharge, the device activates the Output Discharge Resistor to force the output near ground level in shorter time. This feature is useful in applications where the output is expected to start from the (near) ground voltage. When the Reg09[4] bit is logic-L, the main-buck makes the output node high impedance at it disabled condition. Consumption current from load devices discharges the output and, generally, the output voltage value is uncontrolled. Enable. When iEN is logic-H, the main-buck is enabled and it regulates the output as described in following sections. No Controller to Drive the EN pin. The EN pin has an internal pull-up source as shown in the Figure 59, so the EN pin becomes logic-H by leaving it open (connected to nothing) and the main-buck gets enabled every time the Control Logic comes to the Bias Ready status. By using an external delay circuit, the device can support an application specific needs in many flexible ways. See Timing Control between PGBIAS and EN EN Input Buffer The logic input buffer at the EN pin provides a programmable hysteresis capability. As shown in the Figure 59, There are two of 1-µA current sources at the EN pin where the first 1-µA element is always connected working as a constant bias and the second 1-µA element gets connected to the EN pin when its input is logic-H as a hysteresis source. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 39 www.qorvo.com

Figure 59. EN Input Buffer may not be captured. To ensure valid Logic-L input, at least tLOW(EN) of Logic-L period is required. Additional UVLO by the EN pin. Eq.(6), following three calculations are listed.

1. the detecting threshold voltage when VIN is rising
2. the detecting threshold voltage when VIN is falling
3. the hysteresis voltage from "1." and "2."

Based on the Eq.(6), some example calculation results are listed in the Table 5. Table 5. EN pin Hysteresis Example

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator I2C Enable Bit The Reg05[0] bit is a second enable signal input to the main-buck. When the ACT41000 device is controlled by an I2C host processor, this host does not need to control the EN pin. This saves one GPIO terminal at the host. Internal Enable Signal The Main-buck Regulator is controlled by a logic OR operation of 2 input signals 1. a logic input signal at the EN pin from the EN Input Buffer block and 2. a logic setting bit in the I2C register at the Reg05[0] bit. (7) throughout this datasheet, call this logic OR operation result (iEN) as an iEN signal that is short for an internal EN. When the iEN signal becomes logic-H, the main-buck start working. When it reaches its target voltage, the device outputs the Main- buck Power-Good signal. Output Discharge Resistor The device provides a pull down resistor of the R DIS value, from the FB_VO pin to the PGND pin. This RDIS is activated at two different occasions. 1. Active Discharge at Disable See Main-buck Enable Control. 2. Active Negative Transition See Negative Transition with RDIS. Reference Voltage Input The main-buck regulates its output voltage based on the REFIN pin voltage as its reference. In a typical usage, the DACOUT pin, from the Output Voltage Reference block, is connected to the REFIN pin by shorting these adjacent pins on a PCB as shown in the Figure 55. The output voltage, sensed by the FB_VO pin, is regulated at eight times of the REFIN voltage as shown in the Eq.(8). By combined with the Eq.(3) , the output voltage is controlled by the I2C Table 21 in 12.5 mV step as shown in the Eq.(9). The calculated results from the Eq.(9) is found in the Table 21. (8) (9) Even though the I2C block accepts it as a valid data, any value below 0x0F0 sets the output voltage below 3.0 V and, by default, the Under-Voltage Protection (UVP) triggers a fault action. See Programmable Current Limit and Under-Voltage Protection. External Reference Voltage It is not necessary to connect the DACOUT and the REFIN pins for the main-buck voltage reference. When a stable and well-regulated reference voltage source is available on a PCB, such external voltage reference can be used in a position of the Output Voltage Reference. The main-buck control loop is designed to follow whatever voltage comes into the REFIN pin by following the Eq.(8). When the DACOUT pin is not used to feed the REFIN pin, there is no Main-buck Soft-start function and an external voltage reference driving the REFIN pin needs to ramp up slowly to avoid huge inrush current. Main-buck Soft-start The soft-start (or slow-start) function of the main-buck uses the Servo Reference Control so to avoid inrush current to the output capacitor, at a start-up event. While the iEN is logic-L, the iEN signal reset the 11 bit up/down counter at the in the Figure 57. Simply, when the iEN becomes logic-H, the iEN signal releases the reset and the counter start ramping up to the DACOUT[10:0] target. During this soft-start period, the main-buck forces to use, so called, pulse-skip operation so to achieve smooth ramp up of the output voltage. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 41 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Main-buck Soft-start into Pre-biased Output The main-buck supports a start-up operation into a pre-biased output so to avoid huge discharge current from the pre- biased output capacitor. As described in Main-buck Soft-start, in a case of normal start-up ("non" pre-biased output), the soft-start function starts from zero target and the main-buck control loop try to follow the REFIN voltage that is rising by the servo. Here, at the inputs of the Error Amplifier, the reference is higher than the feedback. In a case of pre-biased output without this "pre-bias" support, until its reference voltage comes to the pre-biased output voltage, the feedback is higher than the reference. So a regulator without the "pre-bias" support tries to pull down its pre- biased output toward the voltage target its reference points. Usually, this results in a huge reverse current flow from its output capacitor. The soft-start engine of the ACT41000 device is designed to do nothing until the REFIN voltage comes to the pre-biased output voltage. Error Amplifier The main-buck has one error amplifier to maintain high feedback loop gain. The feedback input voltage at the FB_VO pin and the reference input voltage at the REFIN pin are compared by the error amplifier and its error output signal is assigned at the COMP pin. A compensation network is required between the COMP pin and the ground. See Figure 58 and Main-buck Compensation Network. Valley Current Mode Loop Control The ACT41000 employs a proprietary valley current mode control to regulate the output voltage. The control maintains its operation at a fixed frequency point for EMI noise sensitive applications. This unique current-mode yields very high loop gain bandwidth and good stability over wide range of its operating conditions. Main-buck Switching Options Forced Continuous Current Operation The device operates in a forced continuous conduction mode (FCCM). With this FCCM operation, the regulator maintains its switching frequency to meet the fSW(MAIN) targets. These fSW(MAIN) parameter ensures that its operation frequency do not interfere with AM radio frequency by staying above the AM band. Pulse-skip Operation This function block is not used in this ACT41000 device option. This is a placeholder for other device options in this product family. See Ordering Information. 100% Duty Operation When the PVIN pin voltage is close to the target output voltage VO , the main-buck gets into 100% duty mode by setting the Reg0B[7] bit. Without this 100% duty mode (disabled), the device is designed to output a minimum OFF period at each cycle, even though its internal PWM comparator continuously demands more ON duty. This minimum OFF pulse helps to stay at its target switching frequency but it is not desirable when the input voltage is very close to the output as the output voltage starts dropping. When the 100% duty mode is enabled, the device stops forcing the minimum OFF pulse and the high-side FET maintains ON for multiple cycles without turning OFF as long as the PWM comparator indicates low feedback voltage. This 100% duty operation helps bringing the output voltage close to the input. When keeping the high-side FET ON for a long time period, the bootstrap capacitor voltage becomes lower as a high- side gate driver consumes power from the bootstrap capacitor. To maintain a proper operation of the high-side FET, the bootstrap capacitor needs to be recharged occasionally. This refresh action happens at every eight cycles. This means that, at a worst case, its operation switching frequency becomes one eighth (1/8 = 12.5%) of the target setting. The Reg03[3] bit is set logic-H to indicate that the regulator is in 100% duty operation. When using this 100% duty operation, consider to increase amount of output capacitance by monitoring the output voltage. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 42 www.qorvo.com

This 100% duty operation lowers its switching frequency and may stay at AM radio frequency band. The main-buck provides a spread-spectrum switching frequency control by setting the Reg0B[6] bit. operation improves its EMI performance by lowering noise peaks. Figure 60. Main-buck Regulator Spread-spectrum Operation shown in Figure 58, the FB_VO and the CSN pins are monitoring an external current sense resistor RCS . device. This means a continuous operation at this programmable current limit is safe and supported. of this protection will degrade or damage the device permanently. or damage the device permanently. current limit control (or a constant current "CC" control) to the VCCMODE target when the Reg0B[4] bit is logic-H. VIT(CC,rise) target. And it gets disabled when the FB_VO voltage goes below the VIT(CC,fall) target.

its output voltage droops. This voltage drop may trips the Main-buck Power-Good or Under-Voltage Protection blocks. additional Schottky diode in parallel with the low-side FET helps better rectification. fully depending on the RILIM and RCS accuracy, tolerance control on an application PCB. CV and CC seamlessly. And the device can report its status through the I2C. For certain applications, a host controller device wants to know the timing of this CC⇌CV transition. At a transition event, the Reg01[7] bit becomes logic-H to generate an interrupt. When in CC, the Reg03[4] bit becomes logic-H. When in CV, the Reg03[4] bit becomes logic-L. current) load, may cause an event of output voltage overshoot. The PG pin is an indicator output of the main-buck. The PG is an open-drain type output and it requires a pull-up resistor. PGBIAS/PG Pull-up Resistance for its value selection. Figure 61. PG Block Programming operation employs the Servo Reference Control, the PG pin becomes logic-L during such operation.

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator avoid an inconsistent PG output, the Servo Reference Control blocks the PG pin regardless of voltage or current target changes. Main-buck Power-Good Detail The PG pin indicates the device is in a regulation of either CV or CC. When the PG pin is "good", the device provides multiple bits for the detail of this power-good operation through the I2C. The Reg03[4] bit indicates whether the device in CV or CC . The Reg03[2] bit indicates whether the device in the CV regulation window of the VIH(VO) and VIL(VO) thresholds. The Reg01[7] bit indicates a transition between CV or CC . Main-buck Power-Good Delay The PG block has a programmable delay circuit at the output stage of the PG pin. The device can insert a certain delay time from the timing of device internal power-good judgement to actual PG pin transition. This programmable delay helps to build a flexible power sequencing design on a PCB. The Reg08[7:6] bits controls this delay time and see Table 16 for available options. On-the-fly Reference Programming By using the Servo Reference Control block, the main-buck supports on-the-fly programming of the Output Voltage Reference and Output Current Reference. That means, through the I2C, the main-buck can accept a target value change of these two reference sources while the iEN is logic=H. See Main-buck Power-Good. Negative Transition with RDIS In the Output Voltage Reference is programmed for a lower target voltage from the current output, it may take long time period to reach to the new target value when very little load current / activities there. To accelerate such light-load negative transition, the device utilizes the Output Discharge Resistor block when the Reg09[5] bit is logic-H. Main-buck EMI Tune-up For the purpose of improving its EMI performance, this main-buck provides programmable switching node slew rate. By changing the Reg0E[3:2] bits, an application system designer can balance the tradeoff between its power conversion efficiency and its EMI noise level. By selecting slower transient rate, the noise performance improves; faster transient rate improves the efficiency. See Table 28 for the available options. Output Current Protections In this datasheet, following three function names refer to clearly different meanings and behaviors of the device. Programmable Current Limit The Programmable Current Limit function is a regulation control of the main-buck output current at a programming target value (CC : constant-current operation), within a safe operation area (SOA) of the device. This means a continuous operation at this programmable current limit is safe and supported. Cycle-by-cycle Current Limit The Cycle-by-cycle Current Limit protection is a hard limit of the main-buck output current. The threshold of this protection is beyond the design and safe operation area of the device. Repeated events of this protection will degrade or damage the device permanently. Over-Current Protection The Over-Current Protection (OCP) is a superset of the cycle-by-cycle current limit protection. The OCP is also beyond the design and safe operation area of the device and repeated OCP events will degrade or damage the device permanently. Cycle-by-cycle Current Limit The cycle-by-cycle current limit protection monitors current flow on the integrated high-side and low-side FET devices at every PWM cycle. When the high-side FET current flow exceeds the IOCP(CBC,high) threshold, the protection forces the ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 45 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator SW pin to the low state (high-side FET: OFF, low-side FET: ON) until the low-side FET current flow comes below the IOCP(CBC,low) target. During this protection working, the gate driver logic circuits ignore signals from main regulation control blocks. A result of the cycle-by-cycle current limit protection looks like a CC operation. And also, continuous cycle-by-cycle operation reports the device in a CC operation by setting the Reg03[4] bit to logic-H. Unlike the Programmable Current Limit operation, this cycle-by-cycle current limit protection is outside of the device safe operating area and the system should not operates the device in a continuous cycle-by-cycle current limit. Over-Current Protection The over-current protection is a superset of the Cycle-by-cycle Current Limit protection. When the Cycle-by-cycle Current Limit block repeats four (4) consecutive pairs of IOCP(CBC,high) and IOCP(CBC,low) detections, the device triggers this over- current protection. The Reg02[6] bit is set logic-H to indicate this error. See Executing Protections for the execution of this protection. Practically, without any board level failure condition, the Cycle-by-cycle Current Limit protection reduces main inductor current flow very effectively within one cycle before observing four times of events. So this over-current protection gets triggered by an event of shorting the output, shorting the SW pin or shorting the coil. Over-Voltage Protection The over-voltage protection (OVP) monitors and maintains the output voltage at the FB_VO pin not to exceed the VOVP threshold. For any reason, it exceeds the threshold, the main-buck triggers the over-voltage protection. The Reg02[5] bit is set logic-H to indicate this error. See Executing Protections for the execution of this protection. Under-Voltage Protection The under-voltage protection (UVP) monitors the output voltage at the FB_VO pin at the VUVP(CV) or the VUVP(CC) threshold. See UVP selection. For any reason, it falls below the threshold, the device triggers the under-voltage protection. The Reg02[4] bit is set logic-H to indicate this error. See Hiccup Operation, Latch-off Operation and Executing Protections for the execution of this protection. UVP selection To support various application cases, the main-buck provides different UVP threshold options. When using the CC block, the output voltage is expected to drop when transits from the CV to the CC operation. So the UVP is expected to trigger at lower threshold target for the CC operation. The Reg0B[3] bit at logic-L selects VUVP(CC) for this purpose. Setting this bit at logic-H selects VUVP(CV) for the CV operation. In case a wide CC operation range is needed more than the VUVP(CC) target, the UVP can be disabled by setting the Reg09[3] bit at logic-H. With this Reg09[3] bit, the CC block keeps its operation to the full range down to the VIT(CC,fall) target. By setting the Reg09[3] bit, the UVP protection "action" is disabled at the Control Logic block level regardless of the FB_VO pin voltage. Still the status indicator bit Reg02[4] and its detector circuit is active and an interrupt is generated when the FB_VO cross the threshold. The Reg07[4] mask bit helps this situation if an interrupt is not needed. By disabling the UVP by the Reg09[3] bit, there is no way to detect an event of output short. When a short event happens without the UVP, there are only the Thermal Protection and the Over-Current Protection blocks to protect the device and a risk of damaging the device increases. Hiccup Operation By setting the Reg09[2] bit at logic-L, the main-buck regulator repeats a "wait" and "retry" cycle, that is so called a "hiccup" operation. At the first time the output voltage hits the UVP threshold, the device disables its switching operation for the tW(HICCUP) of time period, and then the device restart the switching. If a cause of the under-voltage condition goes away ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 46 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator while disabled, the main buck regulator keeps working as normal; if the cause is still there, the devices goes into another disabled state for another tW(HICCUP) period to repeat the hiccup operation. See Protection Level 4 for the execution of this protection. When selecting the hiccup option, the device has no way to escape from an endless hiccup loop. A host controller device is expected to take a proper procedure to stop this endless hiccup loop. When the device is in the hiccup operation, always there is a repeating narrow time window where the output voltage overshoots. This time windows are between almost-end of soft-start operation and a sudden event of releasing hiccup cause(s). During this time window, the device has almost finished a soft-start operation and the target reference voltage is high enough but the device does not judge next round of hiccup yet. So the device starts working at a very high duty cycle to overshoot. The latch-off option is free from this overshoot concern. Latch-off Operation By setting the Reg09[2] bit at logic-H, the main-buck regulator latches the OFF status. See Protection Level 3 for the execution of this protection. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 47 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Executing Protections The ACT41000 integrates multiple levels of device protections. Each level of protection behavior is explained in following sections in the order of severity. Protection Level 1 The level 1 protection is a complete shutdown of the device except very minimum functions. When following protections are triggered, the device stops its entire function except UVLO and OVLO blocks because the input voltage VIN (and PVIN) is out of acceptable operation range. See Recommended Operating Conditions.

• Under-Voltage Lock-Out
• Over-Voltage Lock-Out This level 1 protection status continues until both UVLO and OVLO are released. The OVLO does not protect the device from any potential damage caused by over-voltage events. See Note of Absolute Maximum Rating. Protection Level 2 The level 2 protection is a whole device reset of the device by executing an auto-restart procedure. When following protections are triggered, the device executes the Reset Sequence because the device cannot continue its normal operations safely.
• Mini-buck Over-Current Protection
• Mini-buck Over-Voltage Protection
• Mini-buck Under-Voltage Protection
• AUX LDO Under-Voltage Protection
• Hard TSD Reset Sequence 1. Stop the Mini-buck Regulator and Auxiliary LDO. 2. Start a logic timer of the tD(RESET) reset blanking period. 3. Restart the Mini-buck Regulator at the time out of "2." timer. Protection Level 3 The level 3 protection is a latch-OFF of the Main-buck Regulator function. When following protections are triggered, the device turns OFF the Main-buck Regulator and remains OFF until the iEN signal becomes logic-L. This latch-OFF status is just like a device waiting for an enable trigger even though iEN maintains logic-H from the timing of event caused this latch-OFF state.
• Latch-off Operation
• SYNC Input Error Latch-off Operation
• Over-Voltage Protection
• Over-Current Protection Protection Level 4 The level 4 protection is a temporary disable of the Main-buck Regulator function, with an auto-restart. Or it is so called a "hiccup" operation. When following protections are triggered, the device turns OFF the Main-buck Regulator for the tW(HICCUP) period and retry to activate the main-buck. When a cause of protection remains, another disable cycle is repeated for another tW(HICCUP) period.
• Hiccup Operation
• SYNC Input Error Hiccup Operation
• Soft TSD ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 48 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Protection RFREQ In normal conditions, the R FREQ Protection is a short-period transition state. Only when the device cannot validate RFREQ value in the Recommended R FREQ Range, due to a wrong PCB assembly, the device repeats this RFREQ validation forever. This loop is a sort of dead-lock because the bias block is ready but cannot activate the main-buck due to the unreliable R FREQ . By repeating this RFREQ checking loop, the device ensures to keep sending an interrupt of the Reg01[4] bit. This protection is only performed before entering the Bias Ready state and it is not continuously monitoring <Rfreq> after passing the Bias Ready state. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 49 www.qorvo.com

access, how to setup these registers. This is an entire mapping of I2C registers on the ACT41000 device. Here are the meanings of each column in Table 6. Y: The default values can be programmed by a production test. N : The default values are fixed / hard-coded. settings. See Factory Programming Options. In Table 6 below, each register address value string is a link to the detailed bit description. Table 6. Register Address Map

The register 0x00 is Read Only type. It indicates current position of the state-machine. See Control Logic. Table 7. Register 0x00

3 State[3] 0

2 State[2] 0

1 State[1] 0

0 State[0] 0

Table 8. State-Machine Bits [3:0]

described. See Interrupt Output. Bits in these registers will be automatically cleared by reading the value with an I2C command. This automatic bit-clear action applies if the cause of an interrupt is resolved at the timing of a READ action. trigger shutdown actions to resolve the error situation. Table 9. Register 0x01 Table 10. Register 0x02 6 Main-buck Over-current Event 0 Becomes 1 when the output current in Over-Current Protection.

4 VUVP(CV) or VUVP(CC) Event 0 Becomes 1 when the VO falls below the VUVP(CV) or VUVP(CC)

threshold. See Under-Voltage Protection. 3 AUX LDO Under-voltage 0 Becomes 1 when the VO(VLDO) falls below the VUVP(VLDO) threshold.

2 IOCP(V5V) Event 0 Becomes 1 when the output current of the mini-buck exceeds the

IOCP(V5V) threshold. See Mini-buck Over-Current Protection. Mini-buck Over-Voltage Protection. Mini-buck Under-Voltage Protection. The register 0x03 is Read Only type. It indicates various status flags from internal circuit blocks.

Table 11. Register 0x03

7 WDT High 0

6 WDT Low 0

1*: Clock input at SYNC is too high/low to accept. 0: (normal), See SYNC Input Watch Dog Timer. 5 Mini-buck in 100% 0 1*: Mini-buck is operating in 100% mode. : Mini-buck is operating out of 100% mode. See Mini-buck 100% Duty Operation. 4 Main-buck in CC 0 1*: Main-buck is operating in CC mode. : Main-buck is operating in CV mode. See Programmable Current Limit. 3 Main-buck in 100% 0 1*: Main-buck is operating in 100% mode. : Main-buck is operating out of 100% mode.

2 PG of Main-buck 0 1*: Main-buck in "Power-good" condition

The register 0x04 is reserved for future spins. Nothing is assigned to this register. The register 0x05 is Read / Write type. A writing action to this register triggers a certain action at the device. Table 12. Register 0x05 1 Load DACOUT 0 Setting 1 to load DACOUT value in effect. Always reads 0. See Loading New DACOUT Value.

0 Enable Main-buck 0 Writing 1 to enable Main-buck

Reg02[5] bit. See Interrupt Output. Table 13. Register 0x06

7 Mask Main-buck in CC/CV 0 1: mask bit 7 of Reg01

5 Mask Out of Range, SYNC Input 0 1: mask bit 5 of Reg01

4 Mask Out of Range, RFREQ 0 1: mask bit 4 of Reg01

3 Mask TSD(HARD) Event 0 1: mask bit 3 of Reg01

2 Mask TSD(SOFT) Event 0 1: mask bit 2 of Reg01

0 Mask VIT(OVLO) Event 0 1: mask bit 0 of Reg01

Table 14. Register 0x07

6 Mask Main-buck Over-current

5 Mask VOVP Event 0 1: mask bit 5 of Reg02

4 Mask VUVP(CV) or VUVP(CC) Event 0 1: mask bit 4 of Reg02

3 Mask AUX LDO Under-voltage 0 1: mask bit 3 of Reg02

2 Mask IOCP(V5V) Event 0 1: mask bit 2 of Reg02

1 Mask VOVP(V5V) Event 0 1: mask bit 1 of Reg02

0 Mask VUVP(V5V) Event 0 1: mask bit 0 of Reg02

The register 0x08 is Read / Write type. It configures the device behaviors as described. Table 15. Register 0x08

7 PG Delay[1] 0

6 PG Delay[0] 0

5 Mask All 1 1: overrides all Reg06 and Reg07 bits 1 internally. 0: "masking" follows each bit of Reg06 and Reg07.

4 PGBIAS Delay[1] 0

3 PGBIAS Delay[0] 1

See PGBIAS Indicator Output. Table 16. PG Delay [1:0] Table 17. PGBIAS Delay [1:0]

The register 0x09 is Read / Write type. It configures the device behaviors as described. Table 18. Register 0x09

7 Servo Clock[1] 1

6 Servo Clock[0] 1

5 Discharge in Servo 1 1: Use discharge resistor to drive VO servo down. 0: Not use discharge resistor in servo. See Negative Transition with RDIS and Output Discharge Resistor. 4 Discharge at OFF 1 1: Use discharge resistor when main-buck disabled. 0: Not use discharge resistor when main-buck disabled. Main-buck Enable Control and Output Discharge Resistor. 3 Main-buck No UVP 0 1: disable main-buck under-voltage protection. use main-buck under-voltage protection. 2 Hiccup / Latch-off 0 1: Latch-off action in main-buck. See Under-Voltage Hiccup and Under-Voltage Latch-off. Also, see SYNC Error Hiccup and SYNC Error Latch-off. 1 Enable Mini-buck 1 1: enable Mini-buck, automatically start-up Mini-buck. 0: disable Mini-buck, manually start-up Mini-buck. 0 Enable AUX LDO 1 1: enable AUX LDO, automatically start-up AUX LDO. 0: disable AUX LDO, manually start-up AUX LDO. Table 19. Servo Clock [1:0]

The register 0x0A is Read / Write type. It programs DACOUT value. Table 20. Register 0x0A

7 DACOUT[10] 0

6 DACOUT[9] 0

5 DACOUT[8] 1

4 DACOUT[7] 1

3 DACOUT[6] 0

2 DACOUT[5] 0

1 DACOUT[4] 1

0 DACOUT[3] 0

See Output Voltage Reference. Table 21. DACOUT[10:0] [1] Minimum value of the DACOUT range characterized. [2] Maximum value of the DACOUT range characterized. The register 0x0B is Read / Write type. It configures the device behaviors as described.

Table 22. Register 0x0B 7 Enable main-buck 100% 0 1: enable main-buck 100% mode. 0: disable main-buck 100% mode.

6 Enable main-buck Spread-

0 1: enable main-buck spread-spectrum operation. disable main-buck spread-spectrum operation. See Spread-spectrum Operation. 4 Enable main-buck CC 1 1: enable main-buck Constant-current operation. 0: disable main-buck Constant-current operation. 3 Select main-buck UVP 0 1: select VUVP(CV) .

2 DACOUT[2] 0

1 DACOUT[1] 0

0 DACOUT[0] 0

See Output Voltage Reference.

The register 0x0C is Read / Write type. It programs ILIM value. Table 23. Register 0x0C

7 ILIM[7] 1

6 ILIM[6] 1

5 ILIM[5] 1

4 ILIM[4] 1

3 ILIM[3] 1

2 ILIM[2] 1

1 ILIM[1] 1

0 ILIM[0] 1

See Output Current Reference. Table 24. ILIM[7:0]

The register 0x0D is Read / Write type. It programs AUX LDO value. Table 25. Register 0x0D

5 LDO Voltage[5] 1

4 LDO Voltage[4] 1

3 LDO Voltage[3] 0

2 LDO Voltage[2] 0

1 LDO Voltage[1] 0

0 LDO Voltage[0] 0

See AUX LDO Output Voltage Programming. Table 26. LDO Voltage[5:0]

The register 0x0E is Read / Write type. It configures the device behaviors as described. Table 27. Register 0x0E 5 (fixed value) 1 always program this bit to 1.

3 Main-buck HSD[1] 0

2 Main-buck HSD[0] 0

1 (fixed value) 1 always program this bit to 1. 0 (fixed value) 1 always program this bit to 1. Table 28. Main-buck Gate Driver Strength[1:0]

The register 0x0F is Read / Write type. It configures the device behaviors as described. Table 29. Register 0x0F 7 Enable Mini-buck 100% 1 1: enable Mini-buck 100% mode. 0: disable Mini-buck 100% mode. See Mini-buck 100% Duty Operation.

6 Enable Mini-buck Spread-

0 1: enable Mini-buck spread-spectrum operation. disable Mini-buck spread-spectrum operation. See Mini-buck Spread-spectrum Operation. 5 Enable Mini-buck Forced CCM 0 1: enable Mini-buck Forced CCM operation. disable Mini-buck Forced CCM (= pulse-skipping) operation. See Mini-buck Forced Continuous Conduction Operation.

4 Mini-buck HSD[1] 1

3 Mini-buck HSD[0] 1

2 Mini-buck LSD[1] 1

1 Mini-buck LSD[0] 1

Table 30. Mini-buck High-side-driver Strength[1:0] Table 31. Mini-buck Low-side-driver Strength[1:0]

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator

Application Information

RF Power Amplifier IDQ Detection and Bias Sequence Without using an additional current sensing amplifier, the ACT41000 supports precise drain bias current (IDQ ) detection of an RF power amplifiers, by using the integrated Programmable Current Limit function. As an example, the Qorvo® QPA2211 device is selected to illustrate how the ACT41000 detects the IDQ . See the Figure 1. The Original QPA2211 Datasheet Bias Sequence Bias Up Procedure 1. Set ID limit to 3500 mA, IG limit to 40mA 2. Apply ‒ 5 V to VG 3. Apply 22 V to VD ; ensure IDQ is approx. 0 mA 4. Adjust VG until IDQ = 280 mA 5. Turn on RF supply Bias Down Procedure 1. Turn off RF supply 2. Reduce VG to ‒ 5 V; ensure IDQ is approx. 0 mA 3. Set VD to 0 V 4. Turn off VD supply 5. Turn off VG supply The QPA2211 Bias Sequence with ACT41000 Bias Up Procedure 1. @MCU & Gate Driver Set IG limit to 40mA 2. @ACT41000 Set current limit at 280 mA [1] 3. @MCU & Gate Driver Apply ‒ 5 V to VG 4. @ACT41000 Turn on VD [2] 5. @MCU & Gate Drvier Start sweeping up VG 6. @MCU & Gate Driver Stop sweepting VG upon an interrrupt from the PGBIAS pin of ACT41000 7. @ACT41000 Set current limit at 3500 mA [3] 8. Turn on RF supply Bias Down Procedure 1. Turn off RF supply 2. @ACT41000 Set current limit at 280 mA 3. @MCU & Gate Driver Reduce VG to ‒ 5 V 4. @ACT41000 Set voltage reference at the minimum [4] 5. @ACT41000 Turn off VD [2] 6. @MCU & Gate Driver Turn off VG supply [1], [3] See 0x0C register and Programmable Current Limit [2]See 0x05 register and Main-buck Enable Control [4]See 0x05 register, 0x0A register, 0x0B register and Output Voltage Reference ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 63 www.qorvo.com

An inductor value of the LC output filter is 47 µH. close to the device with the highest priority of all components. The target value of the high frequency capacitor is 0.1 µF. The second main capacitor is recommended to be 10 µF. quality MLCC. These bulk capacitors are not necessary to be placed at both edges of the package. recommended to follow this design guideline. requires bigger output capacitance. Strongly recommended to follow this design guideline. Table 32 shows a center target value set of the LC filter. Table 32. Main-buck LC filter recommended value of this bootstrap capacitor is 0.1 µF.

Figure 64. Main-buck Compensation Capacitor For entire frequency range, use 470 pF capacitor as shown in the Table 33. Table 33. Main-buck Compensation Capacitor

2.25 MHz 470

See Switching Frequency Selector. See Output Current Reference. recommended minimum pull-up resistor is calculated as in Eq.(12). Note that a pull-up voltage source is an application system dependent.

Note that a pull-up voltage source is an application system dependent. The Figure 65 is an example of a delay circuit configuration to meet following requirements.

• The EN pin receives only "power-good" signal, an interrupt signal filtered.
• The PGBIAS pin maintains both "power-good" and "interrupt" signals.

Figure 65. Example PGBIAS drives EN with an RC filter

Figure 66. Example Diagram: High Brightness LED Driver

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Factory Programming Options At a production test before shipping, the ACT41000 device can have different behavior(s) from the descriptions in this datasheet by burning different configuration ROM bits. In this section, there’s a quick summary of possible configuration options. Please contact your local sales representatives for an availability of such options and a minimum purchase quantity may apply.

• Main-buck in 0.75 V to 6 V output
• Many of I2C register default values
• AUX LDO default value
• Main-buck in a constant-ON (COT) control, instead of current-mode control
• Stronger spread-spectrum for both mini-buck and main-buck
• Different soft-start time of mini-buck
• Lower PG threshold for the V5V pin
• Alternative mini-buck control without using an external inductor ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 69 www.qorvo.com

Figure 67. 32-pin QFN, 5 mm × 5 mm, 0.5 mm pitch

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Handling Precautions Parameter Rating Standard ESD — Human Body Model (HBM) Class 2 ANSI/ESDA/JEDEC JS-001-2017 ESD — Charged Device Model (CDM) Class C3 ANSI/ESDA/JEDEC JS-002-2014 MSL — Moisture Sensitivity LevelLevel 3 IPC/JEDEC J-STD-020 Caution! ESD-Sensitive Device Solderability Compatible with both lead-free (260 °C max. reflow temperature) and tin/lead (245 °C max. reflow temperature) soldering processes.

REVISION HISTORY

Description

Rev.A Apr 15, 2021 ACT41000 101 Initial release Rev.B Apr 01, 2022 ACT41000 104 Marketing: Adding "104" option Technical: No change ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 71 www.qorvo.com

Programmable Voltage, Programmable Current, Low Noise RFPoL Step-Down Voltage Regulator Product Compliance This part complies with RoHS directive 2011/65/EU as amended by (EU) 2015/863. This part also has the following attributes:

• Lead Free
• Halogen Free (Chlorine, Bromine) Contact Information For the latest specifications, additional product information, worldwide sales and distribution locations: WEB www.qorvo.com TEL +1-844-890-8163 E-MAIL customer.support@qorvo.com Important Notice The information contained herein is believed to be reliable; however, Qorvo makes no warranties regarding the information contained herein and assumes no responsibility or liability whatsoever for the use of the information contained herein. All information contained herein is subject to change without notice. Customers should obtain and verify the latest relevant information before placing orders for Qorvo products. The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information. THIS INFORMATION DOES NOT CONSTITUTE A WARRANTY WITH RESPECT TO THE PRODUCTS DESCRIBED HEREIN, AND QORVO HEREBY DISCLAIMS ANY AND ALL WARRANTIES WITH RESPECT TO SUCH PRODUCTS WHETHER EXPRESS OR IMPLIED BY LAW, COURSE OF DEALING, COURSE OF PERFORMANCE, USAGE OF TRADE OR OTHERWISE, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death. Copyright 2022 © Qorvo, Inc. | Qorvo ® is a registered trademark of Qorvo, Inc. ACT41000 Data Sheet, Rev. B, 01-Apr-2022 Subject to change without notice 72 www.qorvo.com