A1171 MAT | Alldatasheet
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Technical content
General-Purpose Hall Effect Latch 050423 www.masteranalog.com Page 1 of 2 RD-30024 Rev 2.01 A1171 is a high sensitivity and economical on latch function of the Hall IC. Absolute Maximum Ratings At (TA=25℃) Characteristics Values Unit Supply Voltage, (VDD) 26 V Output V oltage, (VOUT) 26 V Output Current, (ISINK) 80 mA Operating Temperature Range, (TA) -40 ~+125 ℃ Storage Temperature Range, (TS) -65 ~ +150 ℃ Package Power Dissipation, (PD) 606 / 230 mW Functional Block Diagram Voltage Regulator Amp VDD Out VSS Hall Sensor Hall Sensor Electrical Specifications DC Operating Parameters： T A=+25℃, VDD=12V Parameters Test Conditions Min Typ Max Units Supply V oltage, (VDD) Operating 3.5 24.0 V Supply Current, (IDD) B<BOP 3.5 8.0 mA Output Saturation V oltage, (VDSON) IOUT=50mA, B>BOP 200.0 mV Output Leakage Current, (IOFF) IOFF B<BRP, VOUT = 12V 10.0 uA Output Switch Frequency, (FSW) 3 kHz Output Rise Time, (TR) RL=1KΩ, CL =20pF 0.5 uS Output Fall Time, (TF) RL=1KΩ; CL =20pF 0.5 uS Electro-Static Discharge HBM 4 KV Operate Point, (BOP) I3(S3) 0(-60) 60(0) Gauss Release Point, (BRP) I3(S3) -60(0) 0(60) Gauss Hysteresis, (BHYS) |BOP - BRP| 60 Gauss CMOS Hall Effect Latch Supply Voltage 3.5 ~ 24V BOP：30 Gauss BRP：-30 Gauss Output Open Drain Package SIP-3(I3) SOT-23(S3) Masteranalog
General-Purpose Hall Effect Latch 050423 www.masteranalog.com Page 2 of 2 RD-30024 Rev 2.01 Package Dimension and Sensor Location (Top VieW) NOTES: 1. Controlling dimension: mm 2. Leads must be free of flash and plating voids 3. Do not bend leads within 1 mm of lead to package interface. 4. PINOUT: Pin No. Pin Name Function
1 VDD Power Supply
2 VSS Ground
3 VOUT Output
(Top VieW) NOTES: 1. Controlling dimension: mm 2. Leads must be free of flash and plating voids 3. Lead thickness after solder plating will be 0.254mm maximum 4. PINOUT: Pin No. Pin Name Function