75545P

HUF75545P3 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 9

Technical content

Features

• Ultra Low On-Resistance -r DS(ON) = 0.010Ω, VGS = 10V
• Simulation Models - Temperature Compensated PSPICE® and SABER© Electrical Models - Spice and SABER© Thermal Impedance Models - www.semi.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve

Ordering Information

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified JEDEC TO-220AB JEDEC TO-263AB DRAIN (FLANGE) DRAIN SOURCE GATE HUF75545P3 GATE SOURCE DRAIN (FLANGE) HUF75545S3S D G S PART NUMBER PACKAGE BRAND HUF75545P3 TO-220AB 75545P HUF75545S3S TO-263AB 75545S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUF75545S3ST. HUF75545P3, HUF75545S3S UNITS Drain Current Figure 4 A A D 270 1.8 W W/oC Maximum Temperature for Soldering 300 260 oC oC NOTES: 1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Data Sheet June 1999

Electrical SpecificationsTC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BV DSS ID = 250µA, VGS = 0V (Figure 11) 80 - - V Zero Gate Voltage Drain Current I DSS VDS = 75V, VGS = 0V - - 1 µA VDS = 70V, VGS = 0V, TC = 150oC - - 250 µA Gate to Source Leakage Current I GSS VGS =±20V - - ±100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage V GS(TH) VGS = VDS , ID = 250µA (Figure 10) 2 - 4 V Drain to Source On Resistance r DS(ON) ID = 75A, VGS = 10V (Figure 9) - 0.0082 0.010 Ω THERMAL SPECIFICATIONS Thermal Resistance Junction to Case R θJC TO-220 and TO-263 - - 0.55 oC/W Thermal Resistance Junction to Ambient R θJA -- 6 2 oC/W SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time t ON VDD = 40V, ID = 75A VGS = 10V, R GS = 2.5Ω (Figures 18, 19) - - 210 ns Turn-On Delay Time t d(ON) -1 4-n s Rise Time t r - 125 - ns Turn-Off Delay Time t d(OFF) -4 0-n s Fall Time t f -9 0-n s Turn-Off Time t OFF - - 195 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Q g(TOT) VGS = 0V to 20V V DD = 40V, ID = 75A, Ig(REF) = 1.0mA (Figures 13, 16, 17) - 195 235 nC Gate Charge at 10V Q g(10) VGS = 0V to 10V - 105 125 nC Threshold Gate Charge Q g(TH) VGS = 0V to 2V - 6.8 8.2 nC Gate to Source Gate Charge Q gs -1 5-n C Reverse Transfer Capacitance Q gd -4 3-n C CAPACITANCE SPECIFICATIONS Input Capacitance C ISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) - 3750 - pF Output Capacitance C OSS - 1100 - pF Reverse Transfer Capacitance C RSS - 350 - pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage V SD ISD = 75A - - 1.25 V ISD = 35A - - 1.00 V Reverse Recovery Time t rr ISD = 75A, dISD /dt = 100A/µs - - 100 ns Reverse Recovered Charge Q RR ISD = 75A, dISD /dt = 100A/µs - - 300 nC HUF75545P3, HUF75545S3S

.SUBCKT HUF75545 2 1 3 ; rev 21 May 1999 CA 12 8 5.4e-9 CB 15 14 5.3e-9 CIN 6 8 3.4e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 87.4 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.1e-9 LSOURCE 3 7 4.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 4.80e-3 RGATE 9 20 0.87 RLDRAIN 2 5 10 RLGATE 1 9 51 RLSOURCE 3 7 44 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.6e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*320),3))} .MODEL DBREAKMOD D (RS = 2.3e-1 TRS1 = 0 TRS2 = -1.8e-5) .MODEL DPLCAPMOD D (CJO = 4.8e-9 IS = 1e-30 N = 10 VJ = 1 M = 0.8) .MODEL MMEDMOD NMOS (VTO = 3.04 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.87) .MODEL MSTROMOD NMOS (VTO = 3.5 KP = 105 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.65 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 8.7 ) .MODEL RBREAKMOD RES (TC1 = 1.3e-3 TC2 = -1e-6) .MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2.8e-5) .MODEL RSLCMOD RES (TC1 = 1.53e-3 TC2 = 2e-5) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5) .MODEL RVTEMPMOD RES (TC1 = -2.9e-3 TC2 = 5e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5 VOFF= -3) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3 VOFF= -5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= 0.5) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -1.5) .ENDS NOTE: For further discussion of the PSPICE model, consultA New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. + - + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ESLC RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE HUF75545P3, HUF75545S3S

template huf75545 n2,n1,n3 electrical n2,n1,n3 var i iscl d..model dbreakmod = () m..model mmedmod = (type=_n, vto = 3.04, kp = 6, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.5, kp = 105, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.65, kp = 0.12, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5, voff = -3) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3, voff = -5) c.ca n12 n8 = 5.4e-9 c.cb n15 n14 = 5.3e-9 c.cin n6 n8 = 3.4e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 5.1e-9 l.lsource n3 n7 = 4.4e-9 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -1e-6 res.rdbody n71 n5 = 2.1e-3, tc1 = 1.5e-3, tc2 = 5.1e-6 res.rdbreak n72 n5 = 2.3e-1, tc1 = 0, tc2 = -1.8e-5 res.rdrain n50 n16 = 4.8e-3, tc1 = 9e-3, tc2 = 2.8e-5 res.rgate n9 n20 = 0.87 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 51 res.rlsource n3 n7 = 44 res.rslc1 n5 n51 = 1e-6, tc1 = 1.53e-3, tc2 = 2e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.6e-3, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.9e-3, tc2 = 5e-7 res.rvthres n22 n8 = 1, tc1 = -2.3e-3, tc2 = -1.2e-5 spe.ebreak n11 n7 n17 n18 = 87.4 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/320))** 3)) + - + - RBREAK RVTEMP VBAT RVTHRES IT 17 18 S1A S1B S2A S2B CA CB EGS EDS MWEAK EBREAK DBODY RSOURCE SOURCE 7 3 LSOURCE RLSOURCE CIN RDRAIN EVTHRES 1621 MMED MSTRO DRAIN LDRAIN RLDRAIN DBREAK DPLCAP ISCL RSLC1 RSLC2 GATE RGATE EVTEMP ESG LGATE RLGATE RDBODY RDBREAK HUF75545P3, HUF75545S3S

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com SPICE Thermal Model REV 21 May 1999 HUF75545T CTHERM1 th 6 6.4e-3 CTHERM2 6 5 3.0e-2 CTHERM3 5 4 1.4e-2 CTHERM4 4 3 1.6e-2 CTHERM5 3 2 5.5e-2 CTHERM6 2 tl 1.5 RTHERM1 th 6 3.2e-3 RTHERM2 6 5 8.1e-3 RTHERM3 5 4 2.3e-2 RTHERM4 4 3 1.3e-1 RTHERM5 3 2 1.8e-1 RTHERM6 2 tl 3.8e-2 SABER Thermal Model SABER thermal model HUF75545T template thermal_model th tl thermal_c th, tl ctherm.ctherm1 th 6 = 6.4e-3 ctherm.ctherm2 6 5 = 3.0e-2 ctherm.ctherm3 5 4 = 1.4e-2 ctherm.ctherm4 4 3 = 1.6e-2 ctherm.ctherm5 3 2 = 5.5e-2 ctherm.ctherm6 2 tl = 1.5 rtherm.rtherm1 th 6 = 3.2e-3 rtherm.rtherm2 6 5 = 8.1e-3 rtherm.rtherm3 5 4 = 2.3e-2 rtherm.rtherm4 4 3 = 1.3e-1 rtherm.rtherm5 3 2 = 1.8e-1 rtherm.rtherm6 2 tl = 3.8e-2 RTHERM4 RTHERM6 RTHERM5 RTHERM3 RTHERM2 RTHERM1 CTHERM4 CTHERM6 CTHERM5 CTHERM3 CTHERM2 CTHERM1 tl th JUNCTION CASE HUF75545P3, HUF75545S3S