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Technical content
Features
- Four derived outputs at frequencies specified by Hewlett Packard Computer Peripherals Bristol/Boise (CPB)
- Less than ±250 ps cycle-to-cycle jitter (13.2 MHz clock excluded derated to ±400 ps)
- Less than ±350 ps absolute jitter
- Supports 3.3V operation
- TTL compatible logic: VIL = 0.8V max., VIH = 2.0V min., VOL = 0.4V max., and VOH = 2.4V min.
- OE pin has internal pull-up
- 45/55% duty cycle on all outputs
- 1 5 output drivers
- Accepts 26.5625 MHz input reference
- Built-in crystal oscillator circuit. Capacitive load presented to the crystal is approximately 14 pF
- Outputs designed to drive 30 pF loads
- Available in 16-pin SOIC package Functional Description The W173 has been defined to meet the timing signal require- ments for Hewlett Packard CPB tape drive system. S Block Diagram Pin Configuration XTAL OSC REFIN PLL 1
50 MHz
6.6 MHz
13.2 MHz
10 MHz
6.6MHZ GND 13.2MHZ VDD GND 10MHZ VDD GND OE VDD 50MHZ 8 9 VDDGND
Note: 1. All inputs, except X1 or X2, have an internal pull-up re sistor. Unconnected inputs will assume a logic HIGH condition. Pin Definitions [1] Pin Name Pin No. Pin Type Pin Description OE 5 I Output Enable: When LOW, this input signal puts all outputs into a high-impedance state. 13.2MHZ 13 O Clock Output: Provides a TTL-level timing signal proportional in frequency to the input signal. For a 26.5625 MHz reference, the frequency will be 13.2 MHz. 6.6MHZ 15 O Clock Output: Provides a TTL-level timing signal proportional in frequency to the input signal. For a 26.5625 MHz reference, the frequency will be 6.6 MHz. 10MHZ 10 O Clock Output: Provides a TTL-level timing signal proportional in frequency to the input signal. For a 26.5625 MHz reference, the frequency will be 10.0 MHz. 50MHZ 7 O Clock Output: Provides a TTL-level timing signal proportional in frequency to the input signal. For a 26.5625 MHz reference, the frequency will be 50.0 MHz. X1 2 I External Crystal Connection: This pin has dual functions. It can be used as an external 26.5625 MHz crystal connection or as an external reference frequency input. X2 3 O External Crystal Connection: An input connection for an external 26.5625 MHz crystal. If using an external reference, this pin must be left unconnected. VDD 1, 6, 9, 12, 16 P Power Supply Connections: Connect both VDD pins to the same voltage, either 3.3V or 5.0V. Each VDD pin should have a decoupling capacitor (such as 0.1 µF) placed as close to the pin as possible. GND 4, 8, 11, 14 G Ground Connections: Connect all ground pins to the common system ground plane.
- Decoupling Capacitor—A 0.1- µF decoupling capacitor
the ground via should be as short as possible.
- Ferrite Bead (FB)—A common supply connection should
- 22-µF Supply Filter Capacitor—The 22- µF capacitor filters
may not be required; its use should be considered optional.
- PCB power supply traces should be at least 20 mils wide to
Supply Schematic–Single Voltage Supply Operation.
- The clock line width should be set to provide a 60 trace
60impedance on a multi-level board.
- The series termination resistor (sometimes called “damping
close to the clock output as possible (within one inch).
- Assume an output resistance from the W173 of 40,
Figure 1. Test Circuit
Absolute Maximum Ratings[2] Stresses greater than those listed in this table may cause permanent damage to the devic e. These represent a stress rating only. Operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Table 1: Parameter Descrip tion Rating Unit VDD, VIN Voltage on Any Pin with Respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C Parameter Description Test Condition Min. Typ. Max. Unit IDD Supply Current Note: CLK output = 50.0 MHz output loaded 40 mA VIL Input Low Voltage V CC = 5.0V 0.8 V VIH Input High Voltage V CC = 5.0V 2.0 V VOL Output Low Voltage I OL = 1 mA 50 mV VOH Output High Voltage I OH = –1 mA 3.1 V IIL Input Low Current 10 µA IIH Input High Current 10 µA RP Input Pull-up Resistor V IN = 0V 500 k CI Input Capacitance Except X1 and X2 6 pF LI Input Inductance Except X1 and X2 7 nH CL XTAL Load Capacitance Total load to crystal 12 pF Parameter Description Test Condition Min. Typ. Max. Unit Clock Outputs tJC Output Clock Jitter, Cycle-to-Cycle Excluding 13.2-MHz output ±175 ±250 ps ZO Output Buffer Impedance 40 W dT Output Duty Cycle 45 50 55 % tPU Stabilization Time from Power-Up To within 0.1% of final frequency 1.5 3.0 ms fA Long Term Output Frequency Stability Over VCC and TA range 0.01 % Note: 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. All AC tests are performed using the circuit shown in Figure 1 to simulate typical system load conditions. Measurements are taken at the load. Threshold voltage for timing measurements is 1.5V.
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Package Drawing and Dimensions
Ordering Information
Ordering Code Package Type W173G 16-pin SOIC (150 mil) W173GT 16-pin SOIC (150 mil) - Tape and Reel Lead Free CYW173SXC 16-pin SOIC (150 mil) CYW173SXCT 16-pin SOIC (150 mil) - Tape and Reel PIN 1 ID 0°~8°
16 Lead (150 Mil) SOIC
0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] BSC 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] DIMENSIONS IN INCHES[MM] MIN. MAX. 0.016[0.406] 0.010[0.254] X 45° 0.004[0.102] REFERENCE JEDEC MS-012 PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. PACKAGE WEIGHT 0.15gms 16-Lead (150-Mil) SOIC S16.15