CP2120-EK SILABS | Alldatasheet
Document overview
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Technical content
- CP2120 Hardware Interface
The evaluation board is connected to a SPI master and to SMBus devices as shown in Figure 1.
- Connect the SPI Master’s SPI bus lines to the CP212 0. If The CP2120 is the only SPI slave device on the
SPI bus, then the CS pin can be tied low.
- Connect the CP2120’s INT pin to a port pin of the SPI Master.
- Connect the CP2120 to SMBus devices through the SMBus lines.
Please refer to "4. Evaluation Board" on page 2 for more information about these steps. Figure 1. System Connections completes, the CP2120 pulls the INT pin low, which signals the SPI Master that the command has been processed.
The CP2120 evaluation board comes wi th a CP2120 device pre-installed fo r system evaluation and development. the locations of the various I/O connectors. Figure 2. CP2120 Evaluation Board
Connector J3 provides the CP2120 access to the SMBus. Table 2 shows the pinout of the J3 header. signals are provided to allow multiple devices to connect to the evaluation board. Table 1. Pinout for J2 Table 2. Pinout for J3
developers to connect these two signals through a resistor by placing a header on J4. an open-drain state to avoid port pin contention. Connectors J6 and J7 give developers the option of adding pullup resistors to the SMBus’s SDA and SCL lines. Removing shorting blocks from these headers disconnects the pullups from the SMBus lines. ber to add pullups to VDD elsewhere on the SMBus. turn on the LED, and writing a 1 to that pin will turn off the LED. Figure 3. Controlling the LEDs
Triggered Interrupt Source pin. Table 3 shows the pinout for this header. Table 3. Pinout for J10
6 Rev. 0.1 5. Schematic
Rev. 0.1 7 NOTES:
8 Rev. 0.1 CONTACT INFORMATION Silicon Laboratories Inc.
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