DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Features
- Low power PCI Express Gen 2 & Gen 3 clock generator
- Two100-MHz differential SRC clocks
- Low power push-pull output buffers (no 50ohm to ground needed)
- Integrated 33ohm series termination resistors
- Low jitter (<50pS)
- SSON input for enabling spread spectrum clock 2C support with readback capabilities
- Triangular Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction
- Input frequency of 14.318MHz
- Industrial Temperature -40 oC to 85oC
- 3.3V power supply
- 20-pin TSSOP package Pin Configuration Block Diagram VD D 1 20 XIN SDATA 2 19 XOUT SC LK 3 18 VSS VD D 4 17 SSON VSS 5 16 VDD VD D 6 15 VSS VSS 7 14 VDD SRC1 8 13 VDD SRC1# 9 12 SRC2# VSS 10 11 SRC2 14.318MHz crystal or clock Crystal Oscillator/ clock bu ffer PLL Control logic SSON SRC1 SRC1# SRC2 SRC2#
byte is encoded in the command code described in Table 1. 2 SDATA I/O SMBus compatible SDATA. 3 SCLK I SMBus compatible SCLOCK.
5 VSS GND Ground
7 VSS GND Ground
8 SRC1 O, DIF 100 MHz Differentia l serial reference clocks. 9 SRC1# O, DIF 100 MHz Differentia l serial reference clocks.
10 VSS GND Ground
11 SRC2 O, DIF 100 MHz Different ial serial reference clocks. 12 SRC2# O, DIF 100 MHz Different ial serial reference clocks.
15 VSS GND Ground
18 VSS GND Ground
19 XOUT O, SE 14.318 MHz Crystal output. 20 XIN I 14.318 MHz Crystal input. Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
9 Write 9 Write
10 Acknowledge from slave 10 Acknowledge from slave
19 Acknowledge from slave 19 Acknowledge from slave
28 Acknowledge from slave 27:21 Slave address–7 bits
37 Acknowledge from slave 29 Acknowledge from slave
46 Acknowledge from slave 38 Acknowledge
Table 3. Byte Read and Byte Write Protocol
29 Stop 28 Read
29 Acknowledge from slave
38 NOT Acknowledge
39 Stop
Byte 0: Control Register 0 Bit @Pup Name Description
7 HW RESERVED RESERVED
Byte 1: Control Register 1 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 0 PLL1_SS_DC Select for down or center SS 0 = Down spread, 1 = Center spread 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 1 RESERVED RESERVED 1 0 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 2: Control Register 2 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 3: Control Register 3 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 RESERVED RESERVED 5 1 RESERVED RESERVED 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED
Byte 4: Control Register 4 Bit @Pup Name Description 7 1 RESERVED RESERVED 6 1 SRC1_OE Output enable for SRC1 0 = Output Disabled, 1 = Output Enabled 5 1 SRC2_OE Output enable for SRC2 0 = Output Disabled, 1 = Output Enabled 4 1 RESERVED RESERVED 3 1 RESERVED RESERVED 2 1 RESERVED RESERVED 1 1 PLL1_SS_EN Enable PLL1s spread modulation, 0 = Spread Disabled, 1 = Spread Enabled 0 1 RESERVED RESERVED Byte 5: Control Register 5 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 6: Control Register 6 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 0 RESERVED RESERVED 0 0 RESERVED RESERVED Byte 7: Vendor ID Bit @Pup Name Description 7 0 Rev Code Bit 3 Revision Code Bit 3 6 0 Rev Code Bit 2 Revision Code Bit 2 5 1 Rev Code Bit 1 Revision Code Bit 1 4 1 Rev Code Bit 0 Revision Code Bit 0 3 1 Vendor ID bit 3 Vendor ID Bit 3 2 0 Vendor ID bit 2 Vendor ID Bit 2 1 0 Vendor ID bit 1 Vendor ID Bit 1 0 0 Vendor ID bit 0 Vendor ID Bit 0
Byte 8: Control Register 8 Bit @Pup Name Description 7 1 Device_ID3 RESERVED 6 0 Device_ID2 RESERVED 5 0 Device_ID1 RESERVED 4 0 Device_ID0 RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 9: Control Register 9 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 1 RESERVED RESERVED 4 0 TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N 3 0 TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 2 1 12C_VOUT<2> I2C_VOUT[2:0] 000 = 0.30V 001 = 0.40V 010 = 0.50V 011 = 060V 100 = 0.70V 101 = 0.80V (default) 110 = 0.90V 111 = 1.00V 1 0 12C_VOUT<1> 0 1 12C_VOUT<0> Byte 10: Control Register 10 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED 2 0 RESERVED RESERVED 1 1 RESERVED RESERVED 0 1 RESERVED RESERVED Byte 11: Control Register 11 Bit @Pup Name Description 7 0 RESERVED RESERVED 6 0 RESERVED RESERVED 5 0 RESERVED RESERVED 4 0 RESERVED RESERVED 3 0 RESERVED RESERVED
1 1 PCI-E_GEN2 PCI-E_Gen2 Compliant 0 = non Gen2, 1= Gen2 Compliant 0 1 RESERVED RESERVED Byte 11: Control Register 11 (continued) Byte 12: Byte Count Bit @Pup Name Description 7 0 BC7 Byte count register for block read operation. The default value for Byte count is 14. In order to read more than 14 bytes, the system BIOS needs to change this register to the number of bytes to be read.
60 B C 6
50 B C 5
40 B C 4
31 B C 3
21 B C 2
11 B C 1
01 B C 0
Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage – 4.6 V VIN Input Voltage Relative to V SS –0.5 4.6 V DC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional -40 85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Mil-STD-883E Method 1012.1 – 20 °C/ W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/ W ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V UL-94 Flammability Rating At 1/8 in. V–0 MSL Moisture Sensitivity Level 1 Parameter Description Condition Min. Max. Unit VDD 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V V IH 3.3V Input High Voltage 2.0 V DD + 0.3 V VIL 3.3V Input Low Voltage V SS – 0.3 0.8 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VILI2C Input Low Voltage SDATA, SCLK – 1.0 V IIH Input High Leakage Current Except internal pull-down resistors, 0 < V IN < VDD –5 A IIL Input Low Leakage Current Except internal pull-up resistors, 0 < VIN < VDD –5 – A VOH 3.3V Output High Voltage I OH = –1 mA 2.4 – V VOL 3.3V Output Low Voltage I OL = 1 mA – 0.4 V IOZ High-impedance Output Current –10 10 A CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance 6p F LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7V DD VDD V VXIL Xin Low Voltage 0 0.3V DD V IDD3.3V Dynamic Supply Current – 40 mA
Parameter Description Condition Min. Max. Unit Crystal TDC XIN Duty Cycle The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification 47.5 52.5 % TPERIOD XIN Period When XIN is dr iven from an external clock source 69.841 71.0 ns TR/TF XIN Rise and Fall Times Measured between 0.3V DD and 0.7VDD –1 0 . 0 n s TCCJ XIN Cycle to Cycle Jitter As an average over 1- s duration – 500 ps SRC TDC SRC Duty Cycle Measured at 0V differential 45 55 % TPERIOD 100 MHz SRC Period Measured at 0V differential @ 0.1s 9.99900 10.0010 ns TPERIODSS 100 MHz SRC Period, SSC Measured at 0V differential @ 0.1s 10.02406 10.02607 ns TPERIODAbs 100 MHz SRC Absolute Period Measured at 0V differential @ 1 clock 9.87400 10.1260 ns TPERIODSSAbs 100 MHz SRC Absolute Period, SSC Meas ured at 0V differential @ 1 clock 9.87406 10.1762 ns TSKEW SRC1 to SRC2 Measured at 0V differential 100 ps TCCJ SRC Cycle to Cycle Jitter Measured at 0V differential – 50 ps RMSGEN1 Output PCIe* Gen1 REFCLK phase jitter BER = 1E-12 (including PLL BW 8 - 16 MHz, ζ = 0.54, Td=10 ns, Ftrk=1.5 MHz) 01 0 8 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 0 p s RMSGEN2 Output PCIe* Gen2 REFCLK phase jitter Includes PLL BW 8 - 16 MHz, Jitter Peaking = 3dB, ζ = 0.54, Td=10 ns), Low Band, F < 1.5MHz 03 . 1 p s RMSGEN3 Output phase jitter impact – PCIe* Gen3 Includes PLL BW 2 - 4 MHz, CDR = 10MHz) 01 . 0 p s LACC SRC Long Term Accuracy Measured at 0V differential – 100 ppm TR / TF SRC Rising/Falling Slew Rate Measured differentially from ±150 mV 2.5 8 V/ns TRFM Rise/Fall Matching Measured single-endedly from ±75 mV – 20 % VHIGH Voltage High 1.15 V VLOW Voltage Low –0.3 – V VOX Crossing Point Voltage at 0.7V Swing 300 550 mV Tjphasepll Phase Jitter (PLL BW 8-16MHz, 5-16MHz) RMS value 3.1 pS ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up – 1.8 ms TSS Stopclock Set-up Time 10.0 – ns
Ordering Information
Part Number Package Type Product Flow Lead-free SL28SRC02BZI 20-pin TSSOP Industrial, -40 to 85C SL28SRC02BZIT 20-pin TSSOP–Tape and Reel Industrial, -40 to 85C VMIN = 0.30V VMIN = 0.30V Vcross MIN = 300mV Vcross MAX = 550mV Vcross MIN = 300mV Vcross MAX = 550mV VMAX = 1.15V VMAX = 1.15V CLK# CLK CLK# Vcross delta = 140mV Vcross delta = 140mV CLK CLK# CLK# CLK Vcross median Vcross median Vcross median +75mV Vcross median -75mV TriseTfall Figure 5. Single-ended Measurement for Differential Output Signals (for AC Parameters Measurement)
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Sil- icon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, repre- sentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse- quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized appli- cation, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Document History Page Document Title: SL28SRC02 PCI Express Gen 2 & Gen 3 Clock Generator REV. Issue Date Orig. of Change Description of Change 1.0 10/28/09 JMA New Datasheet 1.1 11/06/09 JMA Updated Figure 4