CR1210-2W-1000F

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Rev. 1.1 4/16 Copyright © 2016 by Silicon Laboratories Si3402B-EVB Si3402B-EVB NON -I SOLATED E VALUATION B OARD FOR THE Si3402B 1. Description The Si3402B non-isolated evaluation board (Si3402B-EVB Rev 2) is a refer ence design for a power supply in a Power over Ethernet (PoE) Powered Device (PD) applicat ion. The Si3402B is described more completely in the data sheet and application notes. This document de scribes the evaluation boa rd. An evaluation board demonstrating the isolated application is described in the Si3402B-ISO-EVB user’s guide. 2. Si3402B Board Interface Ethernet data and power are applied to the board thro ugh the RJ45 connector (J1). The board itself has no Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out to the test points. Power may be applied in the following ways:  Connecting a dc source to pins 1, 2 and 3, 6 of the Ethernet cable (either polarity)  Connecting a dc source to pins 4, 5 and 7, 8 of the Ethernet cable (either polarity)  Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS The Si3402B-EVB board schematics and layout are shown in Figures 1 through 6. The dc outpu t is at connectors J11(+) and J12(–). Boards are generally shipped configured to produce +5 V output voltage but can be configured for +3.3 V or other output voltages by changing resistors R5 and R6. Re fer to “AN956: Using the Si3402B PoE PD Controller in Isolated and Non-Isolated Designs” for more informat ion. The preconfigured Class 3 signature can also be modified according to Table 3 in AN956. The D8–D15 Schottky type diode bridge bypass is recommended only for higher power levels (Class 3 operati on). For lower power levels, such as Class 1 and Class 2, the diodes can be removed. When the Si3402B is used in external diode bridge configuration, it requires that at least one pair of the CTx and SPx pins be connected to the PoE voltage input terminals (to the input of the external bridge).

Vpos is a EMI and ESD plane. Use top layer. Vneg is a thermal plane as wel as ESD and EMI. on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. SP1/SP2 should be connected.

330 Ohm

30 Ohm

Figure 1. Si3402B Schematic—5 V, Class 3 PD

Figure 2. Top Silkscreen

Figure 3. Top Layer

Figure 4. Internal 1 (Layer 2)

Figure 5. Internal 2 (Layer 3)

Figure 6. Bottom Layer

(D8–D15) can be removed to reduce BOM costs. Table 1. Si3402B-EVB Bill of Materials

100 V ±10% X7R C0603 C0603X7R101-102K Venkel

1 PDS5100 D1 5 A 100 V Schottky POWERDI-5 PDS5100H-13 Diodes Inc.

8 SS2150 D8, D9, D10,

2 A 150 V Single DO-214AC SS2150-LTP MCC

1 RJ-45 J1 Receptacle RJ45-SI-52004 SI-52003-F Bel

2 BND_POST J11, J12 15 A Banana Banana Jack 101 Abbatron Hh

*Note: C10–C17 are populated by default. See the “Surge” section in AN956 for more information.

Rev. 1.1 9 4. BOM Options The Si3402B non-isolated EVB has been compensated for eight different output voltage and filter combinations:  3.3 V output standard ESR 1000 µF 6.3 V filter  5 V output standard ESR 1000 µF 6.3 V filter  9 output standard ESR 470 µF 16 V filter  12 V output standard ESR 470 µF 16 V filter  3.3 V output low ESR 560 µF 6.3 V filter  5 V output low ESR 560 µF 6.3 V filter  9 V output low ESR 330 µF 16 V filter  12 V output low ESR 330 µF 16 V filter For the standard ESR capacito r, the ESR increase at very low temperatures may caus e a loop stability issue. A typical evaluation board has been shown to exhibit instability under ve ry heavy loads at –20 °C. Due to self-heating, this condition is not a great concern. Howeve r, using a low ESR filter ca pacitor solves this problem (but requires some recompensation of the feedback loop ). The low ESR capacitor also improves load transient response and output ripple. The Si3402B (non–isolated) EVB was designed with a very simple compensation consisting of R7 and C7. The standard evaluation board is optimized for a standard ESR filter capacitor for 5 V output. The following table gives the options that have been tested for other situations. VOUT (To Adjust Output Voltage) Filter Cap C5 (Type FM are Low ESR) Filter Cap Part Number (Panasonic) R7 C7 3.3 V 4.64 k  1 0 0 0µ F , 6 . 3V E C A 0 J M 1 0 2 4 7k  1n F 3.3 V 4.64 k  560 µF, 6.3 V EEUFM0J561 47 k  1n F 5.0 V 8.66 k  1 0 00µ F , 6 . 3V E C A 0 J M 1 0 2 4 7k  1n F 5.0 V 8.66 k  560 µF, 6.3 V EEUFM0J561 47 k  1n F 9.0 V 18.2 k  470 µF, 16 V ECA1CM471 47 k  1n F 9.0 V 18.2 k  330 µF, 16 V EEUFM1C331 47 k  1n F 12.0 V 25.5 k  470 µF, 16 V ECA1CM471 47 k  1n F 12.0 V 25.5 k  330 µF, 16 V EEUFM1C331 47 k  1n F

10 Rev. 1.1 APPENDIX —Si3402B D ESIGN AND L AYOUT C HECKLIST Introduction Although the EVB design is pre-configured as a Class 3 PD with 5 V output, the schematics and layouts can easily be adapted to meet a wide variety of common output voltages and power levels. The complete EVB design databases for the stan dard 5 V/Class 3 config uration are located at www.silabs.com/PoE under the “Documentation” link. Silicon Labs strongly reco mmends using these EVB schematics and layout files as a starting point to ens ure robust performance and avoid common mistakes in the schematic capture and PCB layout processes. Following are recommended design checklists that can assist in trouble-free development of robust PD designs. Refer also to the Si3402B data sheet and AN956 when using the following checklists. 1. Design Planning Checklist: a. Determine if your design requires an isolated or non-isolated topology. For more information, see Section 4 of AN956. b. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you begin integrating the Si3402B into your system design process. c. Determine your load’s power requirements (i.e., V OUT and IOUT consumed by the PD, including the typical expected transient surge conditions). In general, to achieve the highest overall efficiency performance of the Si3402B, choose the highest voltage used in your PD and then post regulate to the lower supply rails, if necessary. d. If your PD design consumes > 7 W, be sure to bypass the Si3402B’s on-chip diode bridges with external Schottky diode bridges or discrete diodes. Bypassing the Si3402B’s on-chip diode bridges with external bridges or discrete Schottky diodes is required to help spread the heat generated in designs dissipating >7W . e. Based on your required PD power level, select the appropriate class resistor value by referring to Table 3 of AN956. This sets the Rclass resistor (R3 in Figure 1 on page 2). 2. General design checklist items: a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD (IEC6100-4-2) must provide >15 kV tolerance. b. If your design uses an AUX supply, be sure to include a 3 W surge limiting resistor in series with the AUX supply for hot insertion. Refer to AN956 when AUX supply is 48 V. c. Silicon Labs strongly recommen ds the inclusion of a minimum load (250 mW) to avoid switcher pulsing when no load is present and to avoid false disconnection when less than 10 mA is drawn from the PSE. If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW. d. If using PLOSS function, make sure it’s properly te rminated for connection in your PD subsystem. If PLOSS is not needed, leave this pin floating. 3. Layout guidelines: a. Make sure VNEG pin of the Si3402B is connected to the backside of the QFN package with an adequate thermal plane, as noted in the data sheet and AN956. b. Keep the trace length from connecting to SWO and re tuning to Vss2 as short as possible. Make all of the power (high current) traces as short, direct, and thick as possible. It is a good practice on a standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere. c. Usually, one standard via handles 200 mA of current. If the trace needs to conduct a significant amount of current from one plane to the other, use multiple vias.

Rev. 1.1 11 d. Keep the circular area of the loop from the Swit cher FET output to the inductor or transformer and returning from the input filter capacitors (C1–C4) to Vss2 as small a diameter as possible. Also, minimize the circular area of the loop from the output of the inductor or transformer to the Schottky diode and returning through the first stage output filter capacitor back to the inductor or transformer as small as possible. If possible, keep the direction of current flow in these two loops the same. e. Keep the high power traces as short as possible. f. Keep the feedback and loop st ability components as far from the transformer/inductor and noisy power traces as possible. g. If the outputs have a ground plane or positive out put plane, do not connect the high current carrying components and the filter capacitors through the plane. Connect them together, and then connect to the plane at a single point. h. As a convenience in layout, please note that the IC is symmetrical with respect to CT1, CT2, SP1, and SP2. These leads can be interchanged. At least one pair of CT1/CT2 or SP1/SP2 should be connected. To help ensure first-pass success, submit your schematics and layout files to PoEInfo@silabs.com for review. Other technical questions may be sent to this e-mail address as well.

12 Rev. 1.1 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1  Initial release of Si3402B-EVB User’s Guide, modified from Si3402-EVB User’s Guide Revision 1.0.

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