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© 2014 Silicon Laboratories, Inc. All rights reserved.

FEATURES

 Ultra Low Supply Current: 1.9 μA at 25kHz  Supply Voltage Operation: 1.55V to 5.25V  Single Resistor Sets FOUT at 50% Duty Cycle  FOUT Period:  9kHz ≤ FOUT ≤ 300kHz  Single Resistor Sets Output Frequency  FOUT Period Accuracy: 3%  FOUT Period Drift: 0.02%/ºC  FOUT Output Driver Resistance: 160 Ω

APPLICATIONS

Portable and Battery-Powered Equipment Low-Parts-Count Nanopower Oscillator Compact Micropower Replacement for Crystal and Ceramic Oscillators Micropower Pulse-width Modulation Control Micropower Pulse-position Modulation Control Micropower Clock Generation Micropower Sequential Timing

DESCRIPTION

The TS3006 is a single-supply, second-generation oscillator/timer fully specifi ed to operate at a supply voltage range of 1.55V to 5.25V while consuming less than 2.4 μA(max) supply current. Requiring only a resistor to set the base output frequency (or output period) at 25kHz (or 40µs) with a 50% duty cycle, the TS3006 timer/oscillator is compact, easy-to-use, and versatile. Optimized for ultra-long life, low frequency, battery-powered/portable applications, the TS3006 joins the TS3001, TS3002, TS3004, and TS3005 in the CMOS timer family of “NanoWatt Analog™” high- performance analog integrated circuits. The TS3006 output frequency can be user-adjusted from 9kHz to 300kHz with a single resistor. In addition, the TS3006 represents a 25% reduction in pcb area and a factor-of-10 lower power consumption over other CMOS-based integrated circuit oscillators/timers. When comp ared against industry- standard 555-timer-based products, the TS3006 offers up to 84% reduction in pcb area and over three orders of magnitude lower power consumption. The TS3006 is fully specified over the -40°C to +85°C temperature range and is available in a low-profile, 8-pin 3x3mm TDFN package with an exposed back- side paddle. A 1.55V to 5.25V, 1.9µA, 9kHz to 300kHz Silicon Timer TYPICAL APPLICATION CIRCUIT

Page 2 TS3006 Rev. 1.0 ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the op erational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING CARRIER QUANTITY TS3006ITD833 3006I Tape & Reel ----- TS3006ITD833T Tape & Reel 3000 Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges.

TS3006 Rev. 1.0 Page 3

ELECTRICAL CHARACTERISTICS

VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. See Note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD 1.55 5.25 V Supply Current IDD 1.9 2.4 µA FOUT Period tFOUT 39 40.1 41.2 µs -40°C ≤ TA ≤ 85°C 38 42 FOUT Period Line Regulation ∆tFOUT/V 1.55V ≤ VDD ≤ 5.25V 0.17 %/V FOUT Duty cycle 49 51 % FOUT Period Temperature Coefficient FOUT/∆T 0.02 %/°C UVLO Hysteresis VUVLO (V DD=1.55V) – (VDD_SHUTDOWN VOLTAGE) 150 250 mV FOUT Rise Time tRISE See Note 2, C L = 15pF 10 ns FOUT Fall Time tFALL See Note 2, C L = 15pF 10 ns FOUT Jitter See Note 3 0.001 % RSET Pin Voltage V(RSET) 0.3 V Maximum Oscillator Frequency Fosc RSET= 360K 300 kHz High Level Output Voltage, FOUT V DD - VOH I OH = 1mA 160 mV Low Level Output Voltage, FOUT V OL I OL = 1mA 140 mV Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: Output rise and fall times are measured between the 10% and 90% of the VDD power-supply voltage levels. The specification is based on lab bench characterization and is not tested in production. Note 3: Timing jitter is the ratio of the peak-to-peak variation of the period to the mean of the period. The specification is based on lab bench characterization and is not tested in production.

Page 4 TS3006 Rev. 1.0 PERIOD - µs SUPPLY CURRENT - µA 20 40 Supply Current vs FOUT Period 0 60 80 100 SUPPLY VOLTAGE - Volt PERIOD - µs 2.29 3.03 40.12 40.1 40.18 FOUT Period vs Supply Voltage 1.55 3.77 40.14 40.16 4.51 CLOAD- pF SUPPLY CURRENT - µA 10 20 Supply Current vs CLOAD(FOUT) 0 30 5.25 TEMPERATURE - ºC SUPPLY CURRENT - µA 2.1 1.7 Supply Current vs Temperature 2.3 2.5 1.9 -15 10 -40 35 60 85 SUPPLY VOLTAGE - Volt START-UP TIME - ms Start-up Time vs Supply Voltage TEMPERATURE - ºC PERIOD - µs -15 10 39.5 FOUT Period vs Temperature -40 35 60 85 40.5 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. 40.2

TS3006 Rev. 1.0 Page 5 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, VPWM_CNTRL= VDD, RSET = 4.32MΩ, RLOAD(FOUT) = Open Circuit, CLOAD(FOUT) = 0pF unless otherwise noted. Values are at TA = 25°C unless otherwise noted. RSET - MΩ PERIOD - µs 2 4 100 Period vs RSET 0 6 8 10 PERCENT OF UNITS - % SUPPLY CURRENT - µA Supply Current Distribution 1.95 10% 15% 20% 25% 30% 35% 1.97 1.99 2.01 FOUT VDD = 3V, CLOAD = 15pF 5µs/DIV FOUT VDD = 5V, CLOAD = 15pF 5µs/DIV FOUT 1V/DIV FOUT 1V/DIV 120

Page 6 TS3006 Rev. 1.0 PIN FUNCTIONS PIN NAME FUNCTION

1 FOUT

Fixed Frequency Output. A push-pull output stage with an output resistance of 160 Ω. FOUT pin swings from GND to VDD. For lowest power operation, capacitance loads should be minimized and resistive loads should be maximized. 2 NC Non-Connect. 3,4,5,6 GND Ground. Connect this pin to the system’s analog ground plane.

7 VDD

Power Supply Voltage Input. The supply voltage range is 1.55V ≤ VDD ≤ 5.25V. Bypass this pin with a 0.1uF ceramic coupling capacitor in close proximity to the TS3006.

8 RSET

FOUT Programming Resistor Input. A 4.32MOhm resistor connected from this pin to ground sets the T3003’s internal oscillator’s output period to 40µs (25KHz). For optimal performance, the composition of the RSET resistor shall be consistent with a tolerance of 1% or lower. The RSET pin voltage is approximately 0.3V. BLOCK DIAGRAM

TS3006 Rev. 1.0 Page 7 THEORY OF OPERATION The TS3006 is a user-programmable oscillator where the period of the square wave at its FOUT terminal is generated by an external resistor connected to the RSET pin. The output frequency is given by: FOUT (kHz) ൌ 1.08E11 RSET Equation 1. FOUT Frequency Calculation With an R SET = 4.32M Ω, the output frequency is approximately 25kHz with a 50% duty cycle. As design aids, Tables 1 lists TS3006’s typical FOUT for various standard values for R SET. Connect CPWM to VDD to disable the PWM function and in turn, save power. Connect PWM_CNTRL to VDD for a fixed PWMOUT out put pulse width, which is determined by the CPWM pin capacitor only. APPLICATIONS INFORMATION Minimizing Power Consumption To keep the TS3006’s power consumption low, resistive loads at the FOUT and PWMOUT terminals increase dc power consumption and therefore should be as large as possible. Capacitive loads at the FOUT and PWMOUT terminals increase the TS3006’s transient power consumption and, as well, should be as small as possible. One challenge to minimizing the TS3006’s transient power consumption is the probe capacitance of oscilloscopes and frequency counter instruments. Most instruments exhibit an input capacitance of 15pF or more. Unless buffered, the increase in transient load current can be as much as 400nA. To minimize capacitive loading, the technique shown in Figure 1 can be used. In this circuit, the principle of series-connected capacitors can be used to reduce the effective capacitive load at the TS3006’s FOUT and PWMOUT terminals. To determine the optimal value for C EXT once the probe capacitance is known by simply solving for C EXT using the following expression: For example, if the instrument’s input probe capacitance is 15pF and the desired effective load capacitance at either or both FOUT and PWMOUT terminals is to be ≤5pF, then the value of CEXT should be ≤7.5pF. TS3006 Start-up Time As the TS3006 is powered up, its FOUT terminal (and PWMOUT terminal, if enabled) is active once the applied VDD is higher than 1.55V. Once the applied VDD is higher than 1.55V, the master oscillator achieves steady-state operation within 8ms. RSET (MΩ) FOUT (kHz) 0.360 300 1 108 2.49 43.37 4.32 25 6.81 15.86 9.76 11.07 12 9 Table 1: FOUT vs RSET CEXT = 1 CLOAD(EFF) - 1 CPROBE Equation 2: External Capacitor Calculation Figure 1: Using an External Capacitor in Series with Probes Reduces Effective Capacitive Load.

Page 8 TS3006 Rev. 1.0 Using a Potentiometer to Trim the TS3006’s Output Frequency By using a fixed resistor and a potentiometer, the output frequency of the TS3006 can be trimmed as shown in Figure 2. By selecting a fixed resistor R1 with a tolerance of 0.1% and a potentiometer P1 with a 5% tolerance, the output frequency can be trimmed to provide a ±2% trimming range Figure 2: Using a Fixed Resistor and a Potentiometer to Trim the TS3006’s Output Frequency.

Silicon Laboratories, Inc. Page 9 400 West Cesar Chavez, Austin, TX 78701 TS3006 Rev. 1.0 +1 (512) 416-8500 ▪ www.silabs.com PACKAGE OUTLINE DRAWING Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 8-Pin TDFN33 Package Outline Drawing (N.B., Drawings are not to scale)

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