TS12012

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FEATURES

 NanoWatt Analog™ Op Amp, Comparator, and 0.58V Reference in Single 4 mm2 Package  Ultra Low Total Supply Current: 1.6µA (max)  Supply Voltage Range: 0.8V to 2.5V  Internal 0.58V Reference  Op Amp and Comparator Input Ranges are Rail-to-Rail  Unity-gain Stable Op Amp with A VOL = 104dB  Op Amp Output: Rail-to-Rail and Phase- Reversal-Free  Internal ±7.5mV Co mparator Hysteresis  20µs Comparator Propagation Delay  Resettable Latched Comparator  TS12011: Push-pull Rail-to-Rail Output TS12012: Open-drain Output

APPLICATIONS

Single-Cell and +1.8V, +2.5V Powered Systems Low-Frequency, Local-Area Alarms/Detectors Smoke Detectors and Safety Sensors Infrared Receivers for Remote Controls Instruments, Terminals, and Bar-Code Readers Smart-Card Readers

DESCRIPTION

The TS12011/TS12012 combine a 0.58V reference, a 20µs comparator, and a unity-gain stable op amp in a single IC. All three devices operate from a single 0.8V to 2.5V power supply and consume less than 1.6µA total supply current. Supply current for all three functions over 0.8V to 2.5V supply range is guaranteed 1.6µA max. Super-flexible for crafting voltage detectors, timers, and wake-up circuits, these bundled functions exhibit low shoot-through currents an d graceful power-down modes. Both the comparator and the op amp feature rail-to-rail input stages. The latching comparator exhibits ±7.5mV of internal hysteresis for clean, chatter-free output switching. When compared against similar products, the TS12011/TS12012 offer a factor-of-20 lower power consumption and at least a 55% reduction in pcb area. The TS12011’s comparator has a push-pull output stage with break-before-make switches for low shoot- through currents. The TS12012’s comparator has an open-drain output having no parasitic diode to VDD, for interfacing to wired-OR or mixed-voltage logic. The TS12011 and the TS12012 are fully specified over the -40°C to +85°C temperature range and each is available in a low-profile, 10-pin 2x2mm TDFN package with an exposed back-side paddle. A 0.8V/1.5µA Nanopower Op Amp, Comparator, and Reference TYPICAL APPLICATION CIRCUIT Part Number Comparator Output Stage TS12011 Push-pull TS12012 Open-Drain

Page 2 TS12011/12 Rev. 1.0 ABSOLUTE MAXIMUM RATINGS Input Voltage AMPIN+, AMPIN-…………………….….V SS – 0.3V to VDD + 0.3V Output Voltage Output Current Short-Circuit Duration (REFOUT, AMPOUT, COMPOUT)………………...….Continuous Continuous Power Dissipation (TA = +70°C) Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKING CARRIER QUANTITY ORDER NUMBER PART MARKING CARRIER QUANTITY TS12011ITD1022 AAL Tape & Reel ----- TS12012ITD1022 AAM Tape & Reel ----- TS12011ITD1022T Tape & Reel 3000 TS12012ITD1022T Tape & Reel 3000 Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges.

TS12011/12 Rev. 1.0 Page 3

ELECTRICAL CHARACTERISTICS

VDD = 0.8V; VSS = 0V; VCOMPIN+/- = 0V; VAMPIN+/- = 0V; VAMPOUT = (VDD + VSS)/2; VCOMPOUT = HiZ; TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. See note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VDD 0.8 2.5 V Supply Current IDD REFOUT = open TA = +25°C 1.1 1.6 µA -40°C ≤ TA ≤ 85°C 2 REFERENCE SECTION Reference Output Voltage VREFOUT V DD = 0.8V or 2.5V TA = +25°C 555 577 600 mV -40°C ≤ TA ≤ 85°C 552 602 Reference Load Regulation I OUT = ±100nA 0.5 % AMPLIFIER SECTION Input Offset Voltage V OS V AMPIN+/- = VDD or VAMPIN+/- = VSS TA = +25°C 3.5 mV Input Bias Current I IN+, IN- V AMPIN+, VAMPIN- = (VDD – VSS)/2 20 nA Input Offset Current I OS V AMPIN+, VAMPIN- = (VDD – VSS)/2 0.01 5 nA Input Common-Mode Range IVR Guaranteed by Input Offset Voltage Test V SS V DD V Large-Signal Voltage Gain A VOL RL = 100K to VDD/2; VSS + 50mV < VOUT < VDD - 50mV 90 104 dB Gain-Bandwidth Product GBWP R L = 100kΩ//20pF 15 kHz Phase Margin φM R L = 100kΩ//20pF 70 deg Slew Rate SR R L = 100kΩ//20pF 6 V/ms Common-Mode Rejection Ratio CMRR 0V ≤ V IN(CM) ≤ 2.1V; VDD = 2.5V 50 75 dB Power-Supply Rejection Ratio PSRR 0.65V ≤ (V DD - VSS) ≤ 2.5V 50 75 dB Output High Voltage V OH R L = 100kΩ to VSS V DD – 50mV V Output Low Voltage V OL R L = 100kΩ to VDD VSS + 50mV V Output Source Current I SC+ V AMPOUT = VSS 0.28 mA Output Sink Current I SC- V AMPOUT = VDD 4.5 mA Output Load Capacitive Drive C OUT 50 pF COMPARATOR SECTION Input Offset Voltage V OS VAMPIN+/- = VDD; VAMPIN+/- = VSS; See Note 2 TA = +25°C 4.5 mV Input Hysteresis VHB See Note 3 ±7.5 mV Input Bias Current I IN+, IN- V COMPIN+, VCOMPIN- = VDD or VSS 20 nA Input Offset Current I OS V COMPIN+, VCOMPIN- = VDD or VSS 0.2 5 nA Input Voltage Range IVR Guaranteed by Input Offset Voltage Test VSS V DD V Common-Mode Rejection Ratio CMRR 0V ≤ V IN(CM) ≤ 2.1V; VDD = 2.5V 50 60 dB Power-Supply Rejection Ratio PSRR 0.8V ≤ (V DD - VSS) ≤ 2.5V 50 70 dB Low-to-High Propagation Delay tPD+ VOVERDRIVE = 10mV; See Note 4 TS12011 30 µs VOVERDRIVE = 100mV; See Note 4 20 µs High-to-Low Propagation Delay tPD- VOVERDRIVE = 10mV; See Note 4 30 µs VOVERDRIVE = 100mV; See Note 4 20 µs Output High Voltage V OH TS12011; I OUT = -100μA V DD – 0.1 V Output Low Voltage V OL TS12011 ; I OUT = 100μA VSS + 0.1 V Output Low Voltage V OL TS12012 ; I OUT = 100μA VSS + 0.11 V Output Short-Circuit Current I SC Sourcing; VCOMPOUT = VSS 0.1 mA TS12011 ; Sinking; VCOMPOUT = VDD 0.5 mA TS12012 ; Sinking; VCOMPOUT = VDD 1.4 mA Open Drain Leakage TS12012 ; V COMPOUT = 5V 20 nA

Page 4 TS12011/12 Rev. 1.0 VDD = 0.8V, VSS = 0V, VCOMPIN+/- = 0V, VAMPIN+/- = 0V, VAMPOUT = (VDD + VSS)/2, VCOMPOUT = HiZ. TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. See note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONTROL PIN SECTION LHDETതതതതതതതതതത Input Low Voltage VIL Comparator Latched Output Enabled LHDETതതതതതതതതതത Input High Voltage VIH Comparator Latched Output Disabled 0.8V ≤ V DD ≤ 1.1V V DD - 0.1 V 1.1V < VDD ≤ 2.5V 1 LHDETതതതതതതതതതത Input Leakage VLHDETതതതതതതതതതത = VSS; VLHDETതതതതതതതതതത = 5.5V 100 nA Note 1: All devices are 100% production tested at TA = +25°C and are guaranteed by characterization for TA = TMIN to TMAX, as specified. Note 2: VOS is defined as the center of the hysteresis band at the input minus VIN(CM). Note 3: The hysteresis-related trip points are defined by the edges of the hysteresis band and measured with respect to the center of the hysteresis band. Note 4: The propagation delays are specified with an output load capacitance of CL = 15pF. VOVERDRIVE is defined above and is beyond the offset voltage and hysteresis of the comparator input.

TS12011/12 Rev. 1.0 Page 5 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5V; VSS = 0V; VAMPOUT = HiZ; VCOMPOUT = HiZ, unless otherwise noted. Typical values are at TA = +25°C. SUPPLY VOLTAGE - V SUPPLY CURRENT - µA 1.23 1.65 1.2 0.8 Supply Current vs Supply Voltage and Temperature 0.8 2.08 1.4 1.6 2.5 SUPPLY VOLTAGE - V SHORT-CIRCUIT CURRENT - mA 1.23 1.65 Op Amp Short-Circuit Current vs Supply Voltage 0.8 2.08 2.5 SUPPLY VOLTAGE - V SHORT-CIRCUIT CURRENT - mA Comparator Short-Circuit Current vs Supply Voltage TEMPERATURE - ºC REFERENCE VOLTAGE - V -15 10 0.583 0.581 Reference Voltage vs Temperature -40 35 0.585 60 85 0.587 0.589 TA = +85ºC TA = +25ºC TA = -40ºC VAMPOUT = VSS VCOMPOUT = VSS SUPPLY VOLTAGE - V SHORT-CIRCUIT CURRENT - mA 1.23 1.65 Op Amp Short-Circuit Current vs Supply Voltage 0.8 2.08 38.5 25.5 2.5 SUPPLY VOLTAGE - V SHORT-CIRCUIT CURRENT - mA Comparator Short-Circuit Current vs Supply Voltage VAMPOUT = VDD VCOMPOUT = VDD

Page 6 TS12011/12 Rev. 1.0 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5V; VSS = 0V; VAMPOUT = HiZ; VCOMPOUT = HiZ, unless otherwise noted. Typical values are at TA = +25°C. SOURCE CURRENT - mA VDD - VOH - V 1 2 0.4 Comparator Output Voltage High vs Source Current 0 3 0.6 0.2 SINK CURRENT - mA VOL - V 1 2 0.1 Comparator Output Voltage Low vs Sink Current 0 3 0.2 0.3 0.4 SOURCE CURRENT - mA VDD - VOH - V 2 4 0.1 0.4 Op Amp Output Voltage High vs Source Current 0 6 0.2 0.3 SINK CURRENT - mA VOL - V 2 4 0.14 0.07 0.35 0 6 0.21 0.28 Op Amp Output Voltage Low vs Sink Current 0.5 0.6 SUPPLY VOLTAGE - V INPUT OFFSET VOLTAGE - µV -200 -300 100 -100 200 Op Amp Input Offset Voltage vs Supply Voltage 300 VINCM = VDD VINCM = VSS SUPPLY VOLTAGE - V INPUT OFFSET VOLTAGE - mV -0.5 0.5 Comparator Input Offset Voltage vs Supply Voltage VINCM = VDD VINCM = VSS

TS12011/12 Rev. 1.0 Page 7 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5V; VSS = 0V; VAMPOUT = HiZ; VCOMPOUT = HiZ, unless otherwise noted. Typical values are at TA = +25°C. TS12011 Comparator Propagation Delay (TPD+) VDD = 2.5V, VOVERDRIVE = 100mV, CLOAD = 15pF 20µs/DIV TS12011 Comparator Propagation Delay (TPD-) VDD = 2.5V, VOVERDRIVE = 100mV, CLOAD = 15pF 20µs/DIV INPUT 50mV/DIV OUTPUT 1V/DIV INPUT 50mV/DIV OUTPUT 1V/DIV SUPPLY VOLTAGE - V INPUT OFFSET VOLTAGE - mV 0.4 0.2 0.8 0.6 Op Amp Input Offset Voltage vs Input Common-Mode Voltage 0.2 0.4 0 0.6 0.8 VDD = 0.8V SUPPLY VOLTAGE - V INPUT OFFSET VOLTAGE - mV 0.5 0.4 0.8 0.6 0.7 Op Amp Input Offset Voltage vs Input Common-Mode Voltage 0.5 1 01 . 5 2 VDD = 2.5V 2.5 TS12011 Op Amp Small-Signal Transient Response VDD = 2.5V, RLOAD = 100kΩ, CLOAD = 15pF 200µs/DIV TS12011 Op Amp Large Signal Transient Response VDD = 2.5V, RLOAD = 100kΩ, CLOAD = 15pF 500µs/DIV INPUT 50mV/DIV OUTPUT 50mV/DIV INPUT 1V/DIV OUTPUT 1V/DIV

Page 8 TS12011/12 Rev. 1.0 PIN FUNCTIONS PIN TS12011 PIN TS12012 NAME FUNCTION 1 1 AMPOUT Amplifier Output 2 2 AMPIN- Amplifier Inverting Input 3 3 AMPIN+ Amplifier Non-inverting Input 4 4 VSS Negative Supply Voltage. 5 5 LHDETതതതതതതതതതതതതത Latch Enable Pin, active low. Tie to VDD for normal operation. Do not leave floating. See Latch Truth Tables below. 6 8 COMPIN+ Comparator Non-inverting Input 7 7 REFOUT 0.58V Reference Output 8 6 COMPIN- Comparator Inverting Input 9 9 COMPOUT Comparator Output. TS12011: push-pull TS12012: open-drain 10 10 VDD Positive Supply Voltage. Connect a 0.1µF bypass capacitor from this pin to analog VSS/GND. EP EP ---- Exposed paddle is elec trically connected to VSS/GND. TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5V; VSS = 0V; VAMPOUT = HiZ; VCOMPOUT = HiZ, unless otherwise noted. Typical values are at TA = +25°C. FREQUENCY - Hz PHASE - Degrees -150 -200 -100 -50 -250 Gain and Phase vs Frequency 1k 10k100 100k 100 -10 -20 GAIN - dB GAIN PHASE 70º 14kHzVDD = 0.8V TA = +25ºC RL = 100kΩ CL = 20pF AVCL = 1000V/V

TS12011/12 Rev. 1.0 Page 9 BLOCK DIAGRAM THEORY OF OPERATION The TS12011 and TS12012 are multi-purpose CMOS building blocks intended for creating analog glue functions around battery-powered uC systems. There is an op amp for signal conditioning, a comparator for detection, and a reference to establish detection threshold levels. It’s possible to build a wide variety of timers, event detectors, regulators, and voltage monitors using these flexible uncommitted blocks. Optimized for low-voltage operation, these devices draw less than 1.6uA total from a 0.8V to 2.5V supply. The op amp and comparator blocks typically continue to function down to less than 0.5V (REFOUT will go into dropout, however). Comparator The comparator block is designed for high gain and chatter-free output switching in noisy environments. The comparator inputs have rail-to-rail VIN range, and exhibit +/-7.5mV of hysteresis. The only difference between the two device types is in the output stage of the comparator. The TS12011 has a push-pull output and latches in the high state. The TS12012 has an open-drain output, latches in the low state, and can tolerate pull-up voltages higher than the supply (up to 5.5V absolute max above VSS/GND). TS12011 push-pull output driver was designed to minimize supply-current surges while driving ±100µA loads with an output swing to within 100mV of the supply rails. The TS12011 and the TS12012 can sink 0.5mA and 1.4mA of current, respectively. The TS12011 can source 0.1mA of current. The non-traditional latch function works to detect and latch changes in the input state. If the LHDETത തതതതതതതതത control input is enabled, the output will latch high (low for the TS12012) whenever the differential input voltage is high enough to force a change in that direction. If the differential voltage is in the wrong direction to force a

Page 10 TS12011/12 Rev. 1.0 change, the comparator stays active and waits for the crossing, at which point it will latch in its final state. An internal POR circuit ensures that the latch powers up in the “comparator active” state if LHDETതതതതതതതതതത is low when VDD is first applied. Latch Truth Table – TS12011 LHDETത തതതതതതതതത CMPOUT initial state CMPIN+ to CMPIN- difference voltage CMPOUT HIGH X N/A Normal operation LOW HIGH X HIGH (latched) LOW LOW negative LOW (comparator active) LOW LOW positive HIGH (latched) X = Don’t Care Latch Truth Table – TS12012 LHDETത തതതതതതതതത CMPOUT initial state CMPIN+ to CMPIN- difference voltage CMPOUT HIGH X N/A Normal operation LOW LOW X LOW (latched) LOW HIGH positive HIGH (comparator active) LOW HIGH negative LOW (latched) X = Don’t Care Reference The TS12011 and TS12012 on-board 0.58V ±4.5% reference voltage can source and sink 0.1µA and 0.1µA of current and can drive a capacitive load less than 50pF and greater than 50nF with a maximum capacitive load of 250nF. The higher the capacitive load, the lower the noise on the reference voltage and the longer the time needed for the reference voltage to respond and become available on the REFOUT pin. With a 250nF capacitive load, the reference voltage will settle to within specifications in approximately 20ms. Op Amp The TS12011 and TS12012 have a unity-gain stable op-amp with a GBWP of 15kHz, a slew rate of 6V/ms, and can drive a capacitive load up to 50pF. The common mode input voltage range extends from V SS to V DD and the input bias current and offset current are less than 20nA and 2nA, respectively. Op-Amp Stability The TS12011 and TS12012 op-amp is able to drive up to 50pF of capacitive load and still maintain stability in a unity-gain configuration with a 15kHz GBWP and a phase margin of 70 degrees with a 100kΩ//20pF output load. Though the TS12011 and TS12012 address low frequency applications, it is essential to perform good layout techniques in order to minimize board leakage and stray capacitance, which is of a concern in low power, high impedance circuits. For instance, a 10MΩ resistor coupled with a 1pF stray capacitance can lead to a pole at approximately 15kHz, which is the GBWP of the device. If stray capacitance is unavoidable, a feedback capacitor can be placed in parallel with the feedback resistor. APPLICATIONS INFORMATION Comparator Hysteresis As a result of circuit noise or unintended parasitic feedback, many analog comparators often break into oscillation within their li near region of operation especially when the applied differential input voltage approaches 0V (zero volt). Externally-introduced hysteresis is a well-established technique for stabilizing analog comparator behavior and requires external components. As shown in Figure 1, adding comparator hysteresis creates two trip points: V THR (for the rising input voltage) and V THF (for the falling input voltage). The hysteresis band (V HB) is defined as the voltage difference between the two trip points. When a comparator’s input voltages are equal, hysteresis effectively forces one comparator input to move quickly past the other input, moving the input out of the region where oscillation occurs. Figure 1 illustrates the case in which an IN- input is a fixed voltage and an IN+ is varied. If the input signals were reversed, the figure would be the same with an inverted output. To save cost and external pcb area, an internal ±7.5mV hysteresis circuit was added to the TS12011 and TS12012.

off Q2 and the output of the op-amp will turn Q1 off. Figure 4. Pilot Light Flame Detector with Low-Battery Lockout Circuit

Figure 5. Sawtooth/Triangle Generator with Stable Frequency and Amplitude

Figure 6. Low-power One-shot and Latch Circuits

Figure 7. Adjustable Buffered Reference Generators

Silicon Laboratories, Inc. Page 17 400 West Cesar Chavez, Austin, TX 78701 TS12011/12 Rev. 1.0 +1 (512) 416-8500 ▪ www.silabs.com PACKAGE OUTLINE DRAWING Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 10-Pin TDFN22 Package Outline Drawing (N.B., Drawings are not to scale)

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