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TS1105 and TS1106 Unidirectional and Bidirectional Current- Sense Amplifiers + Buffered Unipolar Output with Adjustable Bias The TS1105 and TS1106 combine the TS1100 or TS1101 current-sense amplifiers with a unipolar buffered output featuring adjustable bias. The TS1105 and TS1106 high-side current-sense amplifiers consume 0.68 μA (typ) and 1.2 μA (max) of supply current while the buffered output consumes 0.76 μA (typ) and 1.3 μA (max) of supply current. With an input offset voltage of 100 μV (max) and a gain error of 0.6% (max), the TS1105 and TS1106 are optimized for high-precision current meas- urements.
Applications
- Power Management Systems
- Portable/Battery-Powered Systems
- Smart Chargers
- Battery Monitoring
- Overcurrent and Undercurrent Detection
- Remote Sensing
- Industrial Controls KEY FEATURES
- Low Supply Current Current Sense Amplifier: 0.68 μA
- IVDD: 0.76 μA
- High-Side Bidirectional and Unidirectional Buffered Current Sense Amplifiers
- Wide CSA Input Common Mode Range: +2 V to +27 V
- Low CSA Input Offset Voltage: 100 μV (max)
- Low Gain Error: 0.6% (max)
- Two Gain Options Available:
- Gain = 20 V/V: TS1105-20 and TS1106-20
- Gain = 200 V/V: TS1105-200 and TS1106-200
- 8-Pin TDFN Packaging (3 mm x 3 mm)
- Ordering Information Table 1.1. Ordering Part Numbers Ordering Part Number1 Description Gain V/V TS1105-20ITD833 Unidirectional buffered unipolar current sense amplifier 20 TS1105-200ITD833 Unidirectional buffered unipolar current sense amplifier 200 TS1106-20ITD833 Bidirectional buffered unipolar current sense amplifier 20 TS1106-200ITD833 Bidirectional buffered unipolar current sense amplifier 200 Note: Adding the suffix “T” to the part number (e.g. TS1106-200ITD833T) denotes tape and reel. TS1105/06 Data Sheet
Ordering Information
- System Overview
2.1 Functional Block Diagrams
Figure 2.1. TS1105 Unidirectional Buffered Current Sense Amplifier Block Diagram Figure 2.2. TS1106 Bidirectional Buffered Current Sense Amplifier Block Diagram TS1105/06 Data Sheet System Overview
2.2 Current Sense Amplifier + Output Buffer
internal configuration of the TS1105 unidirectional and TS1106 bidirectional current-sense amplifiers are buffered variations of the TS1100 unidirectional and TS1101 bidirectional current-sense amplifier respectively. The TS1106 current-sense amplifier is configured for fully differential input/output operation, therefore the behavior of the TS1106 current-sense amplifier is identical for either V RS+ > VRS– or VRS– > VRS+. Referring to the block diagrams, the inputs of the TS1105/06’s differential input/output amplifier are connected to RS+ and RS– across an external RSENSE resistor that is used to measure current. At the non-inverting input of the current-sense amplifier, the applied volt- age difference in voltage between RS+ and RS– is I LOAD x RSENSE. Since the RS– terminal is the non-inverting input of the internal op- amp, the current-sense op-amp action drives PMOS[1/2] to drive current across RGAIN[A/B] to equalize voltage at its inputs. Thus, since the PMOS source for both M1 and M2 are connected to the inverting input of the internal op-amp and since the voltage drop across RGAINA or RGAINB is the same as the external VSENSE, the PMOS drain-source current for either M1 or M2 is equal to: IDS(M 1&M 2) = VSENSE RGAIN A/B or IDS(M 1&M 2) = ILOAD × RSENSE RGAIN A/B The drain terminal for PMOS[1/2] is connected to the transimpedance amplifier’s gain resistor, R OUT, via the inverting terminal. The non-inverting terminal of the transimpedance amplifier is internally connected to VBIAS, therefore the output voltage of the TS1105/06 at the OUT terminal is VOUT = V BIAS − ILOAD × RSENSE × ROUT RGAIN A/B The current-sense amplifier’s gain accuracy is therefore the ratio match of R OUT to RGAIN[A/B]. For each of the gain options available, the table below lists the values for RGAIN[A/B] Table 2.1. Internal Gain Setting Resistors (Typical Values) GAIN (V/V) RGAIN[A/B] (Ω) ROUT (Ω) Part Number 20 2 k 40 k TS1105-20 200 200 40 k TS1105-200 20 2 k 40 k TS1106-20 200 200 40 k TS1106-200 The TS1105/06 allows access to the inverting terminal of the transimpedance amplifier by the FILT pin, whereby a series RC filter may be connected to reduce noise at the OUT terminal. The recommended RC filter is 4 kΩ and 0.47 μF connected in series from FILT to GND to suppress the noise. Any capacitance at the OUT terminal should be minimized for stable operation of the buffer. TS1105/06 Data Sheet System Overview
2.3 Sign Output—TS1106 Only
TS1106’s SIGN output indicates the load current’s direction. The SIGN output is a logic HIGH when M1 is conducting current (VRS + > VRS–). Alternatively, the SIGN output is a logic LOW when M2 is conducting current (VRS– > VRS+). The SIGN comparator’s transfer characteristic is illustrated in the figure below. Unlike other current-sense amplifiers that implement an OUT/SIGN arrangement, the TS1106 exhibits no “dead zone” at ILOAD switchover Figure 2.3. TS1106 Sign Output Transfer Characteristic
2.4 Selecting a Sense Resistor
Selecting the optimal value for the external RSENSE is based on the following criteria, and commentary follows for each: RSENSE Voltage Loss 2. VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD 3. Total ILOAD Accuracy 4. Circuit Efficiency and Power Dissipation 5. RSENSE Kelvin Connections
2.4.1 RSENSE Voltage Loss
For lowest IR power dissipation in RSENSE, the smallest usable resistor value for RSENSE should be selected. 2.4.2 VOUT Swing vs. Desired VSENSE and Applied Supply Voltage at VDD Although the Current Sense Amplifier draws its power from the voltage at its RS+ and RS– terminals, the signal voltage at the OUT terminal is provided by a buffer, and is therefore bounded by the buffer’s output range. As shown in the Electrical Characteristics table, the CSA Buffer has a maximum and minimum output voltage of: VOUT (max ) = VDD(min ) −0.2V VOUT (min ) = 0.2V Therefore, the full-scale sense voltage should be chosen so that the OUT voltage is neither greater nor less than the maximum and minimum output voltage defined above. To satisfy this requirement, the full-scale sense voltage, V SENSE(max), should be chosen so that: VSENSE(max ) < VBIAS −VOUT (min ) GAIN For best performance, RSENSE should be chosen so that the full-scale VSENSE is less than ±75 mV. TS1105/06 Data Sheet System Overview
2.4.3 Total Load Current Accuracy
the TS1105/06’s linear region where V OUT(min) < VOUT < VOUT(max), there are two specifications related to the circuit’s accuracy: a) the TS1105/06 CSA’s input offset voltage (V OS(max) = 150 μV), b) the TS1105/06 CSA’s gain error (GE (max) = 1%). An expression for the TS1105/06’s total error is given by: VOUT = VBIAS + GAIN × (1 ± GE) × VSENSE ± (GAIN × VOS) A large value for RSENSE permits the use of smaller load currents to be measured more accurately because the effects of offset voltag- es are less significant when compared to larger V SENSE voltages. Due care though should be exercised as previously mentioned with large values of RSENSE.
2.4.4 Circuit Efficiency and Power Dissipation
IR loses in RSENSE can be large especially at high load currents. It is important to select the smallest, usable R SENSE value to minimize power dissipation and to keep the physical size of R SENSE small. If the external R SENSE is allowed to dissipate significant power, then its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Precisely because the TS1105/06 CSA’s input stage was designed to exhibit a very low input offset voltage, small R SENSE values can be used to reduce power dissipation and minimize local hot spots on the pcb.
2.4.5 RSENSE Kelvin Connections
For optimal VSENSE accuracy in the presence of large load currents, parasitic pcb track resistance should be minimized. Kelvin-sense pcb connections between R SENSE and the TS1105/06’s RS+ and RS– terminals are strongly recommended. The drawing below illus- trates the connections between the current-sense amplifier and the current-sense resistor. The pcb layout should be balanced and sym- metrical to minimize wiring-induced errors. In addition, the pcb layout for R SENSE should include good thermal management techniques for optimal RSENSE power dissipation. Figure 2.4. Making PCB Connections to RSENSE
2.4.6 RSENSE Composition
resistors are available in metal film, metal strip, and wire-wound constructions. Wire-wound current-shunt resistors are constructed with wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self-inductance. In applications where the load current contains high-frequency transients, metal film or metal strip current sense resistors are recommen- ded.
2.4.7 Internal Noise Filter
In power management and motor control applications, current-sense amplifiers are required to measure load currents accurately in the presence of both externally-generated differential and common-mode noise. An example of differential-mode noise that can appear at the inputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple (whether injected into the circuit inductively or ca- pacitively) can produce a differential-mode voltage drop across the external current-shunt resistor, R SENSE. An example of externally- generated, common-mode noise is the high-frequency output ripple of a switching regulator that can result in common-mode noise in- jection into both inputs of a current-sense amplifier. Even though the load current signal bandwidth is dc, the input stage of any current-sense amplifier can rectify unwanted, out-of-band noise that can result in an apparent error voltage at its output. Against common-mode injection noise, the current-sense amplifier’s in- ternal common-mode rejection ratio is 130 dB (typ). To counter the effects of externally-injected noise, the TS1105-06 incorporates a 50 kHz (typ), 2nd-order differential low-pass filter as shown in the TS1105-06’s block diagram, thereby eliminating the need for an external low-pass filter which can generate errors in the offset voltage and the gain error. TS1105/06 Data Sheet System Overview
2.4.8 PC Board Layout and Power Supply Bypassing
optimal circuit performance, the TS1105/06 should be in very close proximity to the external current-sense resistor and the pcb tracks from RSENSE to the RS+ and the RS– input terminals of the TS1105/06 should be short and symmetric. Also recommended are surface mount resistors and capacitors, as well as a ground plane. TS1105/06 Data Sheet System Overview
- Electrical Characteristics Table 3.1. Recommended Operating Conditions1 Parameter Symbol Conditions Min Typ Max Units System Specifications Operating Voltage Range VDD 1.7 — 5.25 V Common-Mode Input Range V CM VRS+, Guaranteed by CMRR 2 — 27 V Note: All devices 100% production tested at TA = +25 °C. Limits over Temperature are guaranteed by design and characterization. Table 3.2. DC Characteristics1 Parameter Symbol Conditions Min Typ Max Units System Specifications No Load Input Supply Current IRS+ + IRS– See Note — 0.68 — µA VRS+ = 25 V — — 1.2 µA IVDD See Note 2 — 0.76 1.3 µA Current Sense Amplifier Common Mode Re- jection Ratio CMRR 2 V < V RS+ < 27 V 120 130 — dB Input Offset Voltage3 VOS TA = +25 °C — ±30 ±100 µV VOS Hysteresis 4 VHYS TA = +25 °C — 10 — µV Gain G TS1105-20, TS1106-20 — 20 — V/V TS1105-200, TS1106-200 — 200 — V/V Gain Error5 GE TA = +25 °C — ±0.1 ±0.6 % Gain Match 5 GM TA = +25 °C — ±0.2 ±0.6 % Transfer Resistance R OUT From FILT to OUT 28 40 52 kW CSA Buffer Input Bias Current I Buffer_BIAS –40C < TA < +85 °C — 0.3 — nA Input referred DC Off- set VBuffer_OS — — ±2.5 mV Offset Drift TCVBuffer_OS –40 °C < TA < +85 °C — 0.6 — µV/°C Input Common Mode Range VCM_Buffer –40 °C < TA < +85 °C 0.2 — VDD – 0.2 V Output Range VOUT(MIN, MAX) IOUT = ±150 µA 0.2 — VDD – 0.2 V TS1105/06 Data Sheet
Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units Sign Comparator Parameters (TS1106 Only) Output Low Voltage V SIGN_OL ISINK = 35 µA — — 0.2 V Output High Voltage V SIGN_OH ISOURCE = 35 µA VDD – 0.2 — — V Note: RS+ = RS– = 3.6 V, VSENSE = (VRS+ – VRS–) = 0 V, VDD = 3 V, VBIAS = 1.5 V. TA = TJ = –40 °C to +85 °C unless otherwise noted. Typical values are at TA = +25 °C. 2. Extrapolated to VOUT = VFILT. IRS+ + IRS– is the total current into the RS+ and the RS– pins. 3. Input offset voltage VOS is extrapolated from a VOUT(+) measurement with VSENSE set to +1 mV and a VOUT(–) measurement with VSENSE set to –1 mV; Average VOS = (VOUT(–) – VOUT(+))/(2 x GAIN). 4. Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states. 5. Gain error is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer characteristic. TS1105 only applies positive VSENSE values. For GAIN = 20 V/V, the applied VSENSE for GE± is ±25 mV and ±60 mV. For GAIN = 200 V/V, the applied VSENSE for GE± is ±2.5 mV and ±6 mV. Table 3.3. AC Characteristics1 Parameter Symbol Conditions Min Typ Max Units CSA Buffer Output Settling time tOUT_s 1% Final value, VOUT = 1.3 V Gain = 20 V/V — 1.35 — msec Sign Comparator Parameters (TS1106 Only) Propagation Delay tSIGN_PD VSENSE = ±1 mV — 3 — msec VSENSE = ±10 mV — 0.4 — msec Note: RS+ = RS– = 3.6 V, VSENSE = (VRS+ – VRS–) = 0 V, VDD = 3 V, VBIAS = 1.5 V. TA = TJ = –40 °C to +85 °C unless otherwise noted. Typical values are at TA = +25 °C. Table 3.4. Thermal Conditions Parameter Symbol Conditions Min Typ Max Units Operating Tempera- ture Range TOP –40 — +85 °C TS1105/06 Data Sheet
Table 3.5. Absolute Maximum Limits Parameter Symbol Conditions Min Typ Max Units RS+ Voltage VRS+ –0.3 — 27 V RS– Voltage VRS– –0.3 — 27 V Supply Voltage VDD –0.3 — 6 V OUT Voltage VOUT –0.3 — 6 V SIGN Voltage (TS1106 Only) VSIGN –0.3 — 6 V FILT Voltage VFILT –0.3 — 6 V VBIAS Voltage VVBIAS –0.3 — VDD + 0.3 V RS+ to RS– Voltage VRS+ – V RS– — — 27 V Short Circuit Duration: OUT to GND — — Continuous Continuous Input Current (Any Pin) –20 — 20 mA Junction Temperature — — 150 °C Storage Temperature Range –65 — 150 °C Lead Temperature (Soldering, 10 s) — — 300 °C Soldering Temperature (Reflow) — — 260 °C ESD Tolerance Human Body Model — — 2000 V Machine Model — — 200 V TS1105/06 Data Sheet
For the following graphs, VRS+ = VRS– = 3.6 V; VDD = 3 V; VBIAS = 1.5 V, and TA = +25 C unless otherwise noted. TS1105/06 Data Sheet
- Pin Descriptions TS1106 TS1105 Table 5.1. Pin Descriptions Pin Label Function 1 SIGN TS1106 Sign output. SIGN is HIGH for VRS+ > VRS– and LOW for VRS–>VRS+ NC TS1105 No connection. Leave open. 2 VDD External power supply pin. Connect this to the system’s VDD supply. 3 VBIAS Bias voltage for CSA output. When VREF is activated, leave open. 4 GND Ground. Connect to analog ground. 5 OUT CSA buffered output. Connect to CIN–. 6 FILT Inverting terminal of CSA Buffer. Connect a series RC Filter of 4 kΩ and 0.47 µF; otherwise, leave open.
7 RS+ External Sense Resistor Power-Side Connection
8 RS– External Sense Resistor Load-Side Connection
Exposed Pad EPAD Exposed backside paddle. For best electrical and thermal performance, solder to analog ground. TS1105/06 Data Sheet Pin Descriptions
- Packaging Figure 6.1. TS1105-06 3x3 mm 8-TDFN Package Diagram Table 6.1. Package Dimensions Dimension Min Nom Max A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 0.20 REF b 0.25 0.30 0.35 D 3.00 BSC D2 1.49 1.50 1.51 e 0.65 BSC E 3.00 BSC E2 1.65 1.75 1.85 L 0.30 0.40 0.50 K 0.20 0.25 0.30 J 0.65 REF aaa 0.10 bbb 0.05 ccc 0.05 Note: All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 4. This drawing conforms to the JEDEC Solid State Outline MO-229. TS1105/06 Data Sheet Packaging
- Top Marking Figure 7.1. Top Marking Table 7.1. Top Marking Explanation Mark Method Laser Pin 1 Mark: Circle = 0.50 mm Diameter (lower left corner) Font Size: 0.50 mm (20 mils) Line 1 Mark Format: Product ID Note: A = 20 gain, B = 200 gain Line 2 Mark Format: TTTT – Mfg Code Manufacturing code Line 3 Mark Format: YY = Year; WW = Work Week Year and week of assembly TS1105/06 Data Sheet Top Marking
2.3 Table of Contents 17
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