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© 2014 Silicon Laboratories, Inc. All rights reserved.
FEATURES
♦ Ultra-Low Supply Current: 1μA ♦ Wide Input Common Mode Range: +2V to +27V ♦ Low Input Offset Voltage: 200μV (max) ♦ Low Gain Error: 0.6% (max) ♦ Voltage Output ♦ Four Gain Options Available: TS1103-25: Gain = 25V/V TS1103-50: Gain = 50V/V TS1103-100: Gain = 100V/V TS1103-200: Gain = 200V/V ♦ 6-Lead SOT23 Packaging
APPLICATIONS
Portable/Battery-Powered Systems Smart Chargers Smart Phones
DESCRIPTION
The TS1103 is the latest addition to the TS1101 family of bidirectional current-sense amplifiers. Consuming a very low 1 μA supply current, the TS1103 high-side current-sense amplifiers combine a 200-µV (max) V OS and a 0.6% (max) gain error for cost-sensitive applications. For all high-side bidirectional current-sensing applications, the TS1103s are self-powered and feature a wide input common-mode voltage range from 2V to 27V. A SIGN comparator digital output is also provided that indicates the direction of current flow depending on the external connections to the TS1103’s RS+ and RS- input terminals. The SOT23 package makes the TS1103 an ideal choice for pcb-area-critical, supply-current-conscious, high-accuracy current-sense applications in all battery-powered and portable instruments. All TS1103s are specified for operation over the -40°C to +105°C extended temperature range. A 1µA, 200µVOS Bidirectional Precision Current-Sense Amplifier TYPICAL APPLICATION CIRCUIT PART GAIN OPTION TS1103-25 25 V/V TS1103-50 50 V/V TS1103-100 100 V/V TS1103-200 200 V/V SIGN Comparator’s Symmetric ILOAD Crossover
Page 2 TS1103 Rev. 1.1 ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 6-Lead SOT23 (Derate at 4.5mW/°C above +70°C) Electrical and thermal stresses beyond thos e listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION ORDER NUMBER PART MARKIN G CARRIER QUANTITY TS1103-25EG6 TADW Tape & Reel ----- TS1103-25EG6T Tape & Reel 3000 TS1103-50EG6 TADX Tape & Reel ----- TS1103-50EG6T Tape & Reel 3000 TS1103-100EG6 TADY Tape & Reel ----- TS1103-100EG6T Tape & Reel 3000 TS1103-200EG6 TADZ Tape & Reel ----- TS1103-200EG6T Tape & Reel 3000 Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges.
TS1103 Rev. 1.1 Page 3
ELECTRICAL CHARACTERISTICS
VRS+ = 3.6V; VSENSE = (VRS+ - VRS-) = 0V; COUT = 47nF; VDD = 1.8V; TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C. See Note 1. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Current (Note 2) ICC TA = +25°C 0.68 0.85 μA 1.0 VRS+ = 25V TA = +25°C 1.0 1.2 Common-Mode Input Range V CM Guaranteed by CMRR 2 27 V CURRENT SENSE AMPLIFIER PARAMETERS Common-Mode Rejection Ratio CMRR 2V < V RS+ < 27V 120 150 dB Input Offset Voltage (Note 3) V OS TA = +25°C ±30 ±200 μV ±300 VOS Hysteresis (Note 4) VHYS T A = +25°C 10 µV Gain G TS1103-25 25 V/V TS1103-50 50 TS1103-100 100 TS1103-200 200 Gain Error (Note 5) GE TA = +25°C ±0.2 ±0.6 % ±1.0 Gain Match (Note 5) GM TA = +25°C ±0.2 ±0.6 % ±1 Output Resistance (Note 6) R OUT TS1103-25/50/100 7.0 10 13.2 kΩ TS1103-200 14.0 20 26.4 OUT Low Voltage VAOL Gain = 25 5 mV Gain = 50 10 Gain = 100 20 Gain = 200 40 OUT High Voltage (Note 7) V AOH V OH = VRS- - VOUT 0.05 0.2 V Output Settling Time tS TS1103-25/50/100 1% final value, VOUT = 3V 2.2 ms TS1103-200 4.3 SIGN COMPARATOR PARAMETERS VDD Supply Voltage Range V DD 1.25 5.5 V VDD Supply Current IDD 0.02 0.2 µA Output Low Voltage VCOL VDD = 1.25V, ISINK = 5µA 0.2 V VDD = 1.8V, ISINK = 35µA Output High Voltage VCOH VDD = 1.25V, ISOURCE = 5µA VDD – 0.2 V VDD = 1.8V, ISOURCE = 35µA Propagation Delay tPD VSENSE = ±1mV 3 ms VSENSE = ±10mV 0.4 Note 1: All devices are 100% production tested at TA = +25°C. All temperature limits are guaranteed by product characterization. Note 2: Extrapolated to VOUT = 0. ICC is the total current into the RS+ and the RS- pins. Note 3: Input offset voltage VOS is extrapolated from a VOUT+ measurement with VSENSE set to +1mV and a VOUT- measurement with VSENSE set to -1mV; vis-a-viz, Average VOS = ቀVOUT-ቁ - ሺVOUT+ሻ 2 x GAIN Note 4: Amplitude of VSENSE lower or higher than VOS required to cause the comparator to switch output states. Note 5: Gain error applies to current flow in either direction and is calculated by applying two values for VSENSE and then calculating the error of the actual slope vs. the ideal transfer characteristic: For GAIN = 25, the applied VSENSE is 20mV and 120mV. For GAIN = 50, the applied VSENSE is 10mV and 60mV. For GAIN = 100, the applied VSENSE is 5mV and 30mV. For GAIN = 200, the applied VSENSE is 2.5mV and 15mV. Note 6: The device is stable for any capacitive load at VOUT. Note 7: VOH is the voltage from VRS- to VOUT with VSENSE = 3.6V/GAIN.
Page 4 TS1103 Rev. 1.1 Input Offset Voltage vs Common-Mode Voltage Supply Current vs Common-Mode Voltage Input Offset Voltage vs Temperature Supply Current vs Temperature PERCENT OF UNITS - % INPUT OFFSET VOLTAGE - µV PERCENT OF UNITS - % GAIN ERROR - % INPUT OFFSET VOLTAGE - µV TEMPERATURE - °C TEMPERATURE - °C SUPPLY CURENT - µA SUPPLY VOLTAGE - Volt 20 20 10 30 -10 40 25V 3.6V INPUT OFFSET VOLTAGE - µV SUPPLY VOLTAGE - Volt SUPPLY CURRENT - µA TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. -40 -15 10 60 11085 0 5 10 15 30 25 0.2 0.6 0.8 0.4 1 40 -20 -40 -0.4 0.2 -0.6 0.60 Input Offset Voltage Histogram Gain Error Histogram 35 20 0 5 10 15 30 25 20 0.2 0.6 0.8 0.4 -40 -15 10 60 11085 35 50 -0.2 0.4
TS1103 Rev. 1.1 Page 5 Gain Error vs Common-Mode Voltage SUPPLY VOLTAGE - Volt Gain Error vs. Temperature Small-Signal Gain vs Frequency SMALL-SIGNAL GAIN -dB VSENSE- mV COMMON-MODE REJECTION - dB 0.2 0.3 0.001 0.1 1 10 1000 -15 -35 -25 10 20 0 30 GAIN ERROR - % G = 100 G = 25 G = 50 G = 100 G = 50 G = 25 VOUT vs VSENSE @ Supply = 3.6V VOUT - V G = 25 G = 100 G = 50 G =25 G = 50, 100 FREQUENCY - kHz Common-Mode Rejection vs Frequency 0.1 -0.3 -0.2 0.1 0.2 0.3 -0.1 15 5 0 150100 50 0 10060 20 2.5 3.5 1.5 0.2 0.8 1.0 0.4 0.6 -10 -20 -30 100 -20 -60 -140 -80 -40 -100 -120 TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; TA = +25°C, unless otherwise noted. -40 -15 35 60 8510 TEMPERATURE - °C GAIN ERROR - % VSENSE- mV VOUT - V VOUT vs VSENSE @ Supply = 2V FREQUENCY - kHz 40 80 1.2 1.8 1.4 1.6 0.5 25 110 0.01 0.001 0.1 1 10 10001000.01 0.4
Page 6 TS1103 Rev. 1.1 200µs/DIV 200µs/DIV Small-Signal Pulse Response, Gain = 100 VSENSE VOUT VSENSE VOUT TYPICAL PERFORMANCE CHARACTERISTICS VRS+ = VRS- = 3.6V; COUT = 0pF; TA = +25°C, unless otherwise noted. 200µs/DIV 200µs/DIV Small-Signal Pulse Response, Gain = 50 VSENSE VOUT VSENSE VOUT Large-Signal Pulse Response, Gain = 50 200µs/DIV 200µs/DIV Small-Signal Pulse Response, Gain = 25 VSENSE VOUT VSENSE VOUT Large-Signal Pulse Response, Gain = 25 Large-Signal Pulse Response, Gain = 100
TS1103 Rev. 1.1 Page 7 PIN FUNCTIONS PIN LABEL FUNCTION 1 GND Ground. Connect this pin to analog ground. 2 SIGN Comparator Output, pus h-pull; SIGN is HIGH for (VRS+ > VRS-) and LOW for (VRS- > VRS+). 3 OUT Output Voltage. V OUT is proportional to VSENSE = (VRS+ - VRS-) or (VRS- - VRS+).
4 RS- External Sense Resistor Load-Side Connection
5 VDD SIGN Comparator External Power Supply Pi n; Connect this pin to system’s logic VDD supply.
6 RS+ External Sense Resistor Power-Side Connection
The internal configuration of the TS1103 – a bidirectional high-side, current-sense amplifier – is a variation of the TS1100 uni-directional current-sense amplifier. In the design of the TS1103, the input amplifier was reconfigured for fully differential input/output operation and a second low-threshold p- channel FET (M2) was added where the drain terminal of M2 is also connected to ROUT. Therefore, the behavior of the TS1103 for when V RS- > VRS+ is identical for when VRS+ > VRS-. Referring to the typical application circuit on Page 1, the inputs of the TS1103’s differential input/output amplifier are connected across an external RSENSE resistor that is used to measure current. At the non- inverting input of the TS1103 (the RS- terminal), the applied voltage is I LOAD x RSENSE. Since the RS- terminal is the non-inverting input of the internal op amp, op amp feedback action forces the inverting input of the internal op amp to the same potential (ILOAD x RSENSE). Therefore, the voltage drop across RSENSE (V SENSE = V RS+ - V RS-) and the voltage drop across RGAINA (at the RS+ terminal) are equal. Necessary for gain ratio match, both RGAINA and RGAINB are the same value. Since p-channel M1’s source is connected to the inverting input of the internal op amp and since the voltage drop across RGAINA is the same as the
TS1103 Rev. 1.1 Page 9 The other attribute of the SIGN comparator’s behavior is its propagation delay as a function of applied V SENSE [(V RS+ - V RS-) or (V RS- - V RS+)]. As shown in Figure 2, the SIGN comparator’s propagation delay behavior is symmetric regardless of current-flow direction and is inversely proportional to V SENSE. APPLICATIONS INFORMATION Choosing the Sense Resistor Selecting the optimal value for the external RSENSE is based on the following criteria and for each commentary follows: 1) RSENSE Voltage Loss 2) V OUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE 3) Total I LOAD Accuracy 4) Circuit Efficiency and Power Dissipation 5) RSENSE Kelvin Connections 1) RSENSE Voltage Loss For lowest IR power dissipation in RSENSE, the smallest usable resistor value for RSENSE should be selected. 2) V OUT Swing vs. Applied Input Voltage at VRS+ and Desired VSENSE As there is no separate power supply pin for the TS1103, the circuit draws its power from the voltage at its RS+ and RS- terminal s. Therefore, the signal voltage at the OUT terminal is bounded by the minimum voltage applied at the RS+ terminal. Therefore, V OUT(max) = VRS+(min) - VSENSE(max) – VOH(max) and R SENSE ൏ VOUT ሺmaxሻ GAIN × ILOADሺmaxሻ where the full-scale V SENSE should be less than VOUT(MAX)/GAIN at the application’s minimum RS+ terminal voltage. For best performance with a 3.6V power supply, RSENSE should be chosen to generate a V SENSE of: a) 120mV (for the 25V/V GAIN option), b) 60mV (for the 50V/V GAIN option), c) 30mV (for the 100V/V GAIN option), or d) 15mV (for the 200V/V GAIN option) at the full-scale I LOAD current in each application. For the case where the minimum power supply voltage is higher than 3.6V, each of the four full-scale V SENSEs above can be increased. 3) Total Load Current Accuracy In the TS1103’s linear region where V OUT < V OUT(max), there are two specifications related to the circuit’s accuracy: a) the TS1103’s input offset voltage (V OS(max) = 200 μV) and b) its gain error (GE(max) = 0.6%). An expression for the TS1103’s total error is given by: V OUT = [GAIN x (1 ± GE) x VSENSE] ± (GAIN x VOS) A large value for RSENSE permits the use of smaller load currents to be measured more accurately because the effects of offset voltages are less significant when compared to larger VSENSE voltages. Due care though should be exercised as previously mentioned with large values of RSENSE. 4) Circuit Efficiency and Power Dissipation IR losses in RSENSE can be large especially at high load currents. It is important to select the smallest, usable RSENSE value to minimize power dissipation and to keep the physical size of RSENSE small. If the external RSENSE is allowed to dissipate significant power, then its inherent temperature coefficient may alter its design center value, thereby reducing load current measurement accuracy. Precisely because the TS1103’s input stage was designed to exhibit a very low input offset voltage, small RSENSE values can be used to reduce power dissipation and minimize local hot spots on the pcb. 5) RSENSE Kelvin Connections For optimal V SENSE accuracy in the presence of large load currents, parasitic pc b track resistance should be minimized. Kelvin-sense pcb connections between RSENSE and the TS1103’s RS+ and RS- terminals are strongly recommended. The drawing in Figure 3 illustrates the connections between the
Page 10 TS1103 Rev. 1.1 current-sense amplifier and the current-sense resistor. The pcb layout should be balanced and symmetrical to minimize wiring-induced errors. In addition, the pcb layout for RSENSE should include good thermal management techniques for optimal RSENSE power dissipation. 6) RSENSE Composition Current-shunt resistors are available in metal film, metal strip, and wire-wound constructions. Wire- wound current-shunt resistors are constructed with wire spirally wound onto a core. As a result, these types of current shunt resistors exhibit the largest self inductance. In applications where the load current contains high-frequency transients, metal film or metal strip current sense resistors are recommended. Internal Noise Filter In power management and motor control applications, current-sense amplifiers are required to measure load currents accurately in the presence of both externally-generated differential and common- mode noise. An example of differential-mode noise that can appear at the i nputs of a current-sense amplifier is high-frequency ripple. High-frequency ripple – whether injected into the circuit inductively or capacitively - can produce a differential-mode voltage drop across the external current-shunt resistor (RSENSE). An example of externally- generated, common-mode noise is the high- frequency output ripple of a switching regulator that can result in common-mode noise injection into both inputs of a current-sense amplifier. Even though the load current signal bandwidth is DC, the input stage of any current-sense amplifier can rectify unwanted, out-of-band noise that can result in an apparent error voltage at its output. This rectification of noise si gnals occurs because all amplifier input stages are constructed with transistors that can behave as high-frequency signal detectors in the same way pn-junction diodes were used as RF envelope detectors in early radio designs. Against common-mode injected noise, the amplifier’s internal common-mode rejection is usually sufficient. To counter the effects of externally-injected noise, it has always been good engineering practice to add external low-pass filters in series with the inputs of a current-sense amplifier. In the design of discrete current-sense amplifiers, resistors used in the external low-pass filters were incorporated into the circuit’s overall design so errors because of any input-bias current-generat ed offset voltage errors and gain errors were compensated. With the advent of monolithic current-sense amplifiers, like the TS1103, the addition of external low-pass filters in series with the current-sense amplifier’s inputs only introduces additional offset voltage and gain errors. To minimize or eliminate altogether the need for external low-pass filters and to maintain low input offset voltage and gain errors, the TS1103 incorporates a 50-kHz (typ), 2 nd-order differential low-pass filter as shown in the TS1103’s Block Diagram. Output Filter Capacitor If the TS1103 is part of a signal acquisition system where its OUT terminal is connected to the input of an ADC with an internal, switched-capacitor track- and-hold circuit, the internal track-and-hold’s sampling capacitor can cause voltage droop at V OUT. A 22nF to 100nF good-quality ceramic capacitor from the OUT terminal to GND forms a low-pass filter with the TS1103’s R OUT and should be used to minimize voltage droop (holding V OUT constant during the sample interval. Using a capacitor on the OUT terminal will also reduce the TS1103’s small- signal bandwidth as well as band-limiting amplifier noise. PC Board Layout and Power-Supply Bypassing For optimal circuit performance, the TS1103 should be in very close proximity to the external current- sense resistor and the pcb tracks from RSENSE to the RS+ and the RS- input terminals of the TS1103 should be short and symmetric. Also recommended are a ground plane and surf ace mount resistors and capacitors. Figure 3: Making PCB Connections to RSENSE.
Silicon Laboratories, Inc. Page 11 400 West Cesar Chavez, Austin, TX 78701 TS1103 Rev. 1.1 +1 (512) 416-8500 ▪ www.silabs.com PACKAGE OUTLINE DRAWING 6-Pin SOT23 Package Outline Drawing (N.B., Drawings are not to scale) Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 0° ~ 8 Note: Dimension are exclusive of mold flash and gate burr. 2. Dimension are exclusive of solder plating. 3. The foot length measuring is based on the gauge plane method. 4. Package is surface to be matte finish VDI 11~13. 5. Dimensions and tolerances are as per ANSI Y14.5M, 1982. 6. This part is compliant with EIAJ specification SC74A and JEDEC MO-178 AB spec. 7. Die is facing up for mold, Die is facing down for trim/form, ie. reverse trim/form. 8. All dimensions are in mm. 0.050(MIN) 10° TYP. (2 Plcs) 10° TYP. (2 Plcs) 0.60 - 0.80 10° TYP. (2 Plcs) 0.09 – 0.127 1.50 – 1.75 0.25 Guage Plane 0.30 - 0.55 10° TYP. (2 Plcs) 0.50 -0.70 2.80 - 3.00 0.950 0.950 TYP. TYP. 2.60 - 3.00 1.50 - 1.75 0.300(MIN) 0.500(MAX)
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