TS1003IJ5T

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FEATURES

Single 0.8V to 5.5V Operation Supply current: 0.6μA (typ) Input Bias Current: 2pA (typ) Low TCVOS: 9µV/°C (typ) AVOL Driving 100kΩ Load: 90dB (min) Gain-Bandwidth Product: 4kHz Unity Gain Stable Rail-to-rail Input and Output No Output Phase Reversal 5-pin SC70 or 5-pin SOT23 Packaging

APPLICATIONS

Battery/Solar-Powered Instrumentation Portable Gas Monitors Low-voltage Signal Processing Micropower Active Filters Wireless Remote Sensors Battery-powered Industrial Sensors Active RFID Readers Powerline or Battery Current Sensing Handheld/Portable POS Terminals

DESCRIPTION

The TS1003 is the industry’s first sub-1µA supply current, precision CMOS operational amplifier fully specified to operate over a supply voltage range from 0.8V to 5.5V . Fully specified at 1.8V, the TS1003 is optimized for ultra-long-life battery powered applications. The TS1003 is the fourth operational amplifier in the “NanoWatt Analog™” high- performance analog integrated circuits portfolio. The TS1003 exhibits a typical input bias current of 2pA, and has rail-to-rail input and output stages. The TS1003’s combined features make it an excellent choice in applications where very low supply current and low operating supply voltage translate into very long equipment operating time. Applications include: micropower active filt ers, wireless remote sensors, battery and powerline current sensors, portable gas monitors, and handheld/portable POS terminals. The TS1003 is fully specified over the industrial temperature range (−40°C to +85°C) and is available in either a PCB-space saving 5-lead SC70 or a 5-lead SOT23 packaging. Percent of Units - % 10% 15% 20% 25% 30% 35% Supply Current Distribution THE ONLY 0.8V TO 5.5V, 0.6µA RAIL-TO-RAIL SINGLE OP AMP TYPICAL APPLICATION CIRCUIT A MicroWatt 2-Pole Sallen Key Low Pass Filter 0.48 0.53 0.58 0.63 Supply Current - µA VDD = 1.8V

Page 2 TS1003 Rev. 1.0 ABSOLUTE MAXIMUM RATINGS Continuous Power Dissipation (TA = +70°C) 5-Pin SOT23(Derate 3.87mW/°C above +70°C) ... 312 mW Electrical and thermal stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. PACKAGE/ORDERING INFORMATION TAPE & REEL ORDER NUMBER PART MARKING PACKAGE QUANTITY TAPE & REEL ORDER NUMBER PART MARKING PACKAGE QUANTITY TS1003IJ5 TAH --- TS1003IG5 TAEA --- TS1003IJ5T 3000 TS1003IG5T 3000 Lead-free Program: Silicon Labs supplies only lead-free packaging. Consult Silicon Labs for products specified with wider operating temperature ranges.

TS1003 Rev. 1.0 Page 3

ELECTRICAL CHARACTERISTICS

VDD = +1.8V, VSS = 0V, VINCM = VSS; RL = 100kΩ to (VDD-VSS)/2; TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. See Note 1 Parameters Symbol Conditions Min Typ Max Units Supply Voltage Range VDD-VSS 0.8 5.5 V Supply Current ISY RL = Open circuit TA = 25°C 0.6 0.8 µA -40°C ≤ TA ≤ 85°C 1 Input Offset Voltage VOS VIN = VSS or VDD TA = 25°C 0.8 3 mV -40°C ≤ TA ≤ 85°C 5 Input Offset Voltage Drift TCVOS 9 µV/°C Input Bias Current IIN+, IIN- VIN+, VIN- = (VDD - VSS)/2 TA = 25°C 2 pA -40°C ≤ TA ≤ 85°C 100 Input Offset Current IOS Specified as IIN+ - IIN- VIN+, VIN- = (VDD - VSS)/2 TA = 25°C 2 pA -40°C ≤ TA ≤ 85°C 50 Input Voltage Range IVR Guaranteed by Input Offset Voltage Test VSS VDD V Common-Mode Rejection Ratio CMRR Vdd=5.5V; 0V ≤ VIN(CM) ≤ 5.0V TA = 25°C 70 90 dB -40°C ≤ TA ≤ 85°C 68 Power Supply Rejection Ratio PSRR 0.8V ≤ (VDD - VSS) ≤ 5.5V TA = 25°C 70 90 dB -40°C ≤ TA ≤ 85°C 67 Output Voltage High VOH Specified as VDD - VOUT, RL = 100kΩ to VSS TA = 25°C 3.7 mV -40°C ≤ TA ≤ 85°C 6 Specified as VDD - VOUT, RL = 10kΩ to VSS TA = 25°C 30 -40°C ≤ TA ≤ 85°C 60 Output Voltage Low VOL Specified as VOUT - VSS, RL = 100kΩ to VDD TA = 25°C 1.5 mV -40°C ≤ TA ≤ 85°C 6 Specified as VOUT - VSS, RL = 10kΩ to VDD TA = 25°C 15 -40°C ≤ TA ≤ 85°C 30 Short-circuit Current ISC+ VOUT = VSS TA = 25°C 4 mA -40°C ≤ TA ≤ 85°C 2 ISC- VOUT = VDD TA = 25°C 15 Open-loop Voltage Gain AVOL VSS+50mV ≤ VOUT ≤ VDD-50mV TA = 25°C 91 110 dB -40°C ≤ TA ≤ 85°C 84 Gain-Bandwidth Product GBWP RL = 100kΩ to VSS, CL = 20pF 4 kHz Phase Margin φM Unity-gain Crossover, RL = 100kΩ to VSS, CL = 20pF 70 degrees Slew Rate SR RL = 100kΩ to VSS, AVCL = +1V/V 1.5 V/ms Full-power Bandwidth FPBW FPBW = SR/(π • VOUT,PP); VOUT,PP = 0.7VPP 680 Hz Input Voltage Noise Density en f = 1kHz 0.6 µV/√Hz Input Current Noise Density in f = 1kHz 10 pA/√Hz Note 1: All specifications are 100% tested at T A = +25°C. Specification limits over temperature (T A = TMIN to TMAX) are guaranteed by device characterization, not production tested.

Page 4 TS1003 Rev. 1.0 TYPICAL PERFORMANCE CHARACTERISTICS Supply Current vs Supply Voltage SUPPLY CURENT - µA SUPPLY VOLTAGE - Volt Supply Current vs Input Common -Mode Voltage SUPPLY CURENT - µA INPUT COMMON-MODE VOLTAGE - Volt Supply Current vs Input Common -Mode Voltage Input Offset Voltage vs Input Common-Mode Voltage INPUT OFFSET VOLTAGE - mV INPUT OFFSET VOLTAGE - mV INPUT COMMON-MODE VOLTAGE - Volt Input Offset Voltage vs Supply Voltage INPUT COMMON-MODE VOLTAGE - Volt SUPPLY CURENT - µA SUPPLY VOLTAGE - Volt VDD =1.8V TA = +25°C Input Offset Voltage vs Input Common-Mode Voltage INPUT OFFSET VOLTAGE - mV INPUT COMMON-MODE VOLTAGE - Volt VDD = 5.5V TA = +25°C +25°C +85°C -40°C 0.5 0.55 0.6 0.65 0.7 0.75 VDD=1.8V TA = +25°C 0.65 0.61 0.57 0.55 0 0.6 1.8 VDD=5.5V TA = +25°C 0.625 0.605 0.565 0.525 0 3.3 4.4 5.5 1.1 TA = +25°C VINCM = VDD 0.6 0.4 0.2 -0.6 VINCM = 0V 0 0.3 0.9 1.2 1.8 0.6 0.3 -0.3 0.6 0.3 -0.6 -0.3 0.59 0.63 1.2 0.585 0.545 2.2 -0.2 -0.4 2.4 3.9 1.5 0.6 -0.6 0.8 3.9

TS1003 Rev. 1.0 Page 5 -40 TYPICAL PERFORMANCE CHARACTERISTICS Input Bias Current (IIN+, IIN-) vs Input Common-Mode Voltage INPUT BIAS CURRENT - pA INPUT COMMON-MODE VOLTAGE - Volt Output Voltage High (VOH) vs Temperature, RLOAD =100kΩ TEMPERATURE - °C Output Voltage Low (VOL) vs Temperature, RLOAD =100kΩ TEMPERATURE - °C Output Voltage High (VOH) vs Temperature, RLOAD =10kΩ Output Voltage Low (VOL) vs Temperature, RLOAD =10kΩ Input Bias Current (IIN+, IIN-) vs Input Common-Mode Voltage OUTPUT SATURATION VOLTAGE - mV INPUT COMMON-MODE VOLTAGE - Volt INPUT BIAS CURRENT - pA OUTPUT SATURATION VOLTAGE - mV VDD = 5.5V VDD =1.8V -30 -20 RL = 100kΩ VDD = 1.8V VDD = 5.5V RL = 100kΩ VDD = 1.8V VDD = 5.5V 100 120 OUTPUT SATURATION VOLTAGE - mV OUTPUT SATURATION VOLTAGE - mV TEMPERATURE - °C TEMPERATURE - °C RL = 10kΩ VDD = 1.8V VDD = 5.5V RL = 10kΩ VDD = 1.8V VDD = 5.5V TA = +25°C TA = +85°C TA = +25°C TA = +85°C -10

Page 6 TS1003 Rev. 1.0 VOUT(N) - 100µV/DIV 0.1Hz to 10Hz Output Voltage Noise TYPICAL PERFORMANCE CHARACTERISTICS Output Short Circuit Current, ISC+ vs Temperature OUTPUT SHORT-CIRCUIT CURRENT - mA Output Short Circuit Current, ISC- vs Temperature Large-Signal Transient Response VDD = 5.5V, VSS = GND, RLOAD = 100kΩ, CLOAD = 15pF 200µs/DIV OUTPUT SHORT-CIRCUIT CURRENT - mA INPUT Small-Signal Transient Response VDD = 5.5V, VSS = GND, RLOAD = 100kΩ, CLOAD = 15pF 2ms/DIV OUTPUT INPUT OUTPUT TEMPERATURE - °C TEMPERATURE - °C VDD = 1.8V VDD = 5.5V VDD = 1.8V VDD = 5.5V VOUT = 0V VOUT = VDD 6.5 2.5 3.8 5.2 12.5

1 Second/DIV

100µVPP VDD = 1.8V TA = +25°C RL = 100kΩ CL = 20pF AVCL = 1000V/V 21.5 Gain and Phase vs. Frequency GAIN - dB FREQUENCY - Hz PHASE - Degrees 10 1k 10k 100 -10 100k PHASE GAIN 4kHz 70°

TS1003 Rev. 1.0 Page 7 PIN FUNCTIONS Pin Label Function 1 OUT Amplifier Output. 2 VSS Negative Supply or Analog GND. If applying a negative voltage to this pin, connect a 0.1µF capacitor from this pin to analog GND. 3 +IN Amplifier Non-inverting Input. 4 -IN Amplifier Inverting Input. 5 VDD Positive Supply Connection. Connect a 0.1µF bypass capacitor from this pin to analog GND. THEORY OF OPERATION The TS1003 is fully functional for an input signal from the negative supply (V SS or GND) to the positive supply (VDD). The input stage consists of two differential amplifiers, a p-channel CMOS stage and an n-channel CMOS stage that are active over different ranges of the input common mode voltage. The p-channel input pair is active for input common mode voltages, V INCM, between the negative supply to approximately 0.4V below the positive supply. As the common- mode input voltage moves closer towards VDD, an internal current mirror activates the n-channel input pair differential pair. The p-channel input pair becomes inactive for the balance of the input common mode voltage range up to the positive supply. Because both input stages have their own offset voltage (V OS) characteristic, the offset voltage of the TS1003 is a function of the applied input common-mode voltage, V INCM. The V OS has a crossover point at ~0.4V from VDD (Refer to the V OS vs. V CM curve in the Typical Operating Characteristics section). Caution should be taken in applications where the input signal amplitude is comparable to the TS1003’s V OS value and/or the design requires high accuracy. In these situations, it is necessary for the input signal to avoid the crossover point. In addition, amplifier parameters such as PSRR and CMRR which involve the input offset voltage will also be affected by changes in the input common- mode voltage across the differential pair transition region. The second stage is a folded-cascode transistor arrangement that converts the input stage differential signals into a single-ended output. A complementary drive generator supplies current to the output transistors that swing rail to rail. The TS1003 output stages voltage swings within 3.7mV from the rails at 1 .8V supply when driving an output load of 100kΩ - which provides the maximum possible dynamic range at the output. This is particularly important when operating on low supply voltages. When driving a stiffer 10k Ω load, the TS1003 swings within 30mV of V DD and within 13mV of VSS or GND. APPLICATIONS INFORMATION Portable Gas Detection Sensor Amplifier Gas sensors are used in many different industrial and medical applications. Gas sensors generate a current that is proportional to the percentage of a particular gas concentration sensed in an air sample. This output current flows through a load resistor and the resultant voltage drop is amplified. Depending on the sensed gas and sensitivity of the sensor, the output current can be in the range of tens of microamperes to a few milliamperes. Gas sensor datasheets often specify a recommended load resistor value or a range of load resistors from which to choose. There are two main applications for oxygen sensors – applications which sense oxygen when it is abundantly present (that is, in air or near an oxygen tank) and those which detect traces of oxygen in parts-per-million concentration. In medical applications, oxygen sensors are used when air quality or oxygen delivered to a patient needs to be monitored. In fresh air, the concentration of oxygen is 20.9% and air samples containing less than 18% oxygen are considered dangerous. In industrial applications, oxygen sensors are used to detect the

TS1003 Rev. 1.0 Page 9 The circuit utilizes the classic two op amp instrumentation amplifier topology with four resistors to set the gain. The equation is simply that of a noninverting amplifier as shown in the figure. The two resistors labeled R1 should be closely matched to each other as well as both resistors labeled R2 to ensure acceptable common- mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closed-loop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2π×R1C1). If the AC-CMRR is critical, then a matched capacitor to C1 should be included across the second resistor labeled R1. Because the TS1003 accepts rail-to-rail inputs, the input common mode range includes both ground and the positive supply of 1.5V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of 0.6μA, this circuit consumes a quiescent current of only ~1.3μA, yet it still exhibits a 1-kHz bandwidth at a circuit gain of 2. Driving Capacitive Loads While the TS1003’s internal gain-bandwidth product is 4kHz, it is capable of driving capacitive loads up to 50pF in voltage follower configurations without any additional components. In many applications, however, an operational amplifier is required to drive much larger capacitive loads. The amplifier’s output impedance and a large capacitive load create additional phase lag that further reduces the amplifier’s phase margin. If enough phase delay is introduced, the amplifier’s phase margin is reduced. The effect is quite evident when the transient response is observed as there will appear noticeable peaking/ringing in the output transient response. If the TS1003 is used in an application that requires driving larger capacitive loads , an isolation resistor between the output and the capacitive load should be used as illustrated in Figure 5. Table 1 illustrates a range of R ISO values as a function of the external CLOAD on the output of the TS1003. The power supply voltage used on the TS1003 at which these resistor values were determined empirically was 1.8V. The oscilloscope capture shown in Figure 6 illustrates a typical transient response obtained with a C LOAD = 1 00pF and an R ISO = 120kΩ. Note that as C LOAD is increased a smaller R ISO is needed for optimal transient response. In the event that an external R LOAD in parallel with CLOAD appears in the application, the use of an R ISO results in gain accuracy loss because the external series RISO forms a voltage-divider with the external load resistor RLOAD. External Capacitive Load, CLOAD External Output Isolation Resistor, RISO 0-50pF Not Required 100pF 120kΩ 500pF 50kΩ 1nF 33kΩ 5nF 18kΩ 10nF 13kΩ Figure 5: Using an External Resistor to Isolate a C LOAD from the TS1003’s Output VIN VOUT

TS1003 Rev. 1.0 Page 11 PACKAGE OUTLINE DRAWING 5-Pin SC70 Package Outline Drawing (N.B., Drawings are not to scale) 1 3 0.65 TYP. 1.30 TYP. 0.15 - 0.30 1.80 - 2.20 1.15 - 1.35 0.26 - 0.46 0.275 - 0.575 LEAD FRAME THICKNESS GAUGE PLANE NOTES: DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. DOES NOT INCLUDE INTER-LEAD FLASH OR PROTRUSIONS. DIE IS FACING UP FOR MOLDING. DIE IS FACING DOWN FOR TRIM/FORM.3. 5. CONTROLLING DIMENSIONS IN MILIMITERS. ALL SIDE 1.80 - 2.40 0.00 - 0.10 1.00 MAX 0.10 - 0.18 0.15 TYP. 8º - 12º 0º - 8º 0.800 – 0.925 0.40 – 0.55

4 ALL SPECIFICATION COMPLY TO JEDEC SPEC MO-203 AA

1. ALL SPECIFICATIONS REFER TO JEDEC MO-203 AA 7. LEAD SPAN/STAND OFF HEIGHT/COPLANARITY ARE CONSIDERED AS SPECIAL CHARACTERISTIC

0.10 MAX

Page 12 Silicon Laboratories, Inc. TS1003 Rev. 1.0 400 West Cesar Chavez, Austin, TX 78701 +1 (512) 416-8500 ▪ www.silabs.com PACKAGE OUTLINE DRAWING 5-Pin SOT23 Package Outline Drawing (N.B., Drawings are not to scale) NOTES: 1. Dimensions and tolerances are as per ANSI Y14.5M, 1982. 2. Package surface to be matte finish VDI 11~13. 3. Die is facing up mold and facing down for trim/form, ie, reverse trim/form. 4. The foot length measuring is based on the gauge plane method. 5. Dimensions are exclusive of mold flash and gate burr. 6. Dimensions are exclusive of solder plating. 7. All dimensions are in mm. 8. This part is compliant with EIAJ spec. and JEDEC MO-178 AA 9. Lead span/stand off height/coplanarity are considered as special characteristic. 2.80 - 3.00 2.60 - 3.00 1.50 - 1.75 0.95 0.950 TYP 0.30 - 0.50 0.00 - 0.15 10º TYP 10º TYP 10º TYP 0.09 - 0.205 10º TYP 0º- 8º 0.30 - 0.55 0.25 Gauge Plane

1.90 Max

0.09 – 1.45 0.50 – 0.70 1.50 – 1.75

0.50 Max

0.30 Min

0.20 Max

0.09 Min

0.90 - 1.30 0.60 – 0.80 TYP Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low -power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to chan ge without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves t he right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratori es assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in appli cations intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could creat e a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.

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