TA0102A

TA0102A TRIPATH | Alldatasheet

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Technical content

Features

¾ Class-T architecture ¾ Proprietary Digital Power Processing technology ¾ Supports wide range of output power levels ¾ “Audiophile” Quality Sound ¾ 0.05% THD+N @ 20W, 8Ω ¾ 0.03% IHF-IM @ 30W, 8Ω ¾ 80W @ 8Ω, 0.1% THD+N, VS = +/-45V ¾ 150W @ 4Ω, 0.1% THD+N, VS = +/-45V ¾ High Power ¾ 100W @ 8Ω, 1% THD+N, VS = +/-45V ¾ 170W @ 4Ω, 1% THD+N, VS = +/-45V ¾ High Efficiency ¾ Dynamic Range = 108 dB ¾ Requires only N-Channel MOSFET output transistors ¾ High power supply rejection ratio ¾ Mute input ¾ Outputs short circuit protected ¾ Over- and under-voltage protection ¾ Bridgeable, single-ended outputs ¾ 38-pin quad package Supports 100kHz BW of Super Audio CD and DVD-Audio (refer to Application Note for specifics) Typical Performance THD+N (%) Output Power (W) THD+N versus Output Power 20Hz - 22kHz BW f = 1kHz BBM = 25nS Vs = +/-45V Av = 14.8 ST STP19NB20 MOSFET 1 2002 5 10 20 50 100 0.01 0.02 0.05 0.1 0.2 0.5 RL = 4Ω RL = 8Ω

Tripath Technology, Inc. - Technical Information 2 TA0102A, Rev. 3.1/06.01 Absolute Maximum Ratings SYMBOL PARAMETER VALUE UNITS VS Supply Voltage (V SPOS & V SNEG ) +/-70 V V5 Positive 5V Bias Supply 6 V VN12 Supply Voltage: Nominal +12V referenced to V SNEG 18 V TSTORE Storage Temperature Range -40 to 150 °C TA Operating Free-air Temperature Range -20 to +80 °C Notes: Absolute Maximum Rati ngs indicate limits beyond which damage to the device may occur. Damage will occur to the device if VN12 is not supplied or falls below the recommended operating voltage when VS is within its recommended operating range. Operating Conditions SYMB OL PAR AME TE R MIN . TYP. MAX. U N ITS VS Supply Voltage (Vspos & Vsneg) +/-28 +/-49 V V5 Positive 5V Bias Supply 4.5 5 5.5 V VN12 Supply Voltage: Nominal +12V referenced to V SNEG 10.8 12 13.2 V Note: Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits.

Electrical Characteristics

Unless otherwise specified, TA = 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup. SYMB OL PAR AME TE R MIN . TYP. MAX. U N ITS Iq Quiescent Current +33.75V (no load, BBM0=BBM1=0) -33.75V +5V VN12 110 160 mA mA mA mA IS Source Current @ P OUT = 150W, 4Ω +33.75V -33.75V 5.1 5.2 A A I5 Source Current for 5V Bias Supply @ P OUT = 150W, RL = 4Ω 42 mA IVN12 Source Current for VN12 Supply @ P OUT = 150W, RL = 4Ω 46 mA VU Under Voltage (V spos & Vsneg) +/-28 V VO Over Voltage (V spos & Vsneg) +/-49 V VIH - MUTE High-level Input Voltage (MUTE) 3.5 V VIL - MUTE Low -level Input Voltage (MUTE) 1 V IDDMUTE Mute Supply Current +33.75V (no load, 145nS delay) -33.75V +5V VN12 0.315 0.475 mA mA mA mA VOH High-level Output Voltage (HMUTE & OVERLOADB) 3.5 V VOL Low -level Output Voltage (HMUTE & OVERLOADB) 1 V VTO C Over Current Sense Voltage Threshold 0.63 0.70 0.77 V AV Gain Ratio V O/VI, RIN = 0Ω 77 V/V Voffset Offset Voltage, no load, MUTE = Logic low (before nu lling) 500 mV Minimum and maximum limits are guaranteed but may not be 100% tested.

Tripath Technology, Inc. - Technical Information 3 TA0102A, Rev. 3.1/06.01 Performance Characteristics – Single Ended, Vs = +45V Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup. SYMB OL PAR AME TE R CON D ITION S MIN . TYP. MAX. U N ITS POUT Output Pow er (Continuous Average/Channel) THD+N = 0.1% R L = 8Ω R L = 4Ω THD+N = 1% R L = 8Ω R L = 4Ω 130 100 170 W W W W THD + N Total Harmonic Distortion Plus Nois e PO = 20W/Channel, RL = 8Ω 0.05 % IHF-IM IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF), R L = 4Ω POUT = 30W/Channel 0.05 % SNR Signal-to-Noise Ratio A-Weighted, P OUT = 88W/Ch, RL = 8Ω 98.5 dB CS Channel Separation 0dBr = 30W, R L= 8Ω 85 dB PSRR Pow er Supply Rejection Ratio f = 120Hz, Vripple = 100 mV 67 dB η P ow er E fficiency P OUT = 230W/Channel, RL = 4Ω 82 % eNOUT Output Noise Voltage A-Weighted, no signal, input shorted, DC offset nulled to zero 300 µV Performance Characteristics – Single Ended, Vs = +33.75V Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. TA = 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup. SYMB OL PAR AME TE R CON D ITION S MIN . TYP. MAX. U N ITS POUT Output Pow er (Continuous Average/Channel) THD+N = 0.1% R L = 8Ω R L = 4Ω THD+N = 1% R L = 8Ω R L = 4Ω 110 W W W W THD + N Total Harmonic Distortion Plus Nois e PO = 20W/Channel, RL = 8Ω 0.05 % IHF-IM IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF), R L = 4Ω POUT = 30W/Channel 0.03 % SNR Signal-to-Noise Ratio A-Weighted, P OUT = 47W/Ch, RL = 8Ω 100 dB CS Channel Separation 0dBr = 20W, R L= 8Ω 85 dB PSRR Pow er Supply Rejection Ratio f = 120Hz, Vripple = 100 mV 67 dB η P ow er E fficiency P OUT = 85W/Channel, RL = 8Ω 90 % eNOUT Output Noise Voltage A-Weighted, no signal, input shorted, DC offset nulled to zero 195 µV Minimum and maximum limits are guar anteed but may not be 100% tested. Notes: 1. V5 = +5V, VN12 = +12V referenced to V SNEG 2. Test/Application Circuit Values: D = MUR120T3 diodes, R IN = 22.1KΩ R D = 33ΩRS = 0.025ΩRG = 30Ω R OCR1 = ROCR2 = 0Ω, LF = 18uH (Amidon core T200-2) C F = 0.22uF, CD = 0.1uF, CIN = 1uF, CBY = 0.1uF Power Output MOSFET, M = ST STP19NB20 BBM0 =BBM1 = 1

Tripath Technology, Inc. - Technical Information 4 TA0102A, Rev. 3.1/06.01 Pin Description Pin Function Description

1 AGND Analog Ground

2 OVERLOADB Logic output. When low, indicate s that the level of the input signal has overloaded the amplifier.

3 V5 Positive 5 Volts

4 MUTE Logic input. When high, both amplifiers are muted. When low (grounded), both amplifiers are fully operational. 5, 6 IN2, IN1 Single-ended input (Channel 1 & 2) 7, 8 BBM0, BBM1 Break-bef ore-make timing control 9, 12 GNDKELVIN1, GNDKELVIN2 Kelvin connection to speaker ground (Channel 1 & 2) 10, 11 OCR2, OCR1 Over-current th reshold adjustment (Channel 1 & 2) 13, 14 OCS1L+, OCS1L- Over Current Sense resistor, Channel 1 low-side 15, 16 OCS1H-, OCS1H+ Over Current Sense resistor, Channel 1 high-side 17, 30 LO1COM, LO2COM Kelvin connection to s ource of low-side transistor (Channel 1 & 2) 18, 29 FDBKN1;FDBKN2 Feedback (Channel 1 & 2) 19 VN12 Voltage: +12 V from V SNEG. Refer to Application Information section. 20, 27 LO1, LO2 Low side gate drive output (Channel 1 & 2) 21, 26 HO1COM, HO2COM Kelvin connection to s ource of high-side transistor (Channel 1 & 2) 22, 25 HO1, HO2 High side gate drive output (Channel 1 & 2)

23 V SPOS Positive supply voltage

24 V SNEG Negative supply voltage

28 PGND Power Ground

31, 32 OCS2L-, OCS2L+ Over Current Sense resistor, Channel 2 low-side 33, 34 OCS2H-, OCS2H+ Over Current Sense resistor, Channel 2 high-side 35 HMUTE Logic output. When high, indica tes that the output stages of both amplifiers are shut off and muted. 36, 37, 38 NC Not Connected - Must Be Left Floating

38 PIN QUAD MODULE PIN OUT TOP VIEW

9 1 0 1 1 1 2 1 31 41 5 1 6 1 71 8 1 9 AGND OVERLOADB IN2 IN1 BBM0 BBM1 MUTE 38 37 36 35 34 33 32 31 30 29 28 LO2 HO2COM HO2 V SNEG VSPOS HO1 H01COM LO1 GND KELVIN1 OCR2 OCR1 GND KELVIN2 OCS1L+ OCS1L- OCS1H- OCS1H+ LO1COM FDBKN1 VN12 NC NC NC HMUTE OCS2H+ OCS2H- OCS2L+ OCS2L- LO2COM FDBKN2 PGND

Tripath Technology, Inc. - Technical Information 5 TA0102A, Rev. 3.1/06.01 TEST/APPLICATION CIRCUIT Figure 2 Processing Modulation TA0102A MUTE OVERLOADB IN1 IN2 PGndAGnd RIN RIN OCS1H- HO1 HO1COM OCS1L+ OCR1 OCR2 FDBKN1 VN12 RS VSPOS M ROCR1 ROCR2 BBM0 BBM1 RL NC 36 12 8 OCS1H+ OCS1L-14 LO1COM17

9 GNDKELVIN1

NC - Not Connected (Must Be Left Floating) CIN CIN Note - Heavy Lines Indicate High-Current Paths RG D CBY LF CF 100uF M RG D CBY RS 100uF VSNEG RD CD Processing Modulation OCS2H- HO2 HO2COM OCS2L+ RS VSPOS M RL OCS2H+ OCS2L-31 LO2COM30

12 GNDKELVIN2

M RG D CBY RS 100uF VSNEG RD CD LO1

29 FDBKN2

.1uF .1uF .1uF .1uF 0.1 uF 10KΩ 0.1 uF 1MΩ 1MΩ 10KΩ 0.1 uF 1MΩ 1MΩ

Tripath Technology, Inc. - Technical Information 6 TA0102A, Rev. 3.1/06.01 Typical Performance at Vs = +45V 20Hz - 22kHz BW BBM = 25nS Pout = 30W/Channel V S = +/-45V Av = 14.8 ST STP19NB20 MOSFET THD+N (%) Frequency (Hz) THD+N versus Frequency RL = 4Ω 10 20k20 50 100 200 500 1k 2k 5k 10k 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 FFT (dBr) Frequency (Hz) 60 30k100 200 500 1k 2k 5k 10k 20k -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 Intermodulation Performance RL = 4Ω 10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 25nS Pout = 30W/Channel V S = +/-45V 0dBr = 11Vrms Av = 14.8 ST STP19NB20 MOSFET Frequency (Hz) 20 20k50 100 200 500 1k 2k 5k 10k -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Channel Separation (dBr) Channel Separation versus Frequency RL = 4Ω 20Hz - 22kHz BW BBM = 25nS Pout = 30W/Channel VS = +/-45V Av = 14.8 ST STP19NB20 MOSFET -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 Noise (dBv) Frequency (Hz) 20 20k50 100 200 500 1k 2k 5k 10k A-Weighted Noise FFT 20Hz - 22kHz BW BBM = 25nS Pout = 0 VS = +/-45V RL = 4Ω Av = 14.8 ST STP19NB20 MOSFET THD+N (%) Output Power (W) THD+N versus Output Power 20Hz - 22kHz BW f = 1kHz BBM = 25nS Vs = +/-45V Av = 14.8 ST STP19NB20 MOSFET 1 2002 5 10 20 50 100 0.01 0.02 0.05 0.1 0.2 0.5 RL = 4Ω RL = 8Ω Efficiency versus Output Power RL = 4Ω 0 50 100 150 200 250 Output Power (W) Efficiency (%) 22Hz - 22kHz BW f = 1kHz BBM = 145nS V S = +/-45V Av = 20.75 ST STP19NB20 MOSFET

Tripath Technology, Inc. - Technical Information 7 TA0102A, Rev. 3.1/06.01 Typical Performance at Vs = +33.75V 0.01 0.02 0.05 0.1 0.2 0.5 10 20k20 50 100 200 500 1k 2k 5k 10k THD+N (%) Frequency (Hz) BBM = 25nS Pout = 20W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET 22kHz BW 30kHz BW THD+N versus Frequency versus Bandwidth, RL = 8Ω 0.01 0.02 0.05 0.1 0.2 0.5 10 20k20 50 100 200 500 1k 2k 5k 10k BBM = 25nS Pout = 30W/Channel V S = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET THD+N (%) Frequency (Hz) 22kHz BW 30kHz BW THD+N versus Frequency versus Bandwidth, RL = 4Ω 0.01 0.02 0.05 0.1 0.2 0.5 10 20k20 50 100 200 500 1k 2k 5k 10k THD+N versus Frequency versus Break Before Make, RL = 4Ω THD+N (%) Frequency (Hz) 20Hz - 22kHz BW Pout = 30W/Channel V S = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET 25nS 65nS 105nS 145nS 0.01 0.02 0.05 0.1 0.2 0.5 10 20k20 50 100 200 500 1k 2k 5k 10k 25nS THD+N (%) Frequency (Hz) 20Hz - 22kHz BW Pout = 20W/Channel VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET THD+N versus Frequency versus Break Before Make, RL = 8Ω 145nS 65nS 105nS 0.01 0.02 0.05 0.1 0.2 0.5 1 2002 5 10 20 50 100 THD+N versus Output Power THD+N (%) Output Power (W) 20Hz - 22kHz BW f = 1kHz BBM = 25nS V S = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET 4Ω8Ω Efficiency versus Output Power 100 0 25 50 75 100 125 150 175 Output Power (W) Efficiency (%) RL = 8Ω RL = 4Ω 22Hz - 22kHz BW f = 1kHz BBM = 145nS VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET

Tripath Technology, Inc. - Technical Information 8 TA0102A, Rev. 3.1/06.01 Typical Performance Channel Separation versus Frequency -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k50 100 200 500 1k 2k 5k 10k Frequency (Hz) Channel Separation (dBr) 20Hz - 22kHz BW BBM = 25nS Pout = 30W/Channel @ 4 Ω Pout = 20W/Channel @ 8Ω VS = +/-33.75V Av = 14.8 ST STP19NB20 MOSFET A-Weighted Noise FFT -140 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 20k50 100 200 500 1k 2k 5k 10k Frequency (Hz) Noise (dBv) 20Hz - 22kHz BW BBM = 25nS Pout = 0 VS = +/-33.75V RL = 4Ω Av = 14.8 ST STP19NB20 MOSFET -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 60 30k100 200 500 1k 2k 5k 10k 20k Intermodulation Performance RL = 8Ω Frequency (Hz) 10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 25nS Pout = 20W/Channel V S = +/-33.75V 0dBr = 13Vrms Av = 14.8 ST STP19NB20 MOSFET FFT (dBr) Intermodulation Performance RL = 4Ω -100 +10 -90 -80 -70 -60 -50 -40 -30 -20 -10 60 30k100 200 500 1k 2k 5k 10k 20k Frequency (Hz) 10Hz - 80kHz BW 19kHz, 20kHz, 1:1 BBM = 25nS Pout = 30W/Channel V S = +/-33.75V 0dBr = 11Vrms Av = 14.8 ST STP19NB20 MOSFET FFT (dBr) 0.01 0.1 1 10 100 1000 Output Power (W) THD+N (%) 33.75V27V 20Hz - 22kHz BW f = 1kHz BBM = 25nS Av = 14.8 ST STP19NB20 MOSFET 50V THD+N versus Output Power versus Supply Voltage RL = 4Ω 50V 0.01 0.1 1 10 100 1000 Output Power (W) THD+N (%) THD+N versus Output Power versus Supply Voltage RL = 8Ω 20Hz - 22kHz BW f = 1kHz BBM = 25nS Av = 14.8 ST STP19NB20 MOSFET 33.75V 27V

understanding its operation. Figure 3. Simplified TA0102A Amplifier filtered to obtain amplified audio.

Tripath Technology, Inc. - Technical Information 10 TA0102A, Rev. 3.1/06.01 The processor portion of the TA0102A is operated from a 5-volt supply (between V5 and AGND). In the generation of the complementary modulation pattern for the output MOSFETs, the processor inserts a “break-before-make” dead time between when it turns one transistor off and it turns the other one on in order to minimize shoot-through currents in the MOSFETs. The dead time can be programmed by setting the break-before-make control bits, BBM0 and BBM1. Feedback information from the output of the half-bridge is supplied to the processor via FDBKN1. Additional feedback information to account for ground bounce is supplied via GNDKELVIN1. The MOSFET drivers in the TA0102A are operated from voltages obtained from VN12 and LO1COM for the low-side driver, and V BOOT (generated internal to the TA0102A) and HO1COM for the high- side. Only N-Channel MOSFETs are required for both the top and bottom of the half bridge. VN12 must be a stable 12V above VSNEG. The gate resistors, RG, are used to control MOSFET slew rate and thereby minimize voltage overshoots. Over- and Under-Voltage Protection The TA0102A senses the power rails through V SPOS and V SNEG for over- and under-voltage conditions. The over- and under-voltage limits are Vo and Vu respectively as specified in the shuts off the output stages of the amplifiers and asserts a logic level high on HMUTE. The removal of the over-voltage or under-vol tage condition returns the TA0102A to normal operation and returns HMUTE to a logic level low. Please note that the limits specified in the Electrical Characteristics table are at 25°C and these limits may change over temperature. Over-current Protection The TA0102A has over-current protection circuitry to protect itself and the output transistors from short-circuit conditions. The TA0102A uses the voltage across a resistor, R S (measured via OCS1H+, OCS1H-, OCS1L+ and OCS1L-), that is in series with each output MOSFET to detect an over-current condition. RS and ROCR are used to set the over-current threshold. The OCS pins must be Kelvin connected for proper operation. See “Circuit Board Layout” in Applications Information for details. An over-current condition will cause t he TA0102A to shut off t he output stages of the amplifiers and supply a logic level high on HMUTE. The occurrence of an over-current condition is latched in the TA0102A and can be cleared by toggling the MUTE input or cycling power. Overload When logic low, the OVERLOADB pin indicates that the level of the input signal has overloaded the amplifier and that the audio output signal is starting to distort. The OVERLOADB signal is active only when an overload is present. The OVERLOAD B signal can be used to control a distortion indicator light or LED through a simple buffer circuit. Mute When a logic high signal is supplied to MUTE, both amplifier channels are muted (both high- and low-side transistors are turned off) and a logic leve l high is output on the HMUTE pin. When a logic level low is supplied to MUTE, both amplifiers ar e fully operational and a logic level low is supplied on HMUTE. There is a delay of approximately 200 milliseconds between the de-assertion of MUTE and the un-muting of the TA0102A.

Tripath Technology, Inc. - Technical Information 11 TA0102A, Rev. 3.1/06.01

Application Information

Amplifier Gain and Input Resistor Selection The value of the input resistor, R IN, is based on the required voltage gain, A V, of the amplifier according to: A V = 387 x103/(RIN + 5000) where RIN = Input resistor value in ohms. Input Capacitor Selection CIN can be calculated once a value for R IN has been determined. C IN and R IN determine the input low-frequency pole. Typically this pole is set at 10Hz. CIN is calculated according to: C IN = 1/((2π x fP)(RIN + 5000)) where: R IN = Input resistor value in ohms. f P = Input low frequency pole (typically 10Hz). DC Offset Adjust While the DC offset voltages that appear at the speaker terminals of a TA0102A amplifier are typically small, Tripath recommends that any offsets during operation be nulled out of the amplifier with a circuit like the one shown connected to IN1 and IN2 in the Test/Application Circuit. Nulling should be performed with the inputs shorted to ground. It should be noted that even after nulling, the DC voltage on the output of a TA0102A amplifier with no load in mute mode is approximately 2.5V. This offset does not need to be nulled. The output impedance of the amplifier in mute mode is approximately 10 KOhms. This means that the 2.5V drops to essentially zero when a typical load is connected. Supply Voltage and Output Power The relationship between the bipolar power supply voltage needed, V S, for a given RMS output power, POUT, into a given load, RL, at a given level of THD (total harmonic distortion) is approximated by: V S = (2 x RL x POUT) 0.5/(K x RL/(RL + RON + RS + RCOIL)) where: RON = The at-temperature RDSON of the output transistors, M. RCOIL = Resistance of the output filter inductor. RS = Sense Resistor K = THD Factor, a number fixed by the algorit hms in the TA0102A’s signal processor that provides the relationship between THD at full output power of the amplifier and V S. K corresponds to THD at full output power as follows: THD K 0.1% 0.83 1% 0.95 10% 1.09 Typical measurement graphs of P OUT versus supply voltage for various levels of THD are also included in this data sheet to help determine the supply voltage.

Tripath Technology, Inc. - Technical Information 12 TA0102A, Rev. 3.1/06.01 Bridged Operation Note that the two channels of a TA0102A amplifier can be used to provide a single, bridged amplifier of almost four times the output power of one of the single-ended amp lifier channels. To configure a bridged amplifier, the input to one TA0102A channel mu st be the inverted signal of the input to the other channel. Low-frequency Power Supply Pumping A potentially troublesome phenomenon in single-ended switching amplifiers is power supply pumping. This is caused by current from the out put filter inductor flowing into the power supply output filter capacitors in the oppos ite direction as a DC load would dr ain current from them. Under certain conditions (usually low-frequency input signal s), this current can cause the supply voltage to “pump” (increase in magnitude) and eventually cause over-voltage/under-v oltage shut down. Moreover, since over/under-voltage are not “latched” shutdowns, the effect would be an amplifier that oscillates between on and off states. If a DC offset on the order of 0.3V is allowed to develop on the output of the amplifier (see “DC Offset Adjust ”), the supplies can be boosted to the point where the amplifier’s over-voltage protection triggers. One solution to the pumping issue is to use la rge power supply capacitors to absorb the pumped supply current without significant voltage boost. The low frequency pole used at the input to the driver determines the value of the supply capacitor required. This works for AC signals only. Another solution to the supply pumping problem uses the fact that music has low frequency information that is correlated in both channels (it is in phase). This information can be used to eliminate boost by putting the two channels of a TA 0102A amplifier out of phase with each other. This works because each channel is pumping out of phase with the other, and the net effect is a cancellation of pumping currents. The phase of the audio signals needs to be corrected by connecting one of the speakers in the opposite polarity as the other channel. CONTACT INFORMATION World Wide Sales Offices United States & Europe SE Asia & China Japan & Korea Jim Hauer Eugene Hsu Osamu Ito jhauer@tripath.com ehsu@tripath.com ito@tripath.com 408.567.3089 886.2.2653.7428 81.42.334.2433 TRIPATH TECHNOLOGY, INC

3900 Freedom Circle

408.567.3000 www.tripath.com