TAA2008

TAA2008 TRIPATH | Alldatasheet

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Tripath Technology, Inc. - Technical Information 1 TAA2008 –KLi/1.0/05.06 TAA2008 STEREO 9W (8 Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING™ TECHNOLOGY GENERAL DESCRIPTION The TAA2008 is a 9W/ch continuous average two-channel Class-T Digital Audio Power Amplifier IC using Tripath’s proprietary Digital Power Processing™ technology. The TAA2008, in a QFN package, along with extremely high efficiency, allows for a very compact amplifier design. Class-T amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers.

APPLICATIONS

¾ LCD TV’s ¾ LCD Monitors ¾ Plasma TV’s ¾ Computer/PC Multimedia ¾ Battery Powered Systems BENEFITS ¾ Fully integrated solution with FETs ¾ Compact packaging and board design ¾ Reduced system cost with no heat sink ¾ Dramatically improves efficiency versus Class- AB ¾ Signal fidelity equal to high quality linear amplifiers ¾ High dynamic range compatible with digital media such as CD, DVD, and Internet audio ¾ Capable of driving a wide range of load impedances TYPICAL PERFORMANCE

FEATURES

¾ Class-T architecture ¾ Single Supply Operation ¾ “Audiophile” Quality Sound ¾ 0.025% THD+N @ 5W, 8Ω ¾ 0.1% IHF-IM @ 1W, 8Ω ¾ 6.3W @ 8Ω, 0.1% THD+N ¾ 3.5W @ 16Ω, 0.1% THD+N ¾ High Power ¾ 14.25W @ 6Ω, 10% THD+N ¾ 9W @ 8Ω, 10% THD+N ¾ 5W @ 16Ω, 10% THD+N ¾ Extremely High Efficiency ¾ 89% @ 5W, 16Ω ¾ 86% @ 9W, 8Ω ¾ Dynamic Range = 98.5 dB ¾ Mute and Sleep modes ¾ Improved turn-on & turn-off pop suppression ¾ Over-current protection with automatic restart circuit ¾ Over-temperature protection ¾ Space saving 32-pin 8mm x 8mm x 1mm QFN package with exposed pad 0.01 0.02 0.05 0.1 0.2 0.5 1 202 3 4 5 6 7 8 9 10 VDD = 12V f = 1kHz AV = 12V/V BW = 22Hz - 20kHz(AES17) RL =16Ω RL =8Ω RL =6Ω RL =4Ω THD+N versus Output Power Output Power (W) THD+N (%) PGND1 5VGEN DCAP2 DCAP1 V5D AGND1 INV2 DGND PGND2 FAULT SLEEP AGND3 BIASCAP OAOUT2 24 CPUMP VDDA NC OUTP2 OUTM2 VDD1 NC OUTP1 OUTM1 VDD2 NC MUTE INV1 V5A AGND2 OVRLDB REF OAOUT1

Tripath Technology, Inc. - Technical Information 2 TAA2008 –KLi/1.0/05.06 ABSOLUTE MAXIMUM RATINGS (Note 1) SYMBOL PARAMETER Value UNITS VDD Supply Voltage 16 V V5 Input Section Supply Voltage 6.0 V SLEEP SLEEP Input Voltage -0.3 to 6.0 V MUTE MUTE Input Voltage -0.3 to V5+0.3 V TSTORE Storage Temperature Range -40 to 150 °C TA Operating Free-air Temperature Range 0 to 70 °C TJ Junction Temperature 150 °C ESDHB ESD Susceptibility – Human Body Model (Note 2) 2000 V ESDMM ESD Susceptibility – Machine Model (Note 3) 200 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Note 2: Human body model, 100pF discharged through a 1.5KΩ resistor. Note 3: Machine model, 220pF – 240pF discharged through all pins. OPERATING CONDITIONS (Note 4) SYMBOL PARAMETER MIN. TYP. MAX. UNITS VDD Supply Voltage (Note 5) 8.5 12 14.0 V VIH High-level Input Voltage (MUTE, SLEEP) 3.5 V VIL Low-level Input Voltage (MUTE, SLEEP) 1 V Note 4: Recommended Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics for guaranteed specific performance limits. Note 5: Operation above 13.2V requires the use of low and high side schottky diodes as well as 220uF for CSW. See the Application Section for additional information THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNITS θJA Junction-to-ambient Thermal Resistance (note 6) 22 °C/W Note 6: The θJA value is based on the exposed pad being soldered down to the printed circuit board. The exposed pad must be soldered to an exposed copper area on the printed circuit board for proper thermal and electrical performance.

Tripath Technology, Inc. - Technical Information 3 TAA2008 –KLi/1.0/05.06 ELECTRICAL CHARACTERISTICS (Note 7) See Test/Application Circuit. Unless otherwise specified, VDD = 12V, f = 1kHz, Measurement Bandwidth = 20kHz, RL = 8Ω, TA = 25 °C, package exposed pad soldered to the printed circuit board. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNITS PO Output Power (Continuous Average/Channel) THD+N = 0.1% RL = 6Ω R L = 8Ω R L = 16Ω THD+N = 10% RL = 6Ω R L = 8Ω R L = 16Ω VDD = 13.2V, THD+N=10% R L = 6Ω R L = 8Ω R L = 16Ω TBD 6.3 3.5 14.25 6.3 W W W W W W W W W IDD,MUTE Mute Supply Current MUTE = V IH 31 36 mA IDD, SLEEP Sleep Supply Current SLEEP = V IH 0.25 2 mA Iq Quiescent Current V IN = 0 V 61 75 mA THD + N Total Harmonic Distortion Plus Noise PO = 5W/Channel 0.022 % IHF-IM IHF Intermodulation Distortion 19kHz, 20kHz, 1:1 (IHF) 0.1 0.5 % SNR Signal-to-Noise Ratio A-Weighted, POUT = 9W, RL = 8Ω 98.5 dB CS Channel Separation f = 1 kHz

20 Hz < f < 20 kHz

PSRR Power Supply Rejection Ratio VDD = 9V to 13.2V Vripple = 100mVrms, f=1kHz 65 75 dB dB η Power Efficiency POUT = 5W/Channel, RL = 16Ω 89 % VOFFSET Output Offset Voltage No Load, MUTE = Logic Low 50 150 mV VOH High-level output voltage (FAULT & OVERLOAD) 3.5 V VOL Low-level output voltage (FAULT & OVERLOAD) 1 V eOUT Output Noise Voltage A-Weighted, input AC grounded 100 150 µV Note 7: Minimum and maximum limits are guaranteed but may not be 100% tested.

Tripath Technology, Inc. - Technical Information 4 TAA2008 –KLi/1.0/05.06 PIN DESCRIPTION TAA2008 PINOUT Pin Function Description 1, 29 OAOUT2, OAOUT1 Input stage output pins. 2, 30 INV2, INV1 Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with approximately 2.4VDC bias. 3 BIASCAP Input stage bias voltage (approximately 2.4VDC). 4, 24, AGND3, AGND1, AGND2 Analog Ground 5 SLEEP When set to logic high, device goes into low power mode. If not used, this pin should be grounded

6 FAULT A logic high output indicates thermal ov erload, or an output is shorted to ground,

or another output. 7, 18 PGND2, PGND1 Power Grounds (high current) 8 DGND Digital Ground. Connect to AGND locally (near the TAA2008). 10, 12; 15, 13 OUTP2 & OUTM2; OUTP1 & OUTM1 Bridged output pairs 11, 14 VDD2, VDD1 Supply pins for high current H-bridges, nominally 12VDC. 17 VDDA Analog 12VDC. Connect to same supply as VDD1 and VDD2.

19 CPUMP Charge pump output (nominally 10V above VDDA)

20 5VGEN Regulated 5VDC source used to suppl y power to the input section (pins 23 and 28). 21,22 DCAP2, DCAP1 Charge pump switching pins. DCAP1 (pin 22) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 21) is level shifted 10 volts above DCAP1 (pin 22) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1. 23, 28 V5D, V5A Digital 5VDC, Analog 5VDC 25 REF Internal reference voltage; approximately 1.0 VDC. 26 OVERLOADB A logic low output indicates t he input signal has overloaded the amplifier. 31 MUTE When set to logic high, both amplifiers are muted and in idle mode. When low (grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used. 9, 16, 32 NC Not connected. Not bonded internally. PGND1 5VGEN DCAP2 DCAP1 V5D AGND1 INV2 DGND PGND2 FAULT SLEEP AGND3 BIASCAP 32-pin QFN (Top View) OAOUT2 24 CPUMP VDDA NC OUTP2 OUTM2 VDD1 NC OUTP1 OUTM1 VDD2 NC MUTE INV1 V5A AGND2 OVRLDB REF OAOUT1

Tripath Technology, Inc. - Technical Information 5 TAA2008 –KLi/1.0/05.06 APPLICATION / TEST CIRCUIT TAA2008 RL 8Ω or 16 Ω MUTE FAULT (connect to MUTE for auto restart) OVERLOADB (+12V) CI 2.2uF OAOUT1 OAOUT2 INV 1 INV 2 OUTP1 OUTM1 OUTP2 OUTM2 VD D A 5VGEN BIASCAP DCA P2 DCA P1 CI 2.2uF CA 0.1uF CD 0.1uF CPUMP RF 20K Ω RZ 10Ω, 1/4W RZ 10Ω, 1/4W CZ 0.22uF CP 1uF SLEEP +12V 0.1uF REF RREF 8.25KΩ , 1% 1M Ω For VDD voltages above 13.2V, output diodes (D O ) should be used and the value of C SW should be increased to 220uF. All Diodes are Motorola MBRS130T3 or equivalent. VD D 1 PGND1 VD D 1 PGND1 VD D 2 VD D 2 PGND2 PGND2 Note: Analog and Digital/Pow er Grounds must be connected locally at the TAA2008 CS 0.1uF CS 0.1uF To Pin 20 V5D AGN D 1 AGN D 2 V5A CS 0.1uFDGND VD D 1 PGND2 18PGND1 VD D 2 VD D Processing Modulation Processing Modulation Co 0.22uF Lo 10uH, 2A (Pin 4) Analog Ground Digital/Pow er Ground (Pin 18) (Pin 18) (Pin 7) (Pin 7) To Pins 23,28 RI 20K Ω (P in 24) RF 20K Ω RI 20K Ω AGN D 34 100uF, 16V CSW Co 0.22uF Lo 10uH, 2A RL 8Ω or 16 Ω Lo 10uH, 2A Lo 10uH, 2A Co 0.22uF Co 0.22uF CZ 0.22uF CSW 0.1uF CSW 0.1uF CS 0.1uF DO DO CDO 0.01uF (Pin 18) (P in 7) NC CDO 0.01uF NC NC DO DO VD D 1 VD D 2 VD D 2 VD D 1 N.C.

Tripath Technology, Inc. - Technical Information 6 TAA2008 –KLi/1.0/05.06 EXTERNAL COMPONENTS DESCRIPTION (Refer to the Application/Test Circuit) Components Description RI Inverting Input Resistance to provide AC gain in conjunction with R F. This input is biased at the BIASCAP voltage (approximately 2.4VDC). RF Feedback resistor to set AC gain in conjunction with RI; )R/R(12A IFV = . Please refer to the Amplifier Gain paragraph in the Application Information section. CI AC input coupling capacitor which, in conjunction with R I, forms a highpass filter at )CR2(1f IIC π= RREF Bias resistor. Locate close to pin 25 (REF) and ground at pin 24 (AGND1). CA BIASCAP decoupling capacitor. Locate close to pin 3 (BASCAP) and ground at pin 4 (AGND3). CD Charge pump input capacitor. This capa citor should be connected directly between pins 21 (DCAP2) and 22 (DCAP1) and located physically close to the TAA2008. CP Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 19 (CPUMP) and pin 17 (VDDA). Please observe the polarity shown in the Application/ Test Circuit. CS Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit. CSW Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing (0.1uF) and bulk capacitor (100uF/220uF) should have good high frequency performance including low ESR and low ESL. Recommended capacitor families include Nichicon HE series and Panasonic FM series for thru-hole types. Qualified SMT electrolytics include Nichicon UD series and Panasonic FK series. CZ Zobel Capacitor. RZ Zobel resistor, which in conjunction with C Z, terminates the output filter at high frequencies. The combination of RZ and CZ minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency. DO Schottky diodes that minimize undersh oots and overshoots of the outputs with respect to power ground and VDD during switching transitions. These components are recommended for supply voltages above 13.2V. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin. LO Output inductor, which in conjunction with C O and CDO, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of )CL2(1 O TOTCf π= and a quality factor of TOTTOTL CRQ CL2 O= where CTOT = CO || 2 * CDO. CO Output capacitor. CDO Differential Output Capacitor. Differe ntial noise decoupling for reduction of conducted emissions. Must be located near chassis exit point for maximum effectiveness.

Tripath Technology, Inc. - Technical Information 7 TAA2008 –KLi/1.0/05.06 TYPICAL PERFORMANCE 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 20 20k50 100 200 500 1k 2k 5k 10k Hz THD+N versus Frequency VDD = 12V PO = 1W BW = 22Hz - 22khz RL = 8 Ω RL = 16 Ω 0.01 0.02 0.05 0.1 0.2 0.5 1 202 3 4 5 6 7 8 9 10 THD+N versus Output Power RL = 6 Ω f = 1kHz AV = 12V/V BW = 22Hz - 20kHz(AES17) VDD =12V Output Power (W) THD+N (%) VDD =13.2V Eff (%) Total Output Power (W ) Pdiss (W) Efficiency and Power Dissipation versus Total output Power 201612840 Efficiency Power Dissipation V DD = 12V RL = 8 Ω f= 1kHz BW = 22Hz - 20kHz(AES17) 100 Total Output Power (W ) Eff (%) Pdiss (W) Efficiency and Power Dissipation versus Total output Power 10 1286420 Efficiency Power Dissipation VDD = 12V RL = 16 Ω f= 1kHz BW = 22Hz - 20kHz(AES17) 100 Total Output Power (W) 2520151050 Eff (%) 100 Pdiss (W) Efficiency and Power Dissipation versus Total output Power Efficiency Power Dissipation VDD = 12V RL = 6 Ω f= 1kHz BW = 22Hz - 20kHz(AES17) Total Output Power (W ) 2520151050 Eff (%) 100 Pdiss (W) Efficiency and Power Dissipation versus Total output Power Efficiency Power Dissipation VDD = 13.2V RL = 6 Ω f= 1kHz BW = 22Hz - 20kHz(AES17)

Tripath Technology, Inc. - Technical Information 8 TAA2008 –KLi/1.0/05.06 TYPICAL PERFORMANCE Frequency (Hz) Intermodulation Distortion 19kHz, 20kHz 1:1 PO = 1W VDD = 12V RL = 8 Ω 32k FFT FS = 65kHz BW = <10Hz - 80kHz 50 100 200 500 1k 2k 5k 10k 20k 30k -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 FFT (dBr) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B V 20 20k50 100 200 500 1k 2k 5k 10k Hz Noise Fl oor VDD = 12V RL = 8 Ω 32k FFT F S = 65kHz BW = 22Hz - 20kHz(AES17) Output Power versus Supply Voltage Supply Voltage (V) Output Power (W) 109 11 12 13 14 RL = 8 Ω f = 1kHz BW= 22Hz - 20kHz (AES17) THD+N = 10% THD+N = 1% Output Power versus Supply Voltage Supply Voltage (V) Output Power (W) 9 10 11 12 13 14 THD+N = 10% RL = 16 Ω f = 1kHz BW= 22Hz - 20kHz(AES17) THD+N = 1% Output Power versus Supply Voltage Supply Voltage (V) Output Power (W) 1091 1 1 2 1 3 1 4 RL = 6 Ω f = 1kHz BW= 22Hz - 20kHz (AES17) THD+N = 10% THD+N = 1% Maximum Supply Current versus Supply Voltage Supply Voltage (V) Max. Supply Current (I DC ) THD=N = 10% f= 1kHz BW= 22Hz - 20kHz (AES17) Both chanels driv en RL = 16 Ω RL = 8 Ω 9 10 11 12 13 14 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 RL = 6 Ω

Tripath Technology, Inc. - Technical Information 9 TAA2008 –KLi/1.0/05.06 TYPICAL PERFORMANCE

APPLICATION INFORMATION

The TAA2008 is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground, at high speeds, while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TAA2008 to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath’s layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please contact Tripath Technology for further information regarding reference design material regarding the TAA2008. Output Stage layout Considerations and Component Selection Criteria Proper PCB layout and component selection is a major step in designing a reliable TAA2008 power amplifier. The supply pins require proper decoupling with correctly chosen components to achieve optimal performance and reliability. The output pins need proper protection to keep the outputs from going below ground and above VDD. -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 d B r 20 20k50 100 200 500 1k 2k 5k 10k Hz TTTT TT T T Channel Separation VDD = 12V RL = 8 Ω PO = 1W BW = 22Hz - 22kHz VDD = 12V PO = 1W RL = 8 Ω RL = 16 Ω RL = 6 Ω -2.5 -1.5 -0.5 +0.5 +1.5 +2.5 d B r 20 20k50 100 200 500 1k 2k 5k 10k Hz Frequency Response

Tripath Technology, Inc. - Technical Information 10 TAA2008 –KLi/1.0/05.06 The above layout shows ideal component placement and routing for supply decoupling. C2 and C3 are .1uF surface mount capacitors placed directly across their respective VDD and PGND pins. C1 is a low ESR bulk capacitance electrolytic (at least 100uF). C1’s VDD pin is routed to the TAA2008’s VDD1 and VDD2 pins on the opposite side of the PCB as the TAA2008. Vias return the supply trace to the TAA2008 side of the PCB at the VDD1 and VDD2 pins. This arrangement allows C1’s PGND pin to have a low impedance return path to PGND1 and PGND2 through the PCB’s ground plane and allows the output traces (OUTM1, OUTP1, OUTM2, AND OUTP2) to be routed directly to the low pass filter. By having C1’s supply pins directly across the TAA2008’s VDD and PGND pins supply overshoots will be controlled and mean supply elevation will be reduced. Effectively decoupling VDD will shunt any power supply trace length inductance. The construction of the bulk electrolytic is critical. This capacitor should be a low ESR, ripple rated SMT, or through-hole component. Water based through-hole electrolytic capacitors offer very cost competitive solutions with extremely low impedance (ESR). These include Nichicon HE series and Panasonic FM series. Qualified SMT electrolytics include Nichicon UD series and Panasonic FK series. Panasonic FC capacitors also work well but are likely more costly with no improvement in performance over the capacitor families mentioned above. The output L1 – L4 should be placed close to the TAA2008 without compromising the locations of the closely placed supply decoupling capacitors. The purpose of placing the inductors close to the TAA2008 output pins in to reduce the trace length of the switching outputs. This will aid in reducing radiated emissions. For VDD voltages above 13.2V, or on designs where a tight layout cannot be adhered to due to physical constraints, it is strongly recommended that the value of C SW is increased to 220uF and that both low and high side schottky diodes are implemented. These changes will ensure that the output over shoots will not exceed the absolute maximum rating of 16V. The output diodes, DO, should be located as close to the output pins as possible and returned to their respective PGND or VDD, as shown in the Application / Test Diagram. Please see the External Component Description section on page 6 for more details on the above- mentioned components. The Application/ Test Circuit refers to both supply decoupling capacitors as CSW, and the output diodes as DO. TAA2008 Amplifier Gain The ideal gain of the TAA2008 is set by the ratio of two external resistors, RI and RF, and is given by the following formula: I F I O R R12V V −= where VI is the input signal level and VO is the differential output signal level across the speaker. Please note that VO is 180° out of phase with VI.

Tripath Technology, Inc. - Technical Information 11 TAA2008 –KLi/1.0/05.06 The ideal gain of the TAA2008 is 12V/V, whereas typical values are: AV = 11.7V/V for 8Ω. The low frequency roll-off characteristic is dictated by the choice of CI and RI. The –3dB frequency is: I I 3dB RC 2Π 1f =− The figure below shows the roll-off characteristic for different values of CI, assuming an RI value of 20kΩ. As can be seen, the larger the value of CI, the lower the –3dB cutoff point. On the EB- TAA2008, a value of 2.2µF is used for CI which creates a nearly flat response down to 20Hz. In many cases, a lower value of CI can be used because the speakers used in LCD TV’s or similar applications do not have the ability to reproduce low frequency signals. d B r 20 20k50 100 200 500 1k 2k 5k 10k Hz VDD = 12V P O = 1W R L = 8 Ω Frequency Response CI = 2.2uF CI = 1.0uF CI = 0.47uF CI = 0.22uF Mute Pin The mute pin must be driven to a logic low or logic high state for proper operation. To enable the amplifier, connect the mute pin to a logic low. To enable the mute function, connect the mute pin to a logic high signal. Please note that the mute pi n is a 5V CMOS input pin and the mute signal should be de-bounced to eliminate a possibility of falsely muting. When in mute, the internal processor bias voltages are still active in the TAA2008. This minimizes any turn on pop caused by charging the input coupling capacitor. It is recommended that the mute is held high during power up or power down to eliminate audible transients. If turn-on and/or turn-off noise is still present with a TAA2008 amplifier, the cause may be other circuitry external to the TAA2008 such as an audio processor or preamp. Multiple audio processors used in LCD TV’s create audible pops as their power supply collapses. If the TAA2008 is still active (mute pin is low), then these audible pops will be am plified and output to the speakers. To eliminate this problem, simply activate the mute before the power supply collapses. The delay going into mute is approximately 1us, as compared to several hundred milliseconds on the previous Tripath IC’s such as TA2024B. Sleep Pin The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1MΩ recommended) to VDD. To disable SLEEP mode, the sleep pin should be grounded. Protection Circuits The TAA2008 is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI-

Tripath Technology, Inc. - Technical Information 12 TAA2008 –KLi/1.0/05.06 STATED, and will float to 1/2 of VDD. The FAULT pin can be connected directly to MUTE to automatically recover from an overcurrent condition. Over-temperature Protection An over-temperature fault occurs if the junction temperature of the part exceeds approximately 155°C. The thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically clear when the junction temperature drops below 110°C. Over-current Protection An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition. Overload The OVRLDB pin is a 5V logic output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVRLDB signal can be used to control a distortion indicator light or LED through a simple buffer circuit, as the OVRLDB cannot drive an LED directly. Fault Pin The FAULT pin is a 5V logic output that indicates various fault conditions within the device. These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155°C. All faults except overcurrent automatically reset upon removal of the condition. The FAULT output is capable of directly driving an LED through a series 2kΩ resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an over-current condition. Output Voltage Offset The DC offset voltages that appear at the speaker terminals of a TAA2008 amplifier are typically small and for most applications no DC offset correction is necessary. The TAA2008 is 100% tested to ensure that the differential output DC offset voltage is less than +/-150mV. However this DC offset can cause a small turn on and turn off pop, depending on the offset value for that specific IC. Every TAA2008 IC will have a different offset voltage for each channel. If the output offset is deemed unacceptable from a turn on/off pop standpoint, there are three recommended methods for correcting it. These methods of trimming the offset voltage are optional and for most cases the additional circuitry is not needed. 1) A potentiometer can be used at the input of the TAA2008 as shown in the figure below. By changing the input bias voltage the output DC offset voltage can be trimmed. Two separate potentiometers must be used to trim both channels.

Tripath Technology, Inc. - Technical Information 13 TAA2008 –KLi/1.0/05.06 TAA2008 OAOUT1 INV1 CI 2.2uF 30+ OAOUT2 INV2 CI 2.2uF RF 20KΩRI 20KΩ ROFA 10KΩ Offset Trim Potentiometer V5A (pin 28) ROFB 1MΩ COF 0.1uF ROFA 10KΩ V5A (pin 28) ROFB 1MΩ COF 0.1uF RF 20KΩRI 20KΩ Offset Trim Potentiometer 2) In cases where manually trimming potentiomete rs is not possible, resistors can be used in place of potentiometers. Since each TAA2008 has different offset voltage, the output offset voltage will need to be measured for both channel 1 and channel 2 and then resistors will have to be added on the PC board to trim the offset. Below is a lookup table for resistor values for corresponding offset voltages. Both Rx and Ry values should be 1% tolerance resistors. Please refer to the EB-TAA2008 document for more information on this manual trim method using resistors. TAA2008 OAOUT1 INV1 CI 2.2uF 30+ OAOUT2 INV2 CI 2.2uF RF 20KΩRI 20KΩ ROFB 1MΩ RX1 V5A (pin 28) ROFB 1MΩ RY1 RF 20KΩRI 20KΩ RX2 V5A (pin 28) RY2

Tripath Technology, Inc. - Technical Information 14 TAA2008 –KLi/1.0/05.06 OFFSET Ry Rx (1%) 150mV 20kΩ 13.3k Ω 140mV 20kΩ 13.7k Ω 130mV 20kΩ 14.3k Ω 120mV 20kΩ 14.7k Ω 110mV 20kΩ 15.4k Ω 100mV 20kΩ 15.8k Ω 90mV 20kΩ 16.2k Ω 80mV 20kΩ 16.9k Ω 70mV 20kΩ 17.4k Ω 60mV 20kΩ 17.8k Ω 50mV 20kΩ 18.7k Ω 40mV 20kΩ 19.1k Ω 30mV 20kΩ 19.6k Ω 20mV 20kΩ 20.5k Ω 10mV 20kΩ 21k Ω 0mV 20kΩ 21.5k Ω -10mV 20kΩ 22.6k Ω -20mV 20kΩ 23.2k Ω -30mV 20kΩ 24.3k Ω -40mV 20kΩ 24.9k Ω -50mV 20kΩ 25.5k Ω -60mV 20kΩ 26.7k Ω -70mV 20kΩ 27.4k Ω -80mV 20kΩ 28.0k Ω -90mV 20kΩ 29.4k Ω -100mV 20kΩ 30.1k Ω -110mV 20kΩ 31.6k Ω -120mV 20kΩ 32.4k Ω -130mV 20kΩ 33.2k Ω -140mV 20kΩ 34.8k Ω -150mV 20kΩ 35.7k Ω 3) A DC servo using a dual op amp can also be us ed to automatically null any offset voltage. This DC servo will only eliminate the turn off pop since the RC time constant of the DC servo is very slow. Please contact Tripath sales for additional information on the DC servo circuit. Power Dissipation Derating The TAA2008, as a result of high efficiency and good package thermal characteristics, can operate at elevated ambient temperatures without having to derate the output power, assuming 8 ohm output loads or higher. This in stark contra st to many other “compet itive” solutions from other semiconductor vendors, many of which can only provide full power at ambient temperatures of 25 °C, or slightly higher, without ex ceeding a junction temperature of 150 °C. Lower die temperatures result in a more ro bust and reliable amplifier solution that can only be facilitated by a combination of high efficiency and good package thermal characteristics. The exposed pad must be soldered to the PC Board to increase the maximum power dissipation capability of the TAA2008 package. Soldering will minimize the likelihood of an over- temperature fault occurring during continuous heavy load conditions. There should be vias for connecting the exposed pad to the copper area on the printed circuit board.

Tripath Technology, Inc. - Technical Information 15 TAA2008 –KLi/1.0/05.06 Conducting initial testing or characterization without the exposed pad soldered to the printed circuit board will give erroneous case temperature measurements. The TAA2008 is an extremely robust device, so not soldering the device to t he printed circuit board, due to potential rework issues, should not be a concern. These devices do not fail unless the operating supply voltages maximums are exceeded, and/or an improper printed board design is utilized. The maximum device power dissipation, for a gi ven ambient temperature, can be calculated based on a 150°C maximum junction temperature, T JMAX, as given by the following equation: JA AJMAX DISS )TT(P θ where: PDISS = maximum power dissipation TJMAX = maximum junction temperature of TAA2008 TA = operating ambient temperature θJA = junction-to-ambient thermal resistance = 22°C/W when soldered to PCB From the above formula, the maximum power dissipation at an ambient temperature of 25°C is 5.68W, and at 70°C is 3.64W. The amount of power dissipation can easily be calculated given the output power and efficiency for that output level. The Typical Performance Characteristics section has a significant amount of efficiency and power dissipation data. The relation between PDISS, Output Power and Efficiency is given in the formula below. PowerOutput TotalEfficiency PowerOutput TotalPDISS −= The efficiency for the TAA2008 is 86% at 9 watts per channel. Thus, the power dissipation is: Watts2.9318W0.86 18WPDISS =−= Since 2.93 Watts is less than the maximum power dissipation of 3.64 Watts at 70°C, the TAA2008 is not thermally limited assuming maximum output power into 8 ohms loads. The resultant junction temperature, T J, can be calculated using the formula below: AJADISSJ TΘ * PT += The power dissipation at 9 watts per channel into 8 ohms is 2.93W, as calculated above. Assuming an ambient temperature of 40°C, this results in a junction temperature of 105°C. This junction temperature is much lower than “competitive” solutions at similar output power levels with 8 ohm loads, resulting in a more reliable amplifier design. A similar set of calculations can be done for a 16 ohm load. But since the efficiency is higher and the output power is lower for a 16 ohm load, as opposed to an 8 ohm load, the power dissipation will be smaller. Since the TAA2008 is not thermally limited into 8 ohm loads, it will not be thermal limited into 16 ohm loads. Performance Measurements of the TAA2008 The TAA2008 operates by generating a high frequency switching signal based on the audio input. This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an

Tripath Technology, Inc. - Technical Information 16 TAA2008 –KLi/1.0/05.06 amplified version of the audio input. The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components. The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifiers switching pattern will degrade the measurement. One feature of the TAA2008 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements. Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TAA2008 Evaluation Board uses the Test/Application Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.

Tripath Technology, Inc. - Technical Information 17 TAA2008 –KLi/1.0/05.06

PACKAGE INFORMATION

32 PIN QFN - 8MM x 8MM X 1MM

Tripath Technology, Inc. - Technical Information 18 TAA2008 –KLi/1.0/05.06 Tripath Technology Inc. reserves the right to make c hanges without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. Tripath and Digital Power Processing are trademar ks of Tripath Technology Inc. Other trademarks referenced in this document are owned by their respective companies TRIPATH’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEM S WITHOUT THE EXPRESS WR ITTEN CONSENT OF THE PRESIDENT OF TRIPATH TECHNOLOGY INC. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in th is labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the lif e support device or system, or to affect its safety or effectiveness. Contact Information TRIPATH TECHNOLOGY, INC

2560 Orchard Parkway, San Jose, CA 95131

408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ www.tripath.com/cont_s.htm For more Technical Information, please visit us @ www.tripath.com/data.htm

Summary

STEREO 9W (8?? CLASS-T??DIGITAL AUDIO AMPLIFIER USING DIGITAL POWER PROCESSING??TECHNOLOGY

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