STN18T20 STANSON | Alldatasheet
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N Channel Enhancement Mode MOSFET 18.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com Copyright © 2008, Stanson Corp. STN18T20 2012. V1 DESCRIPTION STN18T20 is the N-Channel logic enhancement mode power field effect transistor which is produced using high cell density, DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application such as power management and other battery powered circuits where high-side switching. PIN CONFIGURATION TO-252 PART MARKING Y: Year Code A: Date Code Q: Process Code FEATURE l 200V/12A, RDS(ON) = 170mΩ(Typ.) @VGS = 10V l Super high density cell design for extremely low RDS(ON) l Exceptional on-resistance and maximum DC current capability l TO-252 package design
N Channel Enhancement Mode MOSFET 18.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com Copyright © 2008, Stanson Corp. STN18T20 2012. V1 ABSOULTE MAXIMUM RATINGS (Ta = 25℃ Unless otherwise noted ) Parameter Symbol Typical Unit Drain-Source Voltage VDSS 200 V Gate-Source Voltage VGSS ±30 V Continuous Drain Current (TJ=150℃) TA=25℃ TA=100℃ ID 18 11.4 A Pulsed Drain Current IDM 36 A Avalanche Current IAS 17 mJ Power Dissipation TA=25℃ PD 112 W Operation Junction Temperature TJ 150 ℃ Storgae Temperature Range TSTG -55/150 ℃ Thermal Resistance-Junction to Ambient RθJA 80 ℃/W
N Channel Enhancement Mode MOSFET 18.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com Copyright © 2008, Stanson Corp. STN18T20 2012. V1 9.4 19 nS 23 41 Turn-Off Time td(off) tf 18.4 37 15.6 21.8
N Channel Enhancement Mode MOSFET 18.0A STANSON TECHNOLOGY 120 Bentley Square, Mountain View, Ca 94040 USA www.stansontech.com Copyright © 2008, Stanson Corp. STN18T20 2012. V1 PACKAGE OUTLINE SOP-8P