SRM20100LC SII | Alldatasheet

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SEIKO EPSON CORP. PF463-04 CMOS 1M-BIT STATIC RAM @Low Supply Current @Access Time 70ns/85ns/100ns @131,072 Words X8-Bit Asynchronous WIDESCRIPTION The SRM20100LC7oesi10 is an 131,072 wordsx 8-bit asynchronous, static, random access memory ona monolithic CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage with back-up batteries. The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the input and output ports are TTL compatible and the 3-state output allows easy expansion of memory capacity.

FEATURES

@Fast Access time-:++++-++-+++++-++-- SRM20100LC70 7Ons (Max)* | (o1P/soP6) SRM20100LCes 85ns (Max) Neo BDV | SRM20100LCio 100s (Max) mode = Spwe @Low supply currents\\-1-117--7---standby :2uA (Typ) sede 3 spas operation: 15mA/MHz (Typ) | ‘a de § ssban @Completely static :++++++++++++-++++++-No clock required | fa fo 3 Baie @Single power supply ++-++++++++-+++ -SVE10% ao ge 23 vos @TTL compatible inputs and outputs verqis — isBves ss pu @3-state output with wired-OR capability vos @Non-volatile storage with back-up batteries [aso @Package*--*-"" SRM20100LCrovesno0 -—DIP-32pin (plastic) | and Ths SRM20100LM7ovasi0. —-»« SOP6-32pin (plastic) | BO SB SRM20100LTM7ova5/10 TSOP-32pin (plastic) * weds ed SRM20100LRM7ovesi0 + TSOPR-32pin (plastic)* | Kisq> depos . reds SRMZO100LTM Eves, IBLOCK DIAGRAM +: Under development | sicui spice Mogi Zipior ; ——— args Sob A0 ne die spat | 0 Bed SBR | | Al of | al a2 [OO —O—O—H 8 ‘a . | crsopR) ] > | | a5 Ol 5 9 3 |512 Memory Cell Array | ac Gis Thas | a6 of = 3 4 gis ipa | AT 4 o 512x256x8 ss a BPA | 8 ot 3 * augur zBioe >| 8 q 2B) alodt § Atedhi0 Zpivos | All a 2 ne ge ‘SRM20100LRM_ 24D Vis a veo ds Bios | Ag S 256%8 ceeds irpiee | angi O BBs | | 4 J | asid48 3 | Sleek 8 IIPIN DESCRIPTION | cs20 Bas es | AOtoAI6 Address Input | alle = | We Write Enable | of a eg W/O Butter | OE Output Enable WEO 8S 5} | CSi, cs2 Chip Select 101 to8 Data V0 | 1/01 1/02 1/03 1/08 1/08 1/06 1/07 1/08 | Vss Power Supply( OV) NC No connection 0-71

I MIABSOLUTE MAXIMUM RATINGS (Vss=0V) Input voltage” [vi Input/Output voltage” | Vio Pp 7.0 Storage temperature Tste | =65 to 150 c * Vi, Vuo (Min)= —3.0V (Pulse width is 50ns) IIDC RECOMMENDED OPERATING CONDITIONS (Vss=0V, Ta=0 to 70°C) Voo = [45 7 5.0 55] UV Supply voltage Vs cE — ee ee ee ee a 77 Input voltage Vin = [22 73.5 | Voo+0.3 Vv +f pulse width is less than 50ns, it is —3.0V SDC Eluviical Chorssioristics res (Voo=5V+10%, Vss=0V, Ta=0 to 70°C) [Taoutieakage een |---| 1] oak | loos__|__CS1=Vu or CS2=Vu_|— [1.0/3.0] —[1-0]8.0]—]1.0)8-0) ma | or CS2S0.2V | ] T Preewearet | tS cue =l9lm(=lem ale) | foe wsyoee | ow |Tenba = lwlmlm mlm oe | ee ee Output leakage lo | or WE=Vi. or OE=Vin —}1) BA Vio=0 to Voo | [ Fish Tevet output votase [Vor [tow = 1.0mA (4) —|— [a = — |=) | [Low tevel output vottage [Vo tu =2.tmA || — [0.4] — | Joa} —|—fo.4) | * Typcal values are measured at Ta=25°C and Voo=5.0V @Terminal Capacitance (f=1MHz,_Ta=25°C) [Parameter | Symbol_[ Conditions | Min | Typ | Max [Unit | Vi=0V [vo Capacitance | Cy. Tort | Tt BAC Flectical Characteristics (Voo=8V#10%, Vss=0V, Ta=0 to 70°C) | Read cycle time | tro [70 | = [a5 | — Tif =] ns | | Chip select 2 access time |" tacse | [= [70 | =| 95 | =| to0[ ns | | Output enable access time | toe | [= 40 [= [4s [=] 50] ns | 2 [io] =] io [= [io [=] ns Output enable output set ime | to _| Te | [ouputhoidtime | tw | dO ns 0-72

  • SN TTD EBLE TI TT RITE A TT write Cycle (Voo=5V+10%, Vss=0V, Ta=0to 70°C) | ‘SRM20100LCra| SRM20100L.C9s | SRM20100L Cio) Pp. t | 7 iti - arameter ‘Symbol Conditions [Min [Max/ Min | Max | Min [Max | Unit Co [=[m[=fo[=[ =| Cet — [mf = [f= [os | 6 fo f=fe =f [=p (s[=fe [=f [= ps | tw | Cof=fol=fo [=f | Input data setup time tow | fo[=[s[-fol=] os | tw fof=fe[=fo =f] TE Gut tong Deere *1 Test Conditions +3v #2. Test Conditions 4sv 2. t=tf=5ns 1BkKQ 2. t=tf=5ns 18k2. 3. Input and output timing reference 3. Input timing reference levels: 1.5V yo levels : 1.5V 4. Output timing reference levels : a soon 4. Output load C= 100pF ce S908 £200m\\ (the level displaced from T T stable output voltage level) = = = = 5. Output load =, =SpF C.=SpF (Includes Jig Capacitance) Co 1005 creates se Capactarce) @Timing Chart O Read Cycle Write Cycle (1) (CS1 Control) tee a AooRess ___ Tie i = ‘om a WrPArT7 a 7 eS « ITE = SS sz ee —" at _ = We LZ we = SXXXKNTK ¢ZTTTITITL. Son) — eel out ESD eat Dout a 04, Sn. .8, tout tow OWrite Cycle (2) (CS2 Control) © Write Cycle (3) (WE Control) ‘ADDRESS, A ADDRESS, ee 7 mm a Tae foe wi Wik 477LTTTTIL ts | cs se L222 SANNNNRAANN toww— | --——twe. We We BANS: = tow k-tow—-ton 1 ‘tow ton: Note: 1. During read cycle time, WE is to be "H” level. __ —_ 2. During write cycle time that is controlled by CSI or CS2, Output Buffer is in high impedance state whether OE level 3. During write cycle time that is controlled by WE, Output Buffer is high impedance state if OE is "H" level. 4. When I/O terminals are output mode, be careful that do not give the opposite signals to the I/O terminals. 0-73

a ISDATA RETENTION CHARACTERISTIC WITH LOW VOLTAGE POWER SUPPLY (Ta=0t070°C) Symbol | Conditions | Min Typ Max | Unit fossoacranstowine | toe | || | +1 Ta=25°C *2_ trc=Read cycle time Data retention timing (C31 Control) Data retention timing (CS2 Control) Data hold mode —+ Voo a5v Data hold mode Voo 45V Vooezz0v 45¥ Voorz20v 45¥ ‘teor: = tr: cor tr a RS 12 V00- 0.2V AS csi 22v = aay cs2 o4v cs2.s0.2v av FUNCTIONS @Truth Table [er [ee [©] We oma [moe me L | H L | H | Output data Read Ippo @Reading data Data is able to be read when the address is setted while holding CS1="L", CS2="H", OE="L" and WE= “H”. Since Data I/O terminals are in high impedance state when OE="H’, the data bus line can be used for any other objective, then access time apparently is able to be cut down. @Writing data There are the following four ways of writing data into the memory. (1) Hold CS2="H", WE="L" set addresses and give "L” pulse to CS1. (2) Hold CSi="L’, WE="L’, set addresses and give "H" pulse to CS2. (3) Hold CSi="L’, CS2="H! set addresses and give "L” pulse to WE. (4) After setting addresses, give "L” pulse to CSi, WE and give "H” pulse to CS2. Anyway, data on the Data I/O terminals are latched up into the SRM20100LC7ovas/o at the end of the period that CS1, WE are "L” level, and CS2 is "H” level. As Data I/O terminals are in high impedance state when any of CS1, OE="H", or CS2="L", the contention on the data bus can be avoided. 0-74

@Standby mode When CS1 is "H” or CS2 is "L" level, the SRM20100L Crovesiio is in the standby mode which has retaning date operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any “H" or "L". When CS and CS2 level are in the range over Voo-0.2V, or CS2 level is in the range under 0.2V, in the SRM20100LC7ovas/10 there is almost no current flow except through the high resistance parts of the memory. IPACKAGE DIMENSIONS Plastic DIP-32pin 1.873max | (ease Po ooooponooonoohl las ee | alia isis y oo 88 ‘ Le Lois (o2s°88 gues, ae | See unit: inch | Plastic SOP6-32pin*! azine Eroy TT = unnononeiarnontt—4 | i | wo TOUT wT i— hn 08s gg ‘eat ~ unit : inch (mm) +1 SRM20100LMrorssno has the same characteristics as SRM20100LC7oresn0. 0-75

Plastic TSOP-32pin*! expe (Under development) a — eo bs a Ne 2 Ee 42) af *1 SRM20100LTMroves/00 has the same characteristics as SRM20100LCzovasi0. Plastic TSOPR-32pin*? ogee (Under development) rps see | *2 SRM20100LRMrovasi00 has the same characteristics as SRM20100LCroves0. CHARACTERISTICS CURVES Normalized lova—Ta Normalized Ippa—Frequency Normalized lopa—Voo Lg SS == =F area SSS SJ ; os } ua | 4 a fre 7 oot Ud ll ot LA) ar Od Sd os JAAR TT [ [| write la 7 Ll ZA rem] | od§ FIT TT | no oe) ee Aa 0.9 = Coo) oe ZT | er ol 4) OT |) ot 06 oo 2 4 6 8 10l2Zisileis2 | 8 Gs 3.0 5S ° 26 70 Frequency (MHz) | Voo (Vv) | Ta ('C) Vtre, 1/twe | 0-76

| | | 5.000 = 5.0 EE} 4 fe a a tooo} st EE ee yA Od ut fT | fp Yo | ? fn rot | [Let | ty i SSS ro] fT i] | eH ERE aA os |_| IN} ——— a a fr, | ort | | IN] |] oa oot | | | NJ To 25 70 0230 40 5.0 60 OTT 20 30 40 50 Ta (‘C) | Voo (V) Vou (V) t t - - Normalized thos: | Normalized taest Normalized lo.—Vot 13 pp es eee 2.0 pg i [[ | erase] zo | |} faces A re OD ra) vet | ag TT vp | TT ZT yoL | he ff tt vol ee | oof PR TT) Be pe | ENN eee | So | A ossl-b 095 {I os Z| | ool tr) gw-P ot PZ j eet t tT | oot | TT | oop TAP PT opL Lr | gg oY tt tt 8 oO 25 70 45 50 35 0 02 04 06 O08 | Ta (0) Voo (Vv) Vo W) tacc Normalized tacs1 tacs2z—C ee ee | a a A A A Ys} [AA Ta=25'c BT Te0= 5.09 a A BH a + 7 Se | a a a | a | a a a a a 100 200 300 400 Cu (pF) 0-77