S5725

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www.sii-ic.com HIGH-SPEED BIPOLAR HALL EFFECT LATCH © SII Semiconductor Corporation, 2011-2015 Rev.2.5_01 The S-5725 Series, developed by CMOS technology, is a high-accuracy Hall IC that operates with a high-sensitivity, a high- speed detection and low current consumption. The output voltage changes when t he S-5725 Series detects the intensity level of magnetic flux density and a polarity change. Using the S-5725 Series with a magnet makes it possible to detect the rotation status in various devices. High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A packages. Due to its high-accuracy magnetic char acteristics, the S-5725 Series can make operation's dispersion in the system combined with magnet smaller. Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII Semiconductor Corporation is indispensable.  Features

• Pole detection: Bipolar latch
• Detection logic for magnetism*1: V OUT = "L" at S pole detection V OUT = "H" at S pole detection
• Output form*1: Nch open-drain output, CMOS output
• Magnetic sensitivity*1: B OP = 0.8 mT typ. B OP = 1.8 mT typ. B OP = 3.0 mT typ. B OP = 7.0 mT typ.
• Operating cycle (current consumption)*1: t CYCLE = 50 μs (IDD = 1400.0 μA) typ. t CYCLE = 1.25 ms (IDD = 60.0 μA) typ. t CYCLE = 6.05 ms (IDD = 13.0 μA) typ.
• Power supply voltage range: V DD = 2.7 V to 5.5 V
• Operation temperature range: Ta = −40°C to +85°C
• Built-in power-down circuit: Extends battery life (only SNT-4A)
• Lead-free (Sn 100%), halogen-free *1. The option can be selected.  Applications
• Plaything, portable game
• Home appliance
• Housing equipment
• Industrial equipment  Packages
• SOT-23-3
• SNT-4A

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01  Product Name Structure 1. Product name S-5725 x x B x x - xxxx U Environmental code U: Lead-free (Sn 100%), halogen-free Package name (abbreviation) and packing specifications M3T1: SOT-23-3, Tape I4T1: SNT-4A, Tape Magnetic sensitivity 9: B OP = 0.8 mT typ. 0: B OP = 1.8 mT typ. 1: B OP = 3.0 mT typ. 3: B OP = 7.0 mT typ. Detection logic for magnetism L: V OUT = "L" at S pole detection H: V OUT = "H" at S pole detection Pole detection B: Bipolar latch Output form N: Nch open-drain output C: CMOS output Operating cycle C: t CYCLE = 6.05 ms typ. (Without power-down function) D: t CYCLE = 1.25 ms typ. (Without power-down function) E: t CYCLE = 50 μs typ. (Without power-down function) H: t CYCLE = 6.05 ms typ. (With power-down function, SNT-4A) I: t CYCLE = 1.25 ms typ. (With power-down function, SNT-4A) J: t CYCLE = 50 μs typ. (With power-down function, SNT-4A) *1. Refer to the tape drawing. 2. Packages Table 1 Package Drawing Codes Package Name Dimension Tape Reel Land SOT-23-3 MP003-C-P-SD MP003-C-C-SD MP003-Z-R-SD − SNT-4A PF004-A-P-SD PF004-A-C-SD PF004-A-R-SD PF004-A-L-SD

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series 3. Product name list 3. 1 SOT-23-3 3. 1. 1 Nch open-drain output product Table 2 Product Name Operating Cycle (tCYCLE) Power-down Function Output Form Pole Detection Detection Logic for Magnetism Magnetic Sensitivity (BOP) S-5725CNBL9-M3T1U 6.05 ms typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 0.8 mT typ. S-5725CNBL0-M3T1U 6.05 ms typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 1.8 mT typ. S-5725CNBL1-M3T1U 6.05 ms typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725DNBL1-M3T1U 1.25 ms typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725ENBL9-M3T1U 50 μs typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 0.8 mT typ. S-5725ENBL0-M3T1U 50 μs typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 1.8 mT typ. S-5725ENBL1-M3T1U 50 μs typ. Unavailable Nch open-drain output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725ENBH1-M3T1U 50 μs typ. Unavailable Nch open-drain output Bipolar latch VOUT = "H" at S pole detection 3.0 mT typ. Remark Please contact our sales office for products other than the above. 3. 1. 2 CMOS output product Table 3 Product Name Operating Cycle CYCLE) Power-down Function Output Form Pole Detection Detection Logic for Magnetism Magnetic Sensitivity (BOP) S-5725CCBL9-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 0.8 mT typ. S-5725CCBL0-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 1.8 mT typ. S-5725CCBL1-M3T1U 6.05 ms typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725DCBL1-M3T1U 1.25 ms typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725ECBL9-M3T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 0.8 mT typ. S-5725ECBL0-M3T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 1.8 mT typ. S-5725ECBL1-M3T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 3.0 mT typ. S-5725ECBH0-M3T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725ECBH1-M3T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "H" at S pole detection 3.0 mT typ. Remark Please contact our sales office for products other than the above.

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01 3. 2 SNT-4A 3. 2. 1 Nch open-drain output product Table 4 Product Name Operating Cycle CYCLE) Power-down Function Output Form Pole Detection Detection Logic for Magnetism Magnetic Sensitivity (BOP) S-5725ENBH3-I4T1U 50 μs typ. Unavailable Nch open-drain output Bipolar latch VOUT = "H" at S pole detection 7.0 mT typ. S-5725HNBH0-I4T1U 6.05 ms typ. Available Nch open-drain output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725INBH0-I4T1U 1.25 ms typ. Available Nch open-drain output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725JNBH0-I4T1U 50 μs typ. Available Nch open-drain output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. Remark Please contact our sales office for products other than the above. 3. 2. 2 CMOS output product Table 5 Product Name Operating Cycle CYCLE) Power-down Function Output Form Pole Detection Detection Logic for Magnetism Magnetic Sensitivity (BOP) S-5725ECBL9-I4T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 0.8 mT typ. S-5725ECBL0-I4T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "L" at S pole detection 1.8 mT typ. S-5725ECBH0-I4T1U 50 μs typ. Unavailable CMOS output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725HCBH0-I4T1U 6.05 ms typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725HCBH1-I4T1U 6.05 ms typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 3.0 mT typ. S-5725ICBH0-I4T1U 1.25 ms typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725ICBH1-I4T1U 1.25 ms typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 3.0 mT typ. S-5725JCBH0-I4T1U 50 μs typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 1.8 mT typ. S-5725JCBH1-I4T1U 50 μs typ. Available CMOS output Bipolar latch VOUT = "H" at S pole detection 3.0 mT typ. Remark Please contact our sales office for products other than the above.

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series  Pin Configurations 1. SOT-23-3 Top view Figure 5 Table 6 Pin No. Symbol Pin Description

1 VSS GND pin

2 VDD Power supply pin

3 OUT Output pin

1. SNT-4A Top view Figure 6 Table 7 Pin No. Symbol Description

1 VDD Power supply pin

2 VSS GND pin

"H": Enables operation "L": Power-down

4 OUT Output pin

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01  Absolute Maximum Ratings Table 8 (Ta = +25°C unless otherwise specified) Item Symbol Absolute Maximum Rating Unit Power supply voltage V DD VSS − 0.3 to VSS + 7.0 V Input voltage V CE VSS − 0.3 to VDD + 0.3 V Output current I OUT ±2.0 mA Output voltage Nch open-drain output product VOUT VSS − 0.3 to VSS + 7.0 V CMOS output product VSS − 0.3 to VDD + 0.3 V Power dissipation SOT-23-3 PD 430*1 mW SNT-4A 300*1 mW Operation ambient temperature T opr −40 to +85 °C Storage temperature T stg −40 to +125 °C *1. When mounted on board [Mounted board] (1) Board size: 114.3 mm × 76.2 mm × t1.6 mm (2) Name: JEDEC STANDARD51-7 Caution The absolute maximum ra tings are rated values exceeding whic h the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] Ambient Temperature (Ta) [°C] 0 50 100 150 400 600 200 SNT-4A SOT-23-3 Figure 7 Power Dissipation of Package (When Mounted on Board)

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series  Electrical Characteristics 1. Product without power-down function 1. 1 S-5725CxBxx Table 9 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 13.0 20.0 μA 1 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 0.05 − ms − Sleep mode time t SL − − 6.00 − ms − Operating cycle t CYCLE tAW + t SL − 6.05 12.00 ms − 1. 2 S-5725DxBxx Table 10 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 60.0 90.0 μA 1 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 0.05 − ms − Sleep mode time t SL − − 1.20 − ms − Operating cycle t CYCLE tAW + t SL − 1.25 2.50 ms −

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01 1. 3 S-5725ExBxx Table 11 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 1400.0 2000.0 μA 1 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 50 − μs − Sleep mode time t SL − − 0 − μs − Operating cycle t CYCLE t AW + t SL − 50 100 μs −

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series 2. Product with power-down function (SNT-4A) 2. 1 S-5725HxBxx Table 12 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 13.0 20.0 μA 1 Current consumption during power-down IDD2 V CE = V SS − − 1 μA 6 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 0.05 − ms − Sleep mode time t SL − − 6.00 − ms − Operating cycle t CYCLE t AW + t SL − 6.05 12.00 ms − Enabling pin input voltage "L" V CEL − − − VDD ×

0.3 V −

Enabling pin input voltage "H" V CEH − VDD × 0.7 − − V − Enabling pin input current "L" I CEL V DD = 5.0 V, VCE = 0 V −1 − 1 μA 7 Enabling pin input current "H" I CEH V DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8 Power-down transition time t OFF − − − 100 μs − Enable transition time t ON − − − 100 μs − Output logic update time after inputting "H" to enabling pin tOE − − − 200 μs −

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01 2. 2 S-5725IxBxx Table 13 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 60.0 90.0 μA 1 Current consumption during power-down IDD2 V CE = VSS − − 1 μA 6 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 0.05 − ms − Sleep mode time t SL − − 1.20 − ms − Operating cycle t CYCLE t AW + tSL − 1.25 2.50 ms − Enabling pin input voltage "L" V CEL − − − VDD × Enabling pin input voltage "H" V CEH − VDD × 0.7 − − V − Enabling pin input current "L" I CEL V DD = 5.0 V, VCE = 0 V −1 − 1 μA 7 Enabling pin input current "H" I CEH V DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8 Power-down transition time t OFF − − − 100 μs − Enable transition time t ON − − − 100 μs − Output logic update time after inputting "H" to enabling pin tOE − − − 200 μs −

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series 2. 3 S-5725JxBxx Table 14 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Power supply voltage V DD − 2.7 5.0 5.5 V − Current consumption I DD Average value − 1400.0 2000.0 μA 1 Current consumption during power-down IDD2 V CE = VSS − − 1 μA 6 Output voltage V OUT Nch open-drain output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 CMOS output product Output transistor Nch, IOUT = 2 mA − − 0.4 V 2 Output transistor Pch, IOUT = −2 mA VDD − 0.4 − − V 3 Leakage current I LEAK Nch open-drain output product Output transistor Nch, VOUT = 5.5 V − − 1 μA 4 Awake mode time t AW − − 50 − μs − Sleep mode time t SL − − 0 − μs − Operating cycle t CYCLE t AW + tSL − 50 100 μs − Enabling pin input voltage "L" V CEL − − − VDD × Enabling pin input voltage "H" V CEH − VDD × 0.7 − − V − Enabling pin input current "L" I CEL V DD = 5.0 V, VCE = 0 V −1 − 1 μA 7 Enabling pin input current "H" I CEH V DD = 5.0 V, VCE = 5.0 V −1 − 1 μA 8 Power-down transition time t OFF − − − 100 μs − Enable transition time t ON − − − 100 μs − Output logic update time after inputting "H" to enabling pin tOE − − − 200 μs −

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01  Magnetic Characteristics 1. Product with BOP = 0.8 mT typ. Table 15 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Operation point*1 S pole B OP − 0.1 0.8 1.5 mT 5 Release point*2 N pole B RP − −1.5 −0.8 −0.1 mT 5 Hysteresis width*3 BHYS B HYS = BOP − BRP − 1.6 − mT 5 2. Product with BOP = 1.8 mT typ. Table 16 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Operation point*1 S pole B OP − 0.9 1.8 2.7 mT 5 Release point*2 N pole B RP − −2.7 −1.8 −0.9 mT 5 Hysteresis width*3 BHYS B HYS = BOP − BRP − 3.6 − mT 5 3. Product with BOP = 3.0 mT typ. Table 17 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Operation point*1 S pole B OP − 1.4 3.0 4.0 mT 5 Release point*2 N pole B RP − −4.0 −3.0 −1.4 mT 5 Hysteresis width*3 BHYS B HYS = BOP − BRP − 6.0 − mT 5 4. Product with BOP = 7.0 mT typ. Table 18 (Ta = +25°C, VDD = 5.0 V, VSS = 0 V unless otherwise specified) Item Symbol Condition Min. Typ. Max. Unit Test Circuit Operation point*1 S pole B OP − 5.0 7.0 8.5 mT 5 Release point*2 N pole B RP − −8.5 −7.0 −5.0 mT 5 Hysteresis width*3 BHYS B HYS = BOP − BRP − 14.0 − mT 5 *1. B OP: Operation point BOP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied to the S-5725 Series by the magnet (S pole) is increased (by moving the magnet closer). VOUT retains the status until a magnetic flux density of the N pole higher than BRP is applied. *2. B RP: Release point BRP is the value of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux density applied to the S-5725 Series by the magnet (N pole) is increased (by moving the magnet closer). VOUT retains the status until a magnetic flux density of the S pole higher than BOP is applied. *3. B HYS: Hysteresis width BHYS is the difference between BOP and BRP. Remark The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series VDD VSS OUT CE A S-5725 Series VDD VSS OUT CE A S-5725 Series Figure 19 Test Circuit 7 Figure 20 Test Circuit 8

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series  Precautions

• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feed- through current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes.
• Do not apply an electrostatic discharge to this IC that ex ceeds the performance ratings of the built-in electrostatic protection circuit.
• Large stress on this IC may affect on the magnetic charac teristics. Avoid large stress which is caused by bend and distortion during mounting the IC on a board or handle after mounting.
• SII Semiconductor Corporation claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party.

HIGH-SPEED BIPOLAR HALL EFFECT LATCH S-5725 Series Rev.2.5_01  Marking Specifications 1. SOT-23-3 Top view (1) (2) (3) (4) (1) to (3): Product code (Refer to Product name vs. Product code.) (4): Lot number Product name vs. Product code 1. 1 Nch open-drain output product Product Name Product Code (1) (2) (3) S-5725CNBL9-M3T1U X 9 R S-5725CNBL0-M3T1U X 9 S S-5725CNBL1-M3T1U X 9 J S-5725DNBL1-M3T1U X 9 K S-5725ENBL9-M3T1U X 9 V S-5725ENBL0-M3T1U X 9 A S-5725ENBL1-M3T1U X 9 B S-5725ENBH1-M3T1U X 9 L 1. 2 CMOS output product Product Name Product Code (1) (2) (3) S-5725CCBL9-M3T1U X 9 P S-5725CCBL0-M3T1U X 9 Q S-5725CCBL1-M3T1U X 9 T S-5725DCBL1-M3T1U X 9 U S-5725ECBL9-M3T1U X 9 W S-5725ECBL0-M3T1U X 9 X S-5725ECBL1-M3T1U X 9 C S-5725ECBH0-M3T1U X 9 Z S-5725ECBH1-M3T1U X 9 Y

HIGH-SPEED BIPOLAR HALL EFFECT LATCH Rev.2.5_01 S-5725 Series 2. SNT-4A Top view (1) (2) (3) (1) to (3): Product code (Refer to Product name vs. Product code.) Product name vs. Product code 2. 1 Nch open-drain output product Product Name Product Code (1) (2) (3) S-5725ENBH3-I4T1U X 8 A S-5725HNBH0-I4T1U X 9 D S-5725INBH0-I4T1U X 9 F S-5725JNBH0-I4T1U X 9 H 2. 2 CMOS output product Product Name Product Code (1) (2) (3) S-5725ECBL9-I4T1U X 9 W S-5725ECBL0-I4T1U X 9 X S-5725ECBH0-I4T1U X 9 Z S-5725HCBH0-I4T1U X 9 E S-5725HCBH1-I4T1U X 9 M S-5725ICBH0-I4T1U X 9 G S-5725ICBH1-I4T1U X 9 N S-5725JCBH0-I4T1U X 9 I S-5725JCBH1-I4T1U X 9 O

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54 /X4E/X6F/X2E/X20/X4D/X50/X30/X30/X33/X2D/X43/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X4D/X50/X30/X30/X33/X2D/X43/X2D/X50/X2D/X53/X44/X2D/X31/X2E/X31 /X53/X4F/X54/X32/X33/X33/X2D/X43/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X32/X2E/X39/XB1/X30/X2E/X32 /X30/X2E/X39/X35/XB1/X30/X2E/X31 /X31/X2E/X39/XB1/X30/X2E/X32 /X2B/X30/X2E/X31 /X20/X2D/X30/X2E/X30/X36/X30/X2E/X31/X36 /X30/X2E/X34/XB1/X30/X2E/X31 /X31 /X32 /X33 /X6D/X6D

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/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54 /X51/X54/X59/X2E/X33/X2C/X30/X30/X30 /X4E/X6F/X2E/X20/X4D/X50/X30/X30/X33/X2D/X5A/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X4D/X50/X30/X30/X33/X2D/X5A/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X53/X4F/X54/X32/X33/X33/X2D/X43/X2D/X52/X65/X65/X6C /XF8/X31/X33/XB1/X30/X2E/X32 /X31/X32/X2E/X35/X6D/X61/X78/X2E /X39/X2E/X32/XB1/X30/X2E/X35 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X6D/X6D

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54 /X31/X2E/X32/XB1/X30/X2E/X30/X34 /X30/X2E/X36/X35 /X30/X2E/X32/XB1/X30/X2E/X30/X35 /X6D/X6D /X53/X4E/X54/X2D/X34/X41/X2D/X41/X2D/X50/X4B/X47/X20/X44/X69/X6D/X65/X6E/X73/X69/X6F/X6E/X73 /X50/X46/X30/X30/X34/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X35/X2E/X30 /X4E/X6F/X2E/X20/X50/X46/X30/X30/X34/X2D/X41/X2D/X50/X2D/X53/X44/X2D/X35/X2E/X30 /X31 /X32 /X33/X34

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54/X6D/X6D /X50/X46/X30/X30/X34/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X53/X4E/X54/X2D/X34/X41/X2D/X41/X2D/X43/X61/X72/X72/X69/X65/X72/X20/X54/X61/X70/X65 /X46/X65/X65/X64/X20/X64/X69/X72/X65/X63/X74/X69/X6F/X6E /X34/X2E/X30/XB1/X30/X2E/X31/X32/X2E/X30/XB1/X30/X2E/X30/X35 /X34/X2E/X30/XB1/X30/X2E/X31 /XF8/X31/X2E/X35 /X2B/X30/X2E/X31 /X20/X2D/X30 /XF8/X30/X2E/X35 /X31/X2E/X34/X35/XB1/X30/X2E/X31 /X30/X2E/X36/X35/XB1/X30/X2E/X30/X35 /X30/X2E/X32/X35/XB1/X30/X2E/X30/X35 /X31/X32 /X33/X34 /X35/XB0 /X4E/X6F/X2E/X20/X50/X46/X30/X30/X34/X2D/X41/X2D/X43/X2D/X53/X44/X2D/X31/X2E/X30 /X2B/X30/X2E/X31 /X20/X2D/X30

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54 /X31/X32/X2E/X35/X6D/X61/X78/X2E /X39/X2E/X30/XB1/X30/X2E/X33 /XF8/X31/X33/XB1/X30/X2E/X32 /X28/X36/X30/XB0/X29 /X28/X36/X30/XB0/X29 /X51/X54/X59/X2E /X35/X2C/X30/X30/X30 /X4E/X6F/X2E/X20/X50/X46/X30/X30/X34/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X50/X46/X30/X30/X34/X2D/X41/X2D/X52/X2D/X53/X44/X2D/X31/X2E/X30 /X45/X6E/X6C/X61/X72/X67/X65/X64/X20/X64/X72/X61/X77/X69/X6E/X67/X20/X69/X6E/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X72/X61/X6C/X20/X70/X61/X72/X74 /X6D/X6D /X53/X4E/X54/X2D/X34/X41/X2D/X41/X2D/X52/X65/X65/X6C

/X53/X49/X49/X20/X53/X65/X6D/X69/X63/X6F/X6E/X64/X75/X63/X74/X6F/X72/X20/X43/X6F/X72/X70/X6F/X72/X61/X74/X69/X6F/X6E /X4E/X6F/X2E /X54/X49/X54/X4C/X45 /X41/X4E/X47/X4C/X45 /X55/X4E/X49/X54/X6D/X6D /X53/X4E/X54/X2D/X34/X41/X2D/X41 /X20/X20/X20/X20/X20/X20/X2D/X4C/X61/X6E/X64/X20/X52/X65/X63/X6F/X6D/X6D/X65/X6E/X64/X61/X74/X69/X6F/X6E /X50/X46/X30/X30/X34/X2D/X41/X2D/X4C/X2D/X53/X44/X2D/X34/X2E/X31 /X4E/X6F/X2E/X20/X50/X46/X30/X30/X34/X2D/X41/X2D/X4C/X2D/X53/X44/X2D/X34/X2E/X31 /X30/X2E/X33/X30/X2E/X33/X35 /X30/X2E/X35/X32 /X31/X2E/X31/X36 /X30/X2E/X35/X32 /X43/X61/X75/X74/X69/X6F/X6E /X31/X2E/X20/X44/X6F/X20/X6E/X6F/X74/X20/X64/X6F/X20/X73/X69/X6C/X6B/X73/X63/X72/X65/X65/X6E/X20/X70/X72/X69/X6E/X74/X69/X6E/X67/X20/X61/X6E/X64/X20/X73/X6F/X6C/X64/X65/X72/X20/X70/X72/X69/X6E/X74/X69/X6E/X67/X20/X75/X6E/X64/X65/X72/X20/X74/X68/X65/X20/X6D/X6F/X6C/X64/X20/X72/X65/X73/X69/X6E/X20/X6F/X66/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X2E /X32/X2E/X20/X54/X68/X65/X20/X74/X68/X69/X63/X6B/X6E/X65/X73/X73/X20/X6F/X66/X20/X74/X68/X65/X20/X73/X6F/X6C/X64/X65/X72/X20/X72/X65/X73/X69/X73/X74/X20/X6F/X6E/X20/X74/X68/X65/X20/X77/X69/X72/X65/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X75/X6E/X64/X65/X72/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X20/X73/X68/X6F/X75/X6C/X64/X20/X62/X65/X20/X30/X2E/X30/X33/X20/X6D/X6D /X6F/X72/X20/X6C/X65/X73/X73/X20/X66/X72/X6F/X6D/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X73/X75/X72/X66/X61/X63/X65/X2E /X33/X2E/X20/X4D/X61/X74/X63/X68/X20/X74/X68/X65/X20/X6D/X61/X73/X6B/X20/X61/X70/X65/X72/X74/X75/X72/X65/X20/X73/X69/X7A/X65/X20/X61/X6E/X64/X20/X61/X70/X65/X72/X74/X75/X72/X65/X20/X70/X6F/X73/X69/X74/X69/X6F/X6E/X20/X77/X69/X74/X68/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X2E /X34/X2E/X20/X52/X65/X66/X65/X72/X20/X74/X6F/X20/X22/X53/X4E/X54/X20/X50/X61/X63/X6B/X61/X67/X65/X20/X55/X73/X65/X72/X27/X73/X20/X47/X75/X69/X64/X65/X22/X20/X66/X6F/X72/X20/X64/X65/X74/X61/X69/X6C/X73/X2E /X31/X2E/X20 /X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29 /X32/X2E/X20 /X20/X28/X31/X2E/X31/X30/X20/X6D/X6D/X20/X7E/X20/X31/X2E/X32/X30/X20/X6D/X6D/X29 /X31 /X32 /X30/X2E/X30/X33/X20/X6D/X6D /X31/X2E/X20/X50/X61/X79/X20/X61/X74/X74/X65/X6E/X74/X69/X6F/X6E/X20/X74/X6F/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X77/X69/X64/X74/X68/X20/X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29/X2E /X32/X2E/X20/X44/X6F/X20/X6E/X6F/X74/X20/X77/X69/X64/X65/X6E/X20/X74/X68/X65/X20/X6C/X61/X6E/X64/X20/X70/X61/X74/X74/X65/X72/X6E/X20/X74/X6F/X20/X74/X68/X65/X20/X63/X65/X6E/X74/X65/X72/X20/X6F/X66/X20/X74/X68/X65/X20/X70/X61/X63/X6B/X61/X67/X65/X20/X28/X31/X2E/X31/X30/X20/X6D/X6D/X20/X74/X6F/X20/X31/X2E/X32/X30/X20/X6D/X6D/X29/X2E /X31/X2E /X32/X2E/X20 /X28/X31/X2E/X31/X30/X20/X6D/X6D/X20/X7E/X20/X31/X2E/X32/X30/X20/X6D/X6D/X29 /X28/X30/X2E/X32/X35/X20/X6D/X6D/X20/X6D/X69/X6E/X2E/X20/X2F/X20/X30/X2E/X33/X30/X20/X6D/X6D/X20/X74/X79/X70/X2E/X29

Disclaimers (Handling Precautions) 1. All the information described herei n (product data, specifications, figur es, tables, programs, algorithms and application circuit examples, etc.) is cu rrent as of publishing dat e of this document and is subject to change without notice. 2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of any specific mass-production design. SII Semiconductor Corporation is not responsible for damages caused by the reasons other than the products or infringement of third-party intellectual property rights and any other rights due to the use of the information described herein. 3. SII Semiconductor Corporation is not responsible for da mages caused by the incorrect information described herein. 4. Take care to use the products described herein within their specified ranges. Pay special attention to the absolute maximum ratings, operation voltage range and electrical characteristics, etc. SII Semiconductor Corporation is not re sponsible for damages caused by failu res and/or accidents, etc. that occur due to the use of products outside their specified ranges. 5. When using the products described herei n, confirm their applicatio ns, and the laws and regulat ions of the region or country where they are used and verify suitability, safety and other factors for the intended use. 6. When exporting the products described herein, comply with the Foreign Exchange and Foreign Trade Act and all other export-related laws, and follow the required procedures. 7. The products described herein must not be used or prov ided (exported) for the purposes of the development of weapons of mass destruction or militar y use. SII Semiconductor Corporation is not responsible for any provision (export) to those whose purpose is to develop, manufactur e, use or store nuclear, biol ogical or chemical weapons, missiles, or other military use. 8. The products described herein are not designed to be used as part of any device or equipment that may affect the human body, human life, or assets (such as medical equi pment, disaster prevention sy stems, security systems, combustion control systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment, aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do not use those products without the prior written permission of SII Semiconductor Corporation. Especially, the products described her ein cannot be used for life support dev ices, devices implanted in the human body and devices that directly affect human life, etc. Prior consultation with our sales office is required when considering the above uses. SII Semiconductor Corporation is not responsible for damages caused by unauthorized or unspecified use of our products. 9. Semiconductor products may fail or malfunction with some probability. The user of these products s hould therefore take responsibility to gi ve thorough consideration to safety design including redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social damage, etc. that may ensue from the products' failure or malfunction. The entire system must be sufficiently evaluated and applied on customer's own responsibility. 10. The products described herein are not designed to be radi ation-proof. The necessary radiation measures should be taken in the product design by the customer depending on the intended use. 11. The products described herein do not affect human health under normal use. However, they contain chemical substances and heavy metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Take care when handling these with the bare hands to prevent injuries, etc. 12. When disposing of the products described herein, comply with the laws and ordinances of the country or region where they are used. 13. The information described herein contains copyright info rmation and know-how of SII Semiconductor Corporation. The information described herein does not convey any lic ense under any intellectual property rights or any other rights belonging to SII Semiconductor Corporation or a third party. Reproduction or copying of the information described herein for the purpose of disclosing it to a thir d-party without the express permission of SII Semiconductor Corporation is strictly prohibited. 14. For more details on the information de scribed herein, contact our sales office. 1.0-2016.01 www.sii-ic.com